Citations refer to the original publication, not to a Scieee localized version.
Serrano Gotarredona, M. T., & Linares Barranco, B. (2000). A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation. IEEE Computer Society. https://doi.org/10.1109/ISCAS.2000.858700
Serrano Gotarredona, María Teresa, and Bernabé Linares Barranco. A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation. IEEE Computer Society, 2000. https://doi.org/10.1109/ISCAS.2000.858700.
Serrano Gotarredona, María Teresa, and Bernabé Linares Barranco. A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation. IEEE Computer Society, 2000. https://doi.org/10.1109/ISCAS.2000.858700.
Serrano Gotarredona, M. T. and Linares Barranco, B. (2000) A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation. IEEE Computer Society. Available at: https://doi.org/10.1109/ISCAS.2000.858700.
M. T. Serrano Gotarredona and B. Linares Barranco, “A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation,” IEEE Computer Society, 2000, doi: 10.1109/ISCAS.2000.858700.
@misc{serranogotarredona2000methodology,
author = {Serrano Gotarredona, María Teresa and Linares Barranco, Bernabé},
title = {A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation},
year = {2000},
publisher = {IEEE Computer Society},
doi = {10.1109/ISCAS.2000.858700},
url = {https://doi.org/10.1109/ISCAS.2000.858700}
}
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