A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation

ISCAS 2000 - IEEE International Symposium on Circuits and Systems, May 28-31, 2000, Geneva, Switzerland A Methodology for MOS Transistor Mismatch Parameter Extraction and Mismatch Simulation T. Serrano-Gotarredona and B. Linares-Barranco National Microelectronics Center (CNM), Ed. CICA, AV. Reina Mercedes s/n, 41012 SPAIN. Phone: 34-5-4239923 Fax: 34-5-4624506, E-mail: bemabe @ imse.cnm.es Abstract This paper presents a methodology for mismatch parameter extraction and mismatch simulation using conventional electrical simulators, like HSpice. A measurement and extraction procedure has been carefully designed to be able to obtain reliable measurements of the mismatch parameters of a given technology. The correctness of this extraction procedure method has been checked through three different validation methods. We also present two methods for performing mismatch simulation with conventional circuit simulators (like HSpice) using the extracted parameters. I. Introduction Precise analog CMOS circuit design requires availability of confident transistor mismatch models during the design and simulation stages. During the design phase of an analog VLSI circuit, designers face many constraints imposed by the design specifications, such as speed, bandwidth, noise, precision, power consumption, area consumption, which need to be traded off for optimum overall performance. Designers must rely on accurate simulation tools in order to achieve a well optimized final design. Simulation tools are reliable as long as they are based on good models obtained through confident characterization techniques. Often it is not possible to simulate properly the precision limits that can be achieved by a certain circuit topology in a given fabrication process because VLSI circuit manufacturers rarely provide transistor mismatch information. Transistor mismatch affects offset voltage of differential pairs, errors in current mirrors, errors in arrays of identical current sources, ... . Elsewhere [1],[2], we have presented a very simple and cheap methodology to characterize transistor mismatch as a function of transistor width and length plus a new five parameters mismatch model that achieves better results than other mismatch models previously reported in literature [3],[4]. In this paper, we verify the correctness of this new mismatch model and the measurementlextraction procedure through three different validation methods. Also, we present two different methods of using the experimentally extracted mismatch transistor parameters in a conventional electrical simulator, like HSpice, to predict the offset voltage of differential pairs (or whatever circuit specification we may be interested at). The simulated offset is compared versus the experimentally measured one, showing a good agreement between both. For mismatch characterization of a given technology we fabricate a special purpose chip in the corresponding technology[ 13. Our chip consists of a matrix of 8 x 8 cells. Each cell contains NMOS and PMOS transistors of 30 different sizes. Since, some transistors in the periphery present large systematic deviations with respect to those in the inner cells, only the latter transistors where considered[5]. Transistor parameter mismatches are obtained by measuring pairs of identical transistors located in adjacent cells. Since in the chip there are 6 x 6 effective cells, there are 6 rows, each of which provides 5 pairs of adjacent cells. This results in 30 adjacent transistor pairs (for each transistor size and type). For each transistor pair, four curves were measured. Two of them while operating in the ohmic region and the other two for saturation (always in strong inversion). These curves are (1) (2) Curvel:I,,(V,,) ,V,, = OV,V,,=O.l, VGse 11.5,5.01 Curve2:/,,(Vs,),V,, = 3.0V,VD, = 0.1 V,V,, E LO, 2.01 Curve3:/,S(V,,5),V,, = OV,V,, =4.0V,VG,E [1.5,5.01 (3) Curve4:1,,(VS,),V,, = 3.0V,V0, =~.OV,V,,E [O, 2.01 (4) The following strong inversion large signal transistor model is assumed [I]-[2], where, vr( vs,) = Vm + Y I &%- h I (6) and VD,,,,l is defined as, vDS, = VD.5 for ohmic region (7) V,, - V,( V,,) for saturation These curves depend nonlinearly on the large signal parameters to be extracted ( p, V,,, e,, e, and y ) as well as on the measured data points { V,, ) and { V,, ). Therefore, these large-signal parameters should be extracted using nonlinear multi-parameters curve fitting techniques. For a given transistor pair, the mismatch in the extracted large-signal parameters is obtained by fitting the current mismatch data AIDs/IDs to its theoretical equation [1]-[2], and extract from it the mismatch paramerers (Ap/p, AV,,, AB,, AB,, Ay ) simultaneously for curves 1 to 4. This measurement/extraction procedure is repeated for the N, = 30 transistor pairs. For each extracted mismatch parameter AP , its standard deviation qAP) is computed, as well as all correlations between pairs of mismatch parameters ‘(AP1.AP2) ‘ 11. Validation of the Mismatch Model In this section, we describe a few tests that we have performed to verify the correctness of our mismatch model and measurement/extraction procedure. The chip we have used for our measurements is fabricated in a standard 1.0pin double-metal single-poly CMOS technology. A. Precision Test A first test to validate our measurement procedure was to measure, repeatedly the same transistor 30 times and follow the same parameter extraction and statistical characterization 0-7803-5482-6/99/$10.00 02000 IEEE IV- 109 procedure. We obtain a set of standard deviations that give us an indication of the error of our instruments and mathematical algorithms. When measuring the parameter P mismatch between two transistors the resulting measured AP value has two components, AP = APR<"I + (9) where AP,,,, is the real mismatch in parameter P between both transistors and AP,,,,,, is an error component introduced by the measurement set-up and parameter extraction procedure. By repeating many measurements we obtain the quadratic deviation because the random transistor mismatch and the measurement errors are supposed to be uncorrelated. By repeating the same measurement over the same transistor, we measure B(~~,,,~,~,) . The values of (J(,~,,,~~,~ resulted to be less than 113 of those of a(Ap) in the worst case, and were normally below 1/10. If N, is the number of measurements of a normally distributed random variable, and these measurements are used to compute a standard deviation for this variable, a,,,,,p,,,,,~, then there is a confidence interval for the real standard deviation (JR~~I 161 t-L(Nl) oruiripr,rrd ORsol acoiii,ii!!sr/ . (I When N, = 30 the 95% confidence interval is = 0.8 , rlI = 1.3 . In our case alApl and o(~~,,,~ have been obtained by N, = 30 measurements. On the other hand, we can define a (conservative) confidence interval for r2 7 71 7, (12) (r11 ) x (J& ,,,,,) = Inax[qAPR (,, )) I = rH x a&) - r; x 0;AP ,,,( ",) .7 , -7 1, (rL) X';A/', ,,,,,) = rninla~APRen,)l = r;xa[AP)-r~lXa{AP ,,,,,, !<) By defining it follows that Fig. 1 depicts the values of and rL as a function of a when N, = 30. Note that even for values of a as high as 0.5 there is still a reasonable confidence interval for olAPRm,) (approximately + 50% ). Since, in our case, the worst case a is less than 1/3, by Fig. 1 we can see that for this worst case, the confidence interval is not significantly degraded. This kind of precision test is also called in the literature repeatability study [4]. However, with this repeata6ility study, the only thing we can conclude is that whatever has been measured, it has been measured with acceptable precision. But that does not assure that the obtained statistical mismatch parameters are a good measurement of the physical quantities qAP) and their respective correlations r(Ap,,Ap,) . To verify this, other tests have to be performed. B. Predicting a(A,D5,,os~ of the Measiired Curves the following expression is obtained, If we compute the standard deviation of a(Alns,lD,5) in eq.(8), 20 15 10 05 00 00 01 02 03 04 05 06 07 08 09 10 a Fig. 1: Plot of rk and rt as a function of a curve I. w=*m curve I. w=* CvNe 1. W.lW 2345 curre I w=*m 2515 08 06 04 2345 CvNe I w=z 4m 2 I t Fig. 2: Simulated (solid lines) and measured values (marked symbols) of a(,lnr,,Ds) for curve 1 for all transistor geometries Thus, using the extracted mismatch parameters, o,,~,~, , a(,,, , aIAy) , qA8 ), a(,e and their corresponding correlation coefTflcients, we cin compute the expected current mismatch curves Fig. 2 shows for the 30 geometries of NMOS type transistors a comparison between the measured a(,, sl,osl (marked with symbols) versus the computed ones (solid fines) for curve 1. An excellent agreement is observed for all curves 1 to 4 [2]. This is already avery good indication that we are extracting correct enough mismatch parameters. Although we are predicting the same curves we have used to extract the mismatch parameters, the set of mismatch parameters we are extracting is unique, valid for all 4 curves. However, a more severe test would be to predict other curves, obtained under different bias conditions. This is the test described next. C. Predicting Differential Pairs Offset Voltage In this section, we use the extracted statistical mismatch parameters to predict the offset voltage of differential pairs. To obtain direct measurements of differential pairs input voltage offset, for each pair of transistors in our mismatch characterization chip we measure the following curve Ios(Vc5), V,, = cre,V,, = ~.OV,V,,E [2.99V,3.01VI1 (16) once for each transistor of the pair. The measured transistor are placed in adjacent cells located 363pm apart. Fig. 3 shows the IV-110 2 990 2 995 3 000 3 oQ5 VP Fig. 3: Measured offset voltages for one air of NMOS transistors Table 1 measured points for one pair of NMOS transistors of size 40pmx40pm. Also shown in Fig. 3 are the corresponding interpolated lines of the measurements (17) IDSI(VGS) = mlVGs+nl VGs) = m2 VGs + n2 Consequently, the offset voltage for this differential pair is given by For each pair of transistors the curves of eq.( 16) were measured for two different values of V,, . First for V,, = OV (no substrate effect), and second for Vs, = 1 V (with substrate effect: AY is affecting the offset voltage). The standard deviation for these offset voltages was computed for each transistor size and type. Table 1, under the columns named “MEASURED’, indicates the measured values for o(,~~llI) as a function of transistor size and type. In order to predict the standard deviation of this offset voltage using our extracted mismatchdata, note that (see Fig. 3) where qA1 can be computed by evaluating eq.(15) in saturation, ”% lD,/s,,, can be ca@ulaid !sing the mean extracted large signal parameters (p , V,, , e, and y ). The values of qv computed this way are also shown in Table 1 under the c8hmns named “COMPUTED’. Note that the computed values stay within the confidence intervals of the measured values. 111. Mismatch Simulations The extracted mismatch parameters can be used in a conventional electrical circuit simulator, like HSpice, to predict circuit specifications such as offset voltages, error in the output current of a current mirror, etc. This can be a very valuable tool to design high performance circuits. HSpice simulations have been performed in order to predict the measured differential pairs input offset voltages of Table 1. We describe two simulation methods, both based on Monte Carlo simulations. A.Method 1: In this method the idea is to use the transistor model provided by the manufacturer and introduce into it random variations for some of the most mismatch sensitive parameters. In our case, the manufacturer model is a Level 6 Hspice model. Obviously the physical meaning of the large signal parameters (such as p , V,, , 0 and y ) is different than for the simple model we assumedduring our mismatch characterizations (eqs. (5)-(6)). Besides this, and in our particular case, the manufacturer model does not include explicitly the mobility degradation parameter “8”. Consequently, we will use only o(,glB, , qAV,,,) and qAY) and ignore all correlations. The way to use this mismatch model in (H)Spice is as follows. Each transistor in the netlist is substituted by a subcircuit call which includes a MOS transistor of the specified size and whose p , V,, , and y are recomputed by adding noise to them. If o(,~,~, , IS(^^,,) , and qA are the extracted mismatch parameters then the recomputed values for p , V,, , and y are, where CAW(.) is a normally distributed random number generation routine whose “mean” and ‘‘sigma” values have to be provided. Note that each deviation is divided by “h ”. This is because the transistor defined by eq. (20) is deviated with respect to a nominal one. The HSpice input file section that performs what describes eq. (20) is: .subckt mod-typ Drain Gate Source Bulk width=w m-mod Drain Gate source Bulk nmos w=w 1=1 .MODEL NMOS NMOS UPDATE = xxx + LEVEL = 6.0 WDEL = xxx LATD = xxx + XL = xxx + VTO = vto-n TOX = xxx BETA = betag + GAMMA = gannn=-n VBO = xxx LGAMMA= xxx +WE = xxx NWM = xxx SCM = xxx +xxx length=l .param beta-n_global-typ=xxxx .param vto-n-global-typ=xxxx .param ga”a-n-globalLtyp=xxxx .param delta-beta = agauss(0,sigma-beta.1) IV-Ill I “1, S Fig. 4: Subcircuit for mismatch simulation using Method 2 .param delta-vto = agauss(O,sigma_vto,l) .param delta-gama = agauss(0,sigma-gamma.1) .param beta-n = ‘beta-n-global-typ*(l+delta-beta)’ .param vto-n = ~vtoq-global-typ+delta-vto‘ .param gama-n = sgama-n-global-typ+delta-ganuna’ . ends Using this procedure the differential pairs input offset voltages described in the previous section were simulated for all transistor sizes, with and without substrate effect. The results are given in Table 1 under the columns named “SIMULATED (methodl)”. B. Method 2: The previous method has two problems: - The MOS transistor model provided by the manufacturer might not include some of the large signal parameters we have used, like p, V,, , e or y . The physical meaning of parameters p , V,, , 8 or y in the MOS model provided by the manufacturer (if they are present) is probably different to the one in the model we have assumed (eqs. (5)-(6)). Therefore, Method 1 is only an approximate procedure for predicting transistor mismatch, and the success of this method depends on how much the transistor model provided by the manufacturer differs from the one we have assumed. A possible alternative to overcome these problems would be to substitute each transistor in the netlist by the subcircuit depicted in Fig. 4. The subcircuit includes 3 MOS transistors and a set of controlled sources. Transistor MY,,, is a nominal transistor (without deviations) using the model provided by the manufacturer. Transistors m,,,,,, and m,,,,, are modeled using the transistor model we have assumed (eqs. (5)-(6)). Transistor m,,,,,, is a nominal transistor and transistor in,,,, is such that its p , ,VTo, e and y values are modified by adding random deviations. The voltage controlled voltage sources that bias transistors m,,,,,, and mdr,, do the function of copying the terminal voltages present at transistor The currents flowing through each transistor are sensed: I,, for M,wA,N, I, for m, ,”,,, , and l2 for mdr,, . Transistor M,,,,,, has a current source in parallel AI,, whose value at each instant is given by Note that now we can use our five mismatch parameter (Ap/p, AV,,, , AO,, , AB,, Ay ] model[l] to define the large signal parameters for . The goal is to be able to generate for each mrIr,, these 5 mismatch parameters by knowing their standard deviations and respective correlation coefficients. This can be done in (H)Spice as follows. Suppose that for each m,,*,. transistor we know its srarisrical mismarch paramerers. Suppose also, that for each m,,,, we can generate 5 random numbers { xI , x?, s3, xq, x8 ] which are uncorrelated, have zero mean, and their standard deviation is o(s,) = 1l.h. Using these five uncorrelated random numbers we can obtain five correlated mismatch parameters for ~n,,~, as follows, Where coefficients cij can be obtained by computing the standard deviations of the right and left hand side of eq. (22) [2]. The advantage of this method is that there is complete independence between the simulator model parameters that define the current through transistor M,w,,,v and our model parameters (appearing in equations (5)-(6) and that we extract experimentally for each technology) that define the currents through transistors in,,,,,, and mdr, . The effect of the additional transistors m,,,,,, and yie,, is just to add a deviation AIDs in the current passing through the basic transistor M,w,4,,v that depends on the operating point and the transistor geometry. Using this set-up, and performing Monte Carlo simulations to predict the differential pair input offset voltages for each transistor size, with and without substrate effect, results in the values shown in Table 1 under the columns named “SIMULATED (method2)”. Note that these values are more similar to those shown in Table I under columns. named “COMPUTED” than the ones obtained with the first method of simulation. However, the values under “SIMULATED (method2)” and “COMPUTED” are not identical. The reason is that the coefficient Io,/g,,, of eq. (19) is computed by the simulator using the manufacturer transistor model (through transistor M,,,, ), instead of the one we have assumed (i.e., eqs. (5146)). IV. Conclusions We have designed a new five parameters mismatch model and a method to extract and statistically characterize the mismatch parameters of a given technology. We have developed three different tests in order to validate our mismatch model and measurementlextraction procedure. The first test, previously reported in literature, assures that the measurement and mathematical computations have been done with good precision. The two other designed tests verify the correctness of the mismatch model itself. In these tests, we have achieved an agreement with the experimental results that can not be obtained with the other mismatch models previously reported in literature. Finally, we have proposed two different methods to use our mismatch model as a design tool in a conventional electrical simulator. We have simulated the offset voltage of a differential pair with our two methods and compared it versus the experimentally measured one. A very good agreement between simulations and measurements have been obtained. V. References T. Semno-Gotarredona and B. Linares-Barranco. “Systematic Width-and-Length Dependent CMOS Transistor Mismatch Characterization and Simulation,” Journal of Analog Integrared Circuits and Signal Processing, December 1999. T. Serrano-Gotarredona and B. Linares-Barranco, “A New Five-Parameter MOS Transistor Mismatch Model,” IEEE Electron Device Lerters, pp 37-39, vol. 21, January 2000. M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching Properties of MOS Transistor,” IEEE Journd of Solid-State Circuits, vol 24, October 1989, pp. 1433-1440 J. Bastos, Cliaracterizution of MOS Transistor Misinarch .for Analog Design, Ph.D. Dissertation, Katholieke Univeristeit Leuven, April 1998. A. Pavasovic, A. G. Andreou, and C. R. Westgate, “Characterization of Subthreshold MOS Mismatch Transistors for VLSI Systems,‘’ Analog hiregruted Circuits and Signal Processing, vol. 8, pp. 75-85, 1994. Lennart Rade and Bertil Westergren, BETA Marheinatics Handbook. CRC Press, 1990. IV-112