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Figu e 1: Schema ics o wo implemen a ions o
a NAND ga e
('5!#)(
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Figu e 2: Pa asi ic diodes in a CMOS in e e
)$ *
7+++"!("
"!,7"61-*+,7"2
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Figu e 3: Layou o a COBO NOR ga e
Figu e 4: Layou o an INBO NAND ga e
Figu e 5: Layou o a COBO NAND ga e
Figu e 6: Layou o an INBO NOR ga e
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Figu e 7: PLH e sus an ou o he COBO
and INBO NAND ga es
Figu e 8: PHL e sus an ou o he COBO
and INBO NOR ga es
Figu e 9: PLH e sus an ou o he COBO
and INBO NOR ga es
Figu e 10: PHL e sus an ou o he
COBO and INBO NAND ga es
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&
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&
6, - EE;0 BE12 F1E; A;2;
&
1, - 00;1 09;B BB9F F;6;
Table 1: Powe consumed when he COBO NOR
ga e ecei es an inpu pulse
*$"!
*9*0*;*6
& 0
, - A919 2F0F 1AA9 62FF
& ;
, - F669 AE60 A9AB 292E
&
6, - B219 B0A1 F1;6 AAFA
& 1
, - EB26 E1EA BA22 FB0B
Table 2: Powe consumed when he INBO NOR
ga e ecei es an inpu pulse
*$"!
*9*0*;*6
& 0
, - ;FFF ;1;1 ;09B 0FEA
& ;
, - 6;2F ;BE2 ;2;F ;;6A
& 6
, - 6AEA 661A 69;6 ;F90
& 1
, - 1;9E 6B1; 6200 60A;
Table 3: Powe consumed when he COBO NAND
ga e ecei es an inpu pulse
*$"!
*9*0*;*6
&
0, - ;A61 ;6E6 ;9BA 0FE0
&
;, - 60A2 ;E;0 ;A;E ;60F
&
6, - 6AAB 6161 60AA ;B62
&
1, - 1;;A 6EA9 6F91 66E;
Table 4: Powe consumed when he INBO NAND
ga e ecei es an inpu pulse
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5! $ & $# ++ +
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++ +
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Table 5: S a ic powe consump ion when he se-
ies ee is conduc ing
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Figu e 11: S a ic powe o he NAND ga es
when he se ies ee is no conduc ing
Figu e 12: S a ic powe o he NOR ga es when
he se ies ee is no conduc ing
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#" ' " ! As men-
ioned, hese imp o emen s a e ob ained a he expense o
a ea, bu he p oposed ga es a e no in ended o eplace he
adi ional ones in he whole design. By using he p o-
posed app oach jus in c i ical pa hs, nodes wi h high
swi ching ac i i y o when a ga e wi h a la ge numbe o
inpu s is equi ed, he speed and powe consump ion o
he sys em can be imp o ed while keeping a ea unde con-
ol.
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@',0EE6-
01248356910127111314
0
20
40
60
80
100
120
140
Inpu ec o
Powe (pico wa s)
COBO
INBO
15 141311 7 1210 9 6 5 3 8 4 2 1
0
5
10
15
20
25
30
35
Inpu ec o
Powe (pico wa s)
COBO
INBO