Delay and power consumption of static bulk-CMOS gates using independent bodies
Abstract
Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages obtained can justify its utilization in selected parts of the circuits. This is discussed in this paper.
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#" ' " ! As men-
ioned, hese imp o emen s a e ob ained a he expense o
a ea, bu he p oposed ga es a e no in ended o eplace he
adi ional ones in he whole design. By using he p o-
posed app oach jus in c i ical pa hs, nodes wi h high
swi ching ac i i y o when a ga e wi h a la ge numbe o
inpu s is equi ed, he speed and powe consump ion o
he sys em can be imp o ed while keeping a ea unde con-
ol.
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