Delay and power consumption of static bulk-CMOS gates using independent bodies
Abstract
Digital designs implemented using SOI processes employ separated bodies for each transistor. This approach is not usually considered in digital bulk-CMOS design because of its obvious area penalty. However, the advantages obtained can justify its utilization in selected parts of the circuits. This is discussed in this paper.
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!"#$ !%&'()&) !" ((&*+% (,() &&(((,&-%./*(,% &,&)01(% ,(2&&3( &)(&() #$ ! ""# ! #$ "$"%$%"! #&'# !#$" ()%$*()%$!(' +%% #"!# $$# !( %!$ $!,&!$!&&$ # #'-! !#''! !#('$.$!' #! $(' $/0123!!$$$ $&!!$('"4(5! $$(#$ !!! "4!$('"4(/635! #$ ()%"" #$'!#( $! (' $!$$$$$ $$5!!&7" 08* !"$0*9 :# " ! $$ +%$"*0*;*6& #$$$$ $ !!"&"! #$ !" 5!#( $('!(' $ &!$! $!" ! ' &'"!,(12< "- ' $ $$$ $ 7"0& $"' !'&$# !"5!' "!#)!$$"$ #$#:#! !" *%*,%$*-$! #( "#$! Figure 1: Schematics of two implementations of a NAND gate ('5!#)( ! (' $ =) %* $ ()% &&&$!"#)( ( $!+%% "$">&!(' " ( $!!' $'($()%"$"($ ! $!5! (' : !$!&!$!&&$*+ , *-5!!#) 4(?9('$$"!$('# ! !,7"0(- *!! #$ (!$!$# *! &"$!(! "" (&('*$!! ' !"!$#&( %$ &!&!#( ''#$$&$# $&(##!$
%$ !&"&' ( $"$!('!$"$! &#)($.$8 •5!$('$$$$$$ ("$7!#('$$ $$!$!"' #$!"&"$$# "$!"('$$$$ $!"&">&!(' ($$$$ $"' #$ •%$4(?9 '!(' $ $$$# @!$$&$#!&# $%"/238 •()"$ •%(!!$$ 5! $:('!:$ $ %"$!!!&7" ;$!$ #$! $!$# ! &"!!$ "!$#$( ("()"$! $(!$&$# 5!$$ $&$#!$ $' %("$#'. &!!""$!4>$ $&(!!$ & #'"5!$4 !*+ "$$!(!!$$(! ('!&! # ! )" $ Figure 2: Parasitic diodes in a CMOS inverter )$ * 7+++"!(" "!,7"61-*+,7"2 A-'$#! #$(' $$# $:$5!'! ( ## " 90B C# & % $&!&?;19#&?;19# ++&?;19#&?0119# + ###"!*#*9*0*;*6&! :$" ! Figure 3: Layout of a COBO NOR gate Figure 4: Layout of an INBO NAND gate
Figure 5: Layout of a COBO NAND gate Figure 6: Layout of an INBO NOR gate D"($'$#)( !&!$#!. ##"$##('5!! ## !+++") 01;C#; 0EAC#;&!!*+$ )16FC#;1B2C#;$' *$("! !$$ (#$!! *+$ #!$$$(!&$ !$$$!""&(& &$##"'!!!! $$$ !*+$$&! $$!"" "' $ $!( $$"!"('$$$&( $!"&" 5!:$&!&!'$ '#$&$# $!##( ('$$#5!#!( $ $:$"!>%*/;3 $$#&!!#$('! '#'" 0B4, #01!($- +$ , +$#$ 5!' (!+++"$( (7"FBE09$!"!!&! " ' $! ! "*!$!!$('$ $$$$!(#!: $"('($$$ "$#"!!!"( !$'8!$$$! "!"#'!&$ #!$G* $!#) ('$"!*+' #!$5!' *6,!! -#*+"($ $$$$ #$!$8 !''$!" &!!! ++", !+-!'&! ! !++",!+-7 ! !$$$$($## !*+'( #$ 5!&"!('##! '#!#""! &!!*+'5!+"$'( #!*+'""'## !$* &$#!=>' !& ,*9- (!##&&$ E<!++" 0&!! +"=> $(';2< !# 5!!(" "&!#
Figure 7: tPLH versus fan out of the COBO and INBO NAND gates Figure 8: tPHL versus fan out of the COBO and INBO NOR gates Figure 9: tPLH versus fan out of the COBO and INBO NOR gates Figure 10: tPHL versus fan out of the COBO and INBO NAND gates
+$%$ 5(0;!&#)(!$#! &$# !*++"$' !$#"#&5!"'$# &!*9 ,!$#"# &-$(';;<*!++$ ! !!!$##5!! $#"#&!&$ 2< 0&!!&$('92< 1,(61- *$"! *9*0*;*6 & 0, - FAA1 A2BE 200F 6B9; & ;, - BB0A FFF; A1;2 1E;B & 6, - EE;0 BE12 F1E; A;2; & 1, - 00;1 09;B BB9F F;6; Table 1: Power consumed when the COBO NOR gate receives an input pulse *$"! *9*0*;*6 & 0 , - A919 2F0F 1AA9 62FF & ; , - F669 AE60 A9AB 292E & 6, - B219 B0A1 F1;6 AAFA & 1 , - EB26 E1EA BA22 FB0B Table 2: Power consumed when the INBO NOR gate receives an input pulse *$"! *9*0*;*6 & 0 , - ;FFF ;1;1 ;09B 0FEA & ; , - 6;2F ;BE2 ;2;F ;;6A & 6 , - 6AEA 661A 69;6 ;F90 & 1 , - 1;9E 6B1; 6200 60A; Table 3: Power consumed when the COBO NAND gate receives an input pulse *$"! *9*0*;*6 & 0, - ;A61 ;6E6 ;9BA 0FE0 & ;, - 60A2 ;E;0 ;A;E ;60F & 6, - 6AAB 6161 60AA ;B62 & 1, - 1;;A 6EA9 6F91 66E; Table 4: Power consumed when the INBO NAND gate receives an input pulse +$)$ 5! $ & $# ++ + " !((!*+ '!(#('$$# 5!$#(!!#( $!$,*6*;*0*9-*6;6H*;;;H *0;0H*9;95!$2 :#$ ,*6*;*0*9-?,9090-@!!$$ "!" $!('!#!*+ ##!$&$# ',(2- ++ + *$ 02 9 $& $# FA0@ 1B62@ *+$& $# FA9@ 1B62@ Table 5: Static power consumption when the series tree is conducting @!!$$"!!! !*+$!!&&$&$# #'!&7"000; 5!$!(""! #( $!7# " !!!#$( (!!$7#""! #($ $!# $ !$!$&(!' " ,*+-%$&*+"# $ " &! " $' "5!!!'! $ $# &! " & ! #( ($$" $G#5!#('!# ( !$$! ('$!5!!++"! $0;,*6*;*0*9?0099-#)'!$ 09,*6*;*0*9?0909-$ ! $! !(&! !$$ !'&*$E09&( )!62A$!'!
$$!(* !*+++"!!!!$ ('$$("$$$ ('$$"!!(' $(($!&$ $",:$!$" *9-5!$) )"$!*+" #)!#)'!!$ #!$!&!'$& $##$$!" #!!*+" ($$$($!' #! (' $5! $&!!' $ !5!(&! $ !!($$$! *+!!$5!&!'!*+ ++"() $F0006 01&!!*++""!') $B Figure 11: Static power of the NAND gates when the series tree is not conducting Figure 12: Static power of the NOR gates when the series tree is not conducting "!$&!!#(( '!$&" 2<!++ $"!*+'*!+$!" $&"(09<"!*+ ' -$ & $!" ($# ## ! (,*+- $! $%"$("#)( #$ ##'#$$&$ # &! $# ! $ $## ('$!,-*+"!&#! #" ' " ! As mentioned, these improvements are obtained at the expense of area, but the proposed gates are not intended to replace the traditional ones in the whole design. By using the proposed approach just in critical paths, nodes with high switching activity or when a gate with a large number of inputs is required, the speed and power consumption of the system can be improved while keeping area under control. .$ ! 5!&)!('('!' $ ! %! # !"! ! 5;99FA0B9;G* ,>*- $ ! " #I J;992 5*09;6$ /$ , /03 KK+#L# $"$' &"""L$ " B!** $$$ $%'#,*%-4601;001;1 ,;990- /;3 %''*$04+.&(5 6&(,;996- /63 5M*(/(/*% $&>,0EBF- /13 4$)>%&,./*+.K&$ #$(!5>"%#5! +!,;999- /23 @+!"!K4./*78+ @',0EE6- 01248356910127111314 0 20 40 60 80 100 120 140 Input vector Power (pico watts) COBO INBO 15 141311 7 1210 9 6 5 3 8 4 2 1 0 5 10 15 20 25 30 35 Input vector Power (pico watts) COBO INBO