IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 1
A 0.9-V 100-µW Feed o wa d Adde -Less
In e e -based MASH ∆Σ Modula o wi h 91-dB
Dynamic Range and 20-kHz Bandwid h
Mohammad Hona pa a , S uden Membe , IEEE, Jos´
e M. de la Rosa, Senio Membe , IEEE,
and Mohamad Sawan, Fellow, IEEE
Abs ac —A 0.9-V ∆Σ modula o in eg a ed in a 0.18-µm
CMOS echnology o digi izing signals in low-powe de ices is
p esen ed in his pape . To do so, a cascade (MASH) a chi ec u e
based on an adde -less eed o wa d s uc u e is p oposed. The
p oposed modula o has a uni y signal ans e unc ion in bo h
s ages o he modula o in o de o educe he in eg a o s ou pu
swings. To mi iga e he ailu e o slow p ocess co ne in he weak
in e sion as well as o u he diminish he powe consump ion
o he p esen ed modula o , a ully di e en ial sel and bulk
biased (SBB) in e e -based OTA is p oposed. Expe imen al
esul s a e shown o demons a e he e iciency o he p oposed
∆Σ con e e , showing s a e-o - he-a pe o mance, by ea u ing
88.7-dB SNR, 86.4-dB SNDR and 91-dB DR wi hin a signal
bandwid h o 20-kHz, wi h a powe dissipa ion o 103.4-µW
when he ci cui is clocked a 5.12-MHz.
Index Te ms—Analog- o-digi al con e sion, del a-sigma mod-
ula ion, swi ched-capaci o ci cui s, in e e -based OTAs.
I. INTRODUCTION
THE need o hand-held de ices, sma -phones and medi-
cal implan able mic oelec onic sys ems, is ema kably
g owing up. Howe e , keeping all hese elec onic de ices
powe op imized is one o he main challenges due o he
lack o li e- ime ba e ies u ilized o powe hem up. One
o he mos c i ical building blocks o such de ices is he
analog- o-digi al con e e (ADC), since i needs o e icien ly
digi ize acqui ed signals in a hos ile en i onmen . Compa ed
o o he ADC echniques, Del a-Sigma Modula o s (∆ΣMs)
ha e been widely used in hose de ices due o he unique
ea u es hey o e and hey a e capable o being e ec i ely
powe op imized a bo h a chi ec u al and ci cui le els [1]-
[2]. Ne e heless, special ca e mus be aken in o accoun o
op imize he pe o mance o ∆ΣMs. Indeed, many s a e-o -
he-a high- esolu ion (>14-bi ) low-bandwid h (<25-kHz)
∆ΣMs ha e been epo ed, including single-s age a chi ec-
u es [3]-[4] and cascade opologies – also e e ed o as Mul i
s Age noiSe sHaping (MASH) [1]-[5]. Among o he ∆Σ loop-
il e opologies, he so-called eed o wa d (FF) s uc u e has
M. Hona pa a and M. Sawan a e wi h he Polys im Neu o ech Lab,
Depa men o Elec ical Enginee ing, Poly echnique Mon eal, Mon eal, QC,
Canada, H3T 1J4, e-mail: mohammad.hona pa [email p o ec ed].
J.M. de la Rosa is wi h Ins i u o de Mic oelec onica de Se illa, IMSE-
CNM, CSIC/Uni . de Se illa, Se illa, Spain.
The au ho s acknowledge he Na ional Sciences and Enginee ing Resea ch
Council o Canada o he suppo and CMC Mic osys ems o he design
ools. This wo k was also pa ially suppo ed by he Spanish Min. o Econ.
and Comp. (suppo ed by Eu opean RDF) unde con ac TEC2016-75151-
C3-3-R.
been success ully used by some designe s o implemen single-
s age high-o de ( hi d-o de o mo e) noise shaping [6]-[7].
Howe e , he main limi a ion o FF s uc u es is he powe -
hung y adde equi ed a he inpu o he quan ize . This
adde cons i u es one o he main design bo lenecks o FF
∆ΣMs employed in ADCs, whe e he ene gy consump ion
becomes c i ical. In o de o mi iga e his limi a ion, some
au ho s ha e p oposed al e na i e implemen a ions o he
FF loop- il e . Thus, he ∆ΣM epo ed in [6] includes a
ou h-o de FF loop- il e wi h a passi e adde . Howe e , his
echnique su e s om bo h educ ion o signal swing a he
inpu o he compa a o , and misma ch be ween capaci o s.
A simila s a egy has been adop ed in [7], whe e a 1.5-bi
(3-le el), ou h-o de FF s uc u e is p oposed o digi izing
signals wi h a 20-kHz bandwid h. Ano he app oach consis s
o using swi ch ma ix eedback compensa ion based on a
di ec summa ion echnique as p oposed in [8]. While such
echnique is well-sui ed o mul i-bi quan ize s, i is no
applicable o single-bi ∆ΣMs. Mo eo e , employing mul i-
bi quan ize s in high- esolu ion applica ions is limi ed by
he inhe i ed nonlinea i y o he DAC used in he eedback
pa h o he ∆Σ modula o . This equi es using linea iza ion
echniques, such as dynamic elemen ma ching (DEM), which
ob iously leads o inc easing he ci cui complexi y as well
as he powe consump ion. Simila FF opologies ha e been
add essed in [9]-[10] whe e he las in eg a o se es as an
in eg a o and an adde simul aneously. Howe e , an ex a
DAC in he eedback pa h is needed o e ie e he noise
ans e unc ion (NTF) o he modula o . I is wo h no ing
ha in all abo e-men ioned opologies, an ex a DAC is
equi ed o ex ac he quan iza ion noise i hey a e supposed
o be used in a MASH con igu a ion and hence adds ci cui
complexi y.
Apa om he s a egies o op imize he pe o mance o
∆ΣMs a sys em le el, an impo an e o should be pu
also a ci cui le el. Scaling o CMOS echnologies b ings
signi ican imp o emen s in e ms o unc ionali y, speed, size,
o m ac o and powe consump ion o he digi al ci cui s.
Howe e , such an agg essi e p ocess scaling comes along wi h
he educed supply ol age o ensu e he p ope unc ionali y
o he de ice and educes he in insic gain o CMOS ansis-
o s. The men ioned cons ain s make he design o he analog
building blocks, e.g. ope a ional ansconduc ance ampli ie s
(OTAs), in a ∆Σ con e e e y challenging such ha i limi s
he applica ion o he adi ional OTA opologies [11]. On
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 2
he o he hand, a lowe supply ol age educes he ol age
head oom and he a ailable signal swing. This esul s in he
dynamic ange being limi ed by he mal noise. I also con ines
he choice o ci cui a chi ec u es. Besides he men ioned
d awbacks, biasing a ci cui in he weak in e sion, o minimize
he powe dissipa ion, is s ill o in e es . Howe e , such a
biasing egion makes he ci cui se e ely suscep ible o he
p ocess a ia ions due o luc ua ions in MOS pa ame e s
and i may decay he pe o mance o a complex sys em like
∆Σ con e e s. Ha ing discussed om ha poin o iew,
no only is an app op ia e OTA opology needed, bu p ope
emedy mus be aken when biasing he OTA in he weak
in e sion [12].
This pape con ibu es o imp o e he pe o mance o FF
∆ΣMs by explo ing wo app oaches a he a chi ec u al and
ci cui le els, in o de o mi iga e he men ioned p oblems o
ealize a high-e iciency, high- esolu ion ∆ΣM, which co e s
he audio band (20-kHz) in a sub-1V en i onmen using a
0.18-µm CMOS echnology. To his end, a ou h-o de adde -
less MASH ∆ΣM ope a ing a 0.9-V is p esen ed in his wo k
as an ex ension and imp o ed e sion o he pape p esen ed
by he au ho s in [11]. Al hough he al e na i e s u dy MASH
s uc u e based on he adde -less FF loop- il e , p oposed
in [13], elaxes he OTA DC-gain equi emen , i will be shown
ha only a DC-gain o 50 dB is su icien o he p oposed
MASH s uc u e. The e o e, he main ocus o his wo k a he
ci cui le el is o keep he OTA s uc u e as simple as possible
and powe e icien . A ully di e en ial SBB in e e -based
OTA, ope a ing in he weak in e sion, is he e o e p oposed
o implemen he in eg a o s o he p oposed ∆ΣM. I is shown
ha he p oposed OTA is obus agains slow co ne s and low
supply ol age.
The pape is o ganized as ollows. Sec ion II desc ibes he
p oposed ∆ΣM a chi ec u e and some sys em-le el design
conside a ions. High-le el syn hesis, analysis and op imiza ion
a e add essed in Sec ion III. Sec ion IV demons a es he
ci cui le el implemen a ion o he p oposed ∆ΣM including
SBB in e e -based OTA, swi ches and compa a o . Expe i-
men al esul s a e gi en in Sec ion V and inally a conclusion
is d awn in Sec ionVI.
II. PROPOSED ADDER-LESS MASH FF ∆ΣM
As men ioned in he in oduc ion, FF ∆ΣM is a well-
sui ed opology o implemen low- ol age low-powe ∆ΣMs.
Howe e , he key bo leneck o he FF s uc u e is he adde
be o e he quan ize , which could be ealized ei he using
ac i e o passi e ci cui s. Al hough an ac i e adde , which
allows o an accu a e summa ion, is mo e eliable, a as
powe -hung y OTA needs o be ealized in o de o inco po a e
in o he ac i e adde . Al e na i ely, a passi e adde can be
used. Al hough such echnique is well-sui ed o low-powe
applica ions, signal swings and he quan ize inpu s ep a e
deg aded due o he pa asi ics [3]. In addi ion, he quan ize
kick-back noise as well as capaci o misma ches may se e ely
deg ade he o e all signal o noise plus dis o ion a io (SNDR)
o he modula o . Finally, he a ea occupied by passi e ci cui
elemen s may impose signi ican es ic ions [14].
Fig. 1. Adde -less FF ∆ΣM wi h single (mul i)-bi quan ize .
Fig. 2. Quan iza ion e o ex ac ion: con en ional me hod ( ed) and p oposed
me hod used in he adde -less FF ∆ΣM (blue).
A. Adde -less Single-s age Feed o wa d A chi ec u e
1) Dynamic Beha io o he Adde -less ∆ΣM: The ap-
p oach o o e come he a o emen ioned p oblem is o pe o m
he signal summa ion a he inpu o he las in eg a o ins ead
o he quan ize inpu , as depic ed in Fig. 1. In o he wo ds,
he las in eg a o is sha ed o se e as an in eg a o and as an
adde simul aneously. Consequen ly, bo h he ci cui complex-
i y and he powe consump ion can be educed. Wi hou loss
o gene ali y, all coe icien s a e assumed o be se o uni y
in Fig. 1, i.e. b1= 1 and ai= 1,i= 1,2,3,4. In his case,
he NTF and STF o he modula o can hus be espec i ely
w i en as ollows:
NT F (z) = (1 −z−1)
(1 −z−1) + z−1·I2(z)·(1 + G(z)) (1)
ST F (z) = z−1·I2(z)·(1 + G(z)) + H(z)·I2(z)
(1 −z−1) + z−1·I2(z)·(1 + G(z)) (2)
Compa ing (1) and (2) o ha o he con en ional second
o de FF s uc u e wi h an NT F (z) = (1 −z−1)2,I2(z),
G(z)and H(z), as depic ed in Fig. 1, a e conside ed o ha e
a second-o de noise shaping as well as a uni y STF as ollows.
I is wo h no ing ha any a bi a y NTF can be mapped on o
he ∆ΣM in Fig. 1, esul ing in di e en coe icien alues.
I2(z) = 1
(1 −z−1)(3)
G(z) = H(z)=1−z−1(4)
I is aluable o w i e he in eg a o ou pu s o he adde -
less modula o , depic ed in Fig. 1. As can be seen om (5)
and (6), he i s in eg a o p ocesses he quan iza ion noise
while he ou pu o he second in eg a o includes he inpu
signal componen . No e ha any non-ideali ies caused by he
second-o de in eg a o a e shaped by he loop- il e , so ha
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 3
hese non-ideali ies do no se e ely in luence he pe o mance
o he modula o .
V1(z) = −z−1·(1 −z−1)·E(z)(5)
V2(z) = X(z)−z−1·(1 −z−1)·E(z)(6)
2) Quan iza ion E o Ex ac ion o he Adde -less ∆ΣM:
The con en ional me hod o ex ac he quan iza ion e o in
a MASH ∆ΣM is o sub ac he quan ize ou pu om he
quan ize inpu , as shown in Fig. 2. Howe e , such an app oach
exace ba es he complexi y o he quan iza ion e o ex ac ion,
especially when he numbe o quan ize le el inc eases. This
is due o he ac ha he quan ize ou pu is ep esen ed in
he mome e code and a mul i-bi swi ched capaci o (SC)-
DAC is needed o pe o m such a sub ac ion.
As shown in [15], [16], a delayed e sion o he quan iza ion
e o is a ailable a he ou pu o he second in eg a o in he
FF opology, which makes his opology desi able o a MASH
s uc u e as well as o ex ended coun ing inc emen al ADCs.
Howe e , his is no he case in he p oposed ∆ΣM since
he quan iza ion e o is high-pass il e ed a he ou pu o he
i s in eg a o and he second in eg a o p ocesses bo h he
inpu signal and he quan iza ion e o as well. Fo una ely,
he quan iza ion e o is a ailable in he p oposed a chi ec u e
i he signals a di e en nodes o he modula o a e p ope ly
aced. Se ing all coe icien s a uni y- o simpli y he analysis-
esul s in a second-o de NTF i.e. NT F (z) = (1−z−1)2and
he ou pu o he second in eg a o , V2(z), can be exp essed
as a unc ion o inpu signal, X(z), and i s in eg a o ou pu ,
V1(z)as ollows:
V2(z) = X(z) + 2−z−1
1−z−1·V1(z)(7)
Subs i u ing (5) and (7) in exp ession (8) shows ha wi h
p ope combina ion o he inpu signal o he modula o , X(z),
and he ou pu o he i s and second in eg a o s (V1(z)and
V2(z)), a delayed e sion o he quan iza ion e o can be
ex ac ed in he adde -less FF opology, yielding:
X(z) + V1(z)−V2(z) = z−1·E1(z)(8)
whe e E1(z)is he quan iza ion e o o he on -end s age.
B. P oposed Adde -less MASH Feed o wa d A chi ec u e
In o de o ensu e a high pe o mance powe op imized
∆ΣM, i s sys em-le el pa ame e s, i.e. he o de o he loop-
il e , he OSR and he numbe o bi s o he embedded
quan ize , mus be ca e ully de e mined. Mo eo e , he se-
lec ion be ween a single-s age and a MASH s uc u e is
ano he impo an decision o make. Inc easing he quan ize
esolu ion leads o inc easing he SNDR o he modula o a
he expense o ci cui complexi y and powe consump ion.
Mo eo e , linea iza ion echniques a e equi ed o supp ess
nonlinea beha io o he eedback DAC. To ge id o hese
p oblems, a single-bi quan ize is conside ed in his design.
Al hough a highe SNDR can be achie ed wi h a highe
o de modula o , i makes he modula o suscep ible o ins a-
bili y. Single-bi quan ize e en exace ba es he s abili y issue.
Al e na i ely, a MASH ∆ΣM is a sui able solu ion in which
Fig. 3. Sys em-le el diag am o he p oposed adde -less MASH ∆ΣM.
he o de o he modula o can be inc eased by cascading low-
o de ( ypically i s -o de and second-o de ) s ages, which
a e inhe en ly s able, and hence he o e all ∆ΣM s uc u e
is s able [17]. Based on hese conside a ions, a MASH ∆ΣM
wi h single-bi quan ize is chosen in his wo k.
In o de o de e mine he OSR and he o de o he modula-
o , an ex ensi e analysis, ine uned by beha io al simula ion,
is ca ied ou o maximize he SNDR o he ∆ΣM wi h he
minimum powe consump ion. As depic ed in Fig. 3, a ou h-
o de MASH s uc u e ∆ΣM (MASH 2-2), which consis s o
he wo s ages second-o de adde -less ∆ΣMs wi h a single-
bi quan ize , is conside ed o his design. No e ha he
quan iza ion e o is ex ac ed as desc ibed in he p e ious
sec ion and he explici adde a he inpu o he second s age
is o illus a i e pu poses only. In a p ac ical implemen a ion,
all signals a e summed up a he inpu o he hi d and ou h
in eg a o s, as will be de ailed in Sec ion IV. An OSR o
128 wi h he sampling equency o 5.12 MHz is selec ed o
make he p oposed modula o ope a e o e a 20-kHz signal
bandwid h.
Assuming he NTF o (1 −z−1)2 o each s age o he
p oposed ∆ΣM, he ou pu o he i s and second s age can
be espec i ely exp essed as:
Y1(z) = X(z) + (1 −z−1)2·E1(z)(9)
Y2(z) = z−1·E1(z) + (1 −z−1)2·E2(z)(10)
and he o e all z-domain ou pu signal o he p oposed ∆ΣM
is gi en by:
YP oposed−MASH (z) = Y1(z)·H1(z) + Y2(z)·H2(z)(11)
whe e H1(z)and H2(z)a e he digi al cancella ion logics
(DCLs) o cancel he quan iza ion e o o he i s s age i.e.
E1(z).Y1(z)and Y2(z) ep esen he ou pu s o he i s and
second s ages, espec i ely. Assuming H1(z) = −z−1and
H2(z) = (1 −z−1)2, he quan iza ion e o o he i s s age,
E1(z), is ideally cancelled, while E2(z)is shaped by a ou h-
o de NTF.
III. HIGH-LEVEL SYNTHESIS
The analysis p esen ed abo e conside s ideal ∆ΣM building
blocks. Howe e , his ideal pe o mance deg ades in p ac ice
by he ac ion o ci cui e o mechanisms [18]. A de ailed
analysis o he main nonideali ies is he e o e necessa y in
o de o se he elec ical speci ica ions o he ∆ΣM sub-
ci cui s and o op imize hei design.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 4
(a) (b)
(c) (d)
(e) ( )
Fig. 4. In eg a o ou pu swing (no malized o he ∆ΣM ull scale) e sus
inpu signal le el: (a) Single-bi modula o syn hesized h ough an NTF o
(1 −z−1)4and be o e scaling, (b) Single-bi modula o h ough an NTF
o (1 −z−1)4and a e scaling, (c) 1.5-bi modula o syn hesized h ough
an NTF o (1 −z−1)4and be o e scaling, (d) 4-bi modula o syn hesized
h ough an NTF o (1 −z−1)4and be o e scaling, (e) Single-bi modula o
syn hesized h ough an NTF wi h an ou -o -band gain o 1.5(Hin = 1.5)
and be o e scaling, ( ) Single-bi modula o syn hesized h ough an NTF wi h
an ou -o -band gain o 1.5(Hin = 1.5) and a e scaling.
A. Modula o Loop Fil e Coe icien s Scaling
The p oposed adde -less MASH ∆ΣM, depic ed in Fig. 3,
is syn hesized wi h an NTF o (1 −z−1)4, and all loop coe -
icien s a e ini ialized o one, while he ou pu swing o each
in eg a o is no conside ed. The e o e, i is mo e likely ha
he in eg a o s will be sa u a ed in an ac ual implemen a ion
i he ou pu ol age le el becomes c i ically la ge. Mo eo e ,
dis o ion, which de e io a es he pe o mance o he ∆ΣM, is
he majo consequence o he sa u a ed in eg a o s. The e o e,
i is bene icial o obse e he in eg a o ou pu swings and o
p ope ly scale he coe icien s o he modula o in o de o
gua an ee a easonable signal swing a each in eg a o ou pu .
This esul s in a educed powe consump ion and an imp o ed
dynamic ange (DR).
Beha io al simula ions a e ca ied ou o moni o he ou pu
swing o all in eg a o s e sus inpu signal le el, as shown in
Fig. 4. Fig. 4(a) shows he ou pu swing o all in eg a o s while
all coe icien s a e ini ialized o one esul ing in an o e all NTF
Fig. 5. His og am o he in eg a o ou pu swings ela i e o he FS ol age.
o (1 −z−1)4. I is clea ha he inpu o he i s in eg a o
mus be scaled down by a ac o o 8 o accommoda e
in eg a o ’s ou pu swing in sub-1-V en i onmen . This ac o
mus be la ge o he second and hi d in eg a o s. I mus
be men ioned ha la ge scaling down ac o leads o highe
in eg a ing capaci o alue o a gi en sampling capaci o , and
hence inc eased modula o powe consump ion. The ou h
in eg a o is p oblema ic as an unbounded ou pu swing is
obse ed a i s ou pu . In his condi ion he modula o ends
o be uns able. Figu e 4(b) shows he scaled modula o wi h
a ac o o 8. No e ha , e en using such a la ge scale ac o
o all in eg a o s, an unbounded ou pu swing is ob ained a
he ou pu o he ou h in eg a o . As s a ed abo e, mul i-bi
quan iza ion alle ia es his issue a he expense o equi ing
DAC linea izion echniques, wi h a esul ing penal y in powe
consump ion. Fig. 4(c) and (d) shows he ou pu swing o he
in eg a o s wi h a 1.5-bi and a 4-bi quan ize , espec i ely.
Fo he case o a 1.5bi quan ize pe s age, he modula o
s ill needs o be scaled down wi h la ge ac o s.
As a single-bi quan ize is assumed in his design, he NTF
ou -o -band gain (Hin ) is educed o 1.5and he coe icien s
o he modula o a e e-syn hesized. As shown in Fig. 4(e),
he ou pu swing o all in eg a o s a e bounded o 1be o e
scaling o he modula o . The ou pu swing o in eg a o s a e
coe icien scaling is shown in Fig. 4( ). I can be seen ha
he ou pu swings do no end o be sa u a ed e en close o an
inpu le el o 0dBFS.
The ou pu swing o he in eg a o s a e be e illus a ed in
he his og ams depic ed in Fig. 5, whe e a −6-dBFS inpu
signal le el is conside ed a e coe icien s scaling. As can
be seen om his igu e, he ou pu swings o all in eg a o s
a e wi hin 23% o he ull-scale (FS) ol age. Due o such
a elaxed head oom equi emen , a high slew- a e OTA is
no equi ed, esul ing in he abili y o design a lowe powe
ci cui . The coe icien s selec ed o he modula o a e scaling
a e summa ized in Table I.
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 5
TABLE I
COEFFICIENTS OF THE PROPOSED ∆ΣMAFTER SCALING
Coe icien a11 a12 a13 b11 c11 a21
Value 0.15 0.3 0.75 0.15 0.15 0.15
Coe icien a22 a23 b21 c21 d d1,2
Value 0.3 0.75 0.15 0.15 1 5
Fig. 6. Maximum IBN e sus in eg a ion capaci o size o he i s in eg a o .
B. Sampling Capaci o o he F on -end In eg a o
Ca e ul selec ion o he sampling capaci o , especially o
he i s in eg a o , is an impo an ask since i de e mines
he KT
Cnoise, which cons i u e he ul ima e limi ing ac o
in he noise loo o he modula o . On he o he hand, he
on -end sampling capaci o has a di ec con ibu ion on he
capaci i e load o he in eg a o and hence, on he se ling
equi emen and he powe consump ion. The p ocedu e gi en
in [17] is ollowed o de e mine he sampling capaci o o he
i s in eg a o . In his design, o he a ge signal o noise a io
(SNR) o 90 dB a −3-dBFS, he signal powe is 2
s= 0.25
V2. The e o e, he in-band noise o 2n,in−band = 2.5×10−10
V2 esul s in o al noise o 2n= 3.2×10−8V2 o an
OSR o 128. The calcula ed sampling capaci o would hus
be o abou 0.5-pF. Ensu ing some design ma gin, he inal
sampling capaci o is selec ed o be 1-pF. I should be no ed
ha he in eg a ion capaci o can be calcula ed acco ding o
a11 =Cs1
Ci1. A beha io al simula ion is also ca ied ou o
op imize he in eg a ion capaci o o he i s in eg a o , as
shown in Fig. 6. The maximum in-band noise (IBNmax)
is moni o ed as a unc ion o he i s in eg a ing capaci o .
Ha ing he in eg a ing capaci o o 6.7pF esul s in an
IBNmax o abou −105 dB. Conside ing ha a11 = 0.15,
he sampling capaci o is calcula ed as 1-pF, which con i ms
ou calcula ions.
C. OTA Speci ica ions
The se ling beha io o he in eg a o a he end o in-
eg a ion phase, which depends on he OTA pa ame e s i.e.
ini e DC-gain, uni y gain-bandwid h (GBW) and slew- a e
(SR), play a c ucial ole in he o e all pe o mance o a high-
esolu ion ∆ΣM. This equi es ca e ul design o hese pa-
ame e s o ensu e p ope ope a ion. Howe e , o e designing
pa ame e s in o de o mee he equi emen s is no a iable
app oach as i would esul in excessi e powe consump ion, a
c i ical pa ame e o minimize in he a ge low-powe de ices.
Fig. 7. SQNR e sus GBW and SR in he on -end OTA.
Fig. 8. Maximum in-band noise e sus OTA DC-gain.
The e o e, he objec i e o his sec ion is o de e mine he
minimum equi emen s o he OTAs used in he in eg a o s
o he p oposed ∆ΣM.
Since GBW and SR bo h de e mine he se ling beha io o
he modula o , i is bene icial o examine he simul aneous
e ec o GBW and SR, depic ed in Fig. 7. I mus be
men ioned ha he in eg a ing capaci o o he i s in eg a o
is se o 6.7-pF o his simula ion. As can be in e ed om
his simula ion, o a ain he a ge e ec i e numbe o bi
(ENOB) o 14-bi , he GBW and SR need o be mo e han
20-MHz and 15-V/µS, espec i ely. Gi ing some ma gin helps
o a oid SNDR deg ada ion due o o he ci cui impe ec ions
no conside ed a his design s age.
Fini e DC-gain o he OTA de e mines he accu acy o he
inal se led alue a he end o he in eg a ion phase. An
isola ed e alua ion is pe o med o ex ac he IBNmax o he
modula o as a unc ion o OTAs’ DC-gain, as shown in Fig. 8.
I should be men ioned ha his e alua ion is pe o med o he
scaled modula o wi h a −6-dBFS sinusoidal inpu a he OSR
o 128. As can be seen om his igu e, he ideal quan iza ion
noise loo emains in ac down o abou 50-dB OTA DC-gain.
This alue could be scaled down o he es o he in eg a o s.
D. Ji e e ec
I is well-known ha a SC-∆ΣM is less sensi i e o clock
ji e e o as compa ed o i s CT coun e pa and his is due
o he ac ha he SC-in eg a o is designed o be well-se led
wi hin hal o he clock pe iod. The ji e modula ed by he
signal equency, howe e , migh deg ade he pe o mance o
he SC-∆ΣM when inc easing he inpu equency. Assuming
ha he clock ji e has a Gaussian andom dis ibu ion wi h

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 6
Fig. 9. SJNR e sus inpu signal equency and clock ji e s anda d de ia ion.
he s anda d de ia ion o σ∆ , he signal o ji e noise a io
(SJNR) is exp essed as ollows [17]:
SJNR =OSR
4π2 2
inσ2
∆
(12)
whe e in is he inpu signal equency. To examine he e ec
o clock ji e while inc easing he inpu signal equency, a
beha io al simula ion is ca ied ou as depic ed in Fig. 9. I is
shown ha he p oposed modula o can ole a e clock ji e o
up o 400-ps wi hou signi ican ly SJNR deg ada ion.
E. Capaci o Misma ch
The in eg a o gain coe icien s, depic ed in Fig. 3, a e
implemen ed as capaci o a ios o Cs,i
CI,i i= 1, ..., 4. The e o e,
any de ia ion o hese alues om he nominal ones, due
o a ia ion in p ocess echnology pa ame e s o changes
he pole/ze o loca ion o he NTF may make he modula o
uns able. In he case o single-loop ∆ΣMs, a small de ia ion
is no signi ican since he il e ing p o ided by he in eg a o s
emains unchanged. Mo eo e , capaci o misma ch may ha e
a signi ican impac on he pe o mance o he MASH ∆ΣM
since he gain de ia ion o he in eg a o s is no compensa ed
by he digi al coe icien s o he DCL, and consequen ly he
modula o has a quan iza ion e o leakage a i s ou pu wi h
low o de noise shaping.
Conside ing he OTAs’ speci ica ions de e mined in he
p e ious sec ion, he capaci o misma ch equi emen is de-
e mined by execu ing a 500- un Mon e Ca lo analysis wi h
a Gaussian dis ibu ed andom misma ch. As depic ed in
Fig. 10, SNDR de ia es 2-dB om i s nominal alue o 0.1%
coe icien misma ch. Capaci o misma ch beyond 0.1% is a
pessimis ic design scena io, as a capaci o misma ch lowe
han 0.1% can be achie ed by ca e ul layou echniques.
Table II summa izes he esul s o he high-le el sizing
p ocess, conside ing he main ci cui non-ideal pa ame e s
associa ed o he ∆ΣM building blocks. These pa ame e s
de ine he elec ical speci ica ions o he ci cui -le el design
desc ibed in he nex sec ion.
IV. CIRCUIT-LEVEL IMPLEMENTATION
Figu e 11 depic s a concep ual schema ic o he p oposed
adde -less MASH 2-2 ∆ΣM along wi h he i s clock-phase
iming diag am. Al hough a single-ended schema ic is shown
o simplici y, he ac ual implemen a ion is ully di e en ial.
(a) (b)
(c) (d)
Fig. 10. Mon e Ca lo simula ion esul s by conside ing a capaci o - a io
misma ch o : (a) 0.1%, (b) 0.2%, (c) 0.3% and (4) 0.4%.
TABLE II
HIGH-LEVEL SIZING OF THE PROPOSED ∆ΣM
Simula ion se up @ −6-dBFS, OSR = 128 SNDR (dB)
Quan iza ion noise only 108
In eg a ing capaci o o 6.7-pF o he i s in eg a o 95.7
OTAs
DC-gain
(dB)
OTA1 50 93.6
OTA2,3,4 40
GBW
(MHz)
OTA1 >20
94.85
OTA2,3,4 >10
SR
(V/µs)
OTA1 >15
OTA2,3,4 >5
Quan ize Hys e esis + o se
(mV)
Q1 70 95.24
Q2 70
To ealize bo h s ages o he p oposed modula o , a delayed in-
eg a o ollowed by a non-delayed in eg a o se e as a loop-
il e as well as summing ampli ie . The i s in eg a o samples
he inpu signal a Φ1and he in eg a ion is pe o med a
subsequen Φ2. Meanwhile, he ou pu o he i s in eg a o is
di ec ly sampled by he second in eg a o a Φ2and in eg a ed
du ing he Φ1phase. The second in eg a o also sums he wo
ano he signals coming om he inpu signal and ou pu o he
i s in eg a o , simul aneously. P ope swi ching echniques
a e employed o gua an ee low swi ch on- esis ance and hence
o e ing enough se ling accu acy du ing he ope a ion ime.
Locally boo s apped swi ches (BT-SW) [8], highligh ed in
Fig. 11, a e u ilized in he signal pa hs o p o ide enough
sampling linea i y o a oid deg ading he pe o mance o he
p oposed modula o o e a wide ange o inpu swings. As
explained ea lie , he in eg a ing capaci o o he i s in eg a o
needs o be 6.7-pF o achie e a hal SNDR o abou 95 dB. Fo
he es o he in eg a o s, he in eg a ing capaci o s a e scaled-
down o 1-pF, due o he noise supp ession inside he loop,
and o diminish he powe consump ion. The es o capaci o s
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 7
Fig. 11. Schema ic (single-ended) o he p oposed adde -less MASH 2-2
∆ΣM.
a e de e mined acco ding o he co esponding coe icien s.
Non-o e lapping clock phases, i.e. Φ1and Φ2, a e needed
o no mal ope a ion o he SC-∆ΣM. The delayed e sion o
he main phases i.e. (Φ1dand Φ2d) a e also needed o diminish
he clock eed- h ough. Analog implemen a ion o he swi ches
can be p oblema ic when he supply ol age is educed o hal
o he nominal ol age a ing o he 0.18-µm CMOS p ocess
(i.e. 1.8-V). To ci cum en his issue, locally BT-SW [8] a e
used in he ∆ΣM chip. Dummy swi ches a e also u ilized o
he sake o clock eed- h ough supp ession.
A. P oposed Sel and bulk Biased OTA
The selec ion o an app op ia e OTA opology is he mos
c i ical pa o he design o a ∆ΣM especially in he case o
low-powe high- esolu ion ∆ΣMs. Compa ed o o he OTA
opologies, in e e -based OTAs ha e been employed in di -
e en ∆ΣMs [19]-[20]. One o he main d awbacks o hese
kinds o OTAs is ha hey need a dedica ed low d opou
egula o o make some o hei pe o mance pa ame e s
insensi i e o p ocess, ol age and empe a u e (PVT) [21]-
[22]. To ole a e PVT a ia ions, a dynamic biasing ech-
nique has also been add essed in [23] a he expense o
limi ing he bandwid h o in e e -based OTA which makes
his echnique undesi able o MHz ange sampling equency.
To accommoda e he speed limi a ion o he dynamic biasing
echnique, an ac i e pa asi ic compensa ion is p oposed in [24]
a he expense o ex a cu en d awing due o he use o
copying he quiescen cu en o he in e e and adding mo e
ci cui complexi ies. I is known ha sel -biasing echniques
p o ide obus ness agains PVT a ia ion and emo e he need
o egula o s. Thus, a sel -biased single-ended in e e -based
OTA was in oduced in [25], while [26] add esses a pseudo-
di e en ial in e e -based OTA wi h complex ci cui ies and
bo h a e biased in he s ong in e sion. I is a o able o bias
he in e e -based OTA in he weak in e sion o maximize gm
ID
and minimize he powe consump ion [24]. Howe e , i was
shown ha sub- h eshold ci cui s do no mee he equi emen s
o e slow and as p ocess co ne [12].
Fig. 12. In e e -based OTA, (a) P oposed SB in e e -based OTA in he weak
in e sion, (b) P oposed SBB in e e -based OTA in he weak in e sion, (c)
CMFB ci cui .
As shown in Sec ion III, unlike [20] whe e an OTA wi h
a gain boos ing echnique is equi ed, a DC-gain o 50 dB
is su icien o main ain he SNDR o he p oposed ∆ΣM
in ac . The e o e, he main objec i e is o keep he s uc u e
o he in e e -based OTA as simple as possible while making
i obus o e p ocess co ne . Beginning wi h he p oposed
sel -biased (SB) in e e -based OTA in he weak in e sion
egion, i will be shown ha i p o ides he a ge DC-gain
o e he p ocess co ne s. Howe e , i ails a slow p ocess
co ne o low VDD. The a o emen ioned issues a e a oided
by p oposing a SBB in e e -based OTA as desc ibed in he
ollowing sec ions.
1) Powe -E iciency Conside a ions: Figu e 12(a) shows
he schema ic o a SB ully di e en ial cu en s a ed in e e -
based OTA biased in he weak in e sion. Due o he use o a
di e en ial OTA, a common mode eedback (CMFB) ci cui is
used o sense he ou pu common-mode ol age and main ain
he ou pu ol age a a ce ain le el which is he mid-supply
ol age, i.e. 0.45-V. T ansis o s M5,6along wi h he CMFB
make he DC-gain o he SB in e e -based OTA obus o
PVT a ia ion by p o iding a nega i e eedback loop. I will
be shown ha he DC-gain o he OTA is always abo e 51-dB
o e he p ocess co ne s which mee s he a ge speci ica ions.
A SC implemen a ion o he CMFB, shown in Fig. 12(c), is
used o sa e on powe consump ion and no o limi he swing
o he OTAs. The swi ches connec ed o he OTA ou pu s a e
implemen ed as locally BT-SW o accommoda e wide ol age
swings.
The OTA s uc u e in Fig. 12(a) p esen s a e y high
ansconduc ance e iciency whe eas bo h de ices (i.e. NMOS
and PMOS) con ibu e o he o e all ansconduc ance o he
OTA so ha Gm, o al =gm,NMOS +gm,P MOS . Assuming
he same ansconduc ance o bo h NMOS and PMOS, he
ail cu en o he in e e -based OTA can be exp essed as
ollow:
I ail =GBW.2π.n.VT.CL(13)
Compa ing (12) o he esul s shown in [11], no only does
he in e e -based OTA exhibi a lowes ail cu en , bu i
also shows a ail- o- ail ou pu swing, esul ing in a highe
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 8
SR. Unlike loa ing in e e -based OTAs, he p oposed SB
OTA in Fig. 12(a), is sandwiched be ween a PMOS cu en
sou ce a he op and an NMOS cu en sink a he bo om.
These cu en sou ce/sinks help o imp o e he posi i e powe
supply ejec ion a io (PSRR) and nega i e PSRR as well,
o cou se a he expense o ex a ol age head oom. This
is no an issue since all o he ansis o s a e biased in he
weak in e sion egion. Fu he mo e, MOS ope a ion in weak
in e sion can p o ide a la ge alue o gm
IDin compa ison o
ansis o s ope a ing in s ong in e sion, esul ing in a be e
cu en e iciency [27].
2) Noise: In addi ion o he he mal noise, dic a ed by he
sampling capaci o , he inpu e e ed noise o he OTA is
ano he limi ing ac o ha needs o be aken in o accoun .
In his design, L1−4=Ln,W2,4= 3×W1,3= 3×Wnand
µn=3×µpa e chosen, esul ing in o al inpu e e ed noise
gi en by:
2
n,in =4
3·KF
CoxWnLn
·1
+4kT γ
gm
(14)
whe e KFis he licke noise coe icien ; is equency; Cox
is he oxide capaci ance, gm,Wand L ep esen he anscon-
duc ance, wid h and leng h o he ansis o , espec i ely; kis
he Bol zmann’s cons an ; Tis he absolu e empe a u e alue
and γis app oxima ely 1
2in he weak in e sion egion.
Flicke noise is he dominan noise sou ce a low equen-
cies. In o de o a enua e i s e ec , well-known choppe
s abiliza ion and co ela ed double sampling echniques can
be used. Howe e , he i s one may modula e he shaped
high- equency quan iza ion noise back down o he baseband
and he la e can cause addi ional he mal noise and coupling
clock noise induced by he added swi ches in he sampling
on -end [28]. Conside ing he abo e issues, none o he
men ioned licke -noise a enua ion echniques a e used in
his design. Ins ead, de ice sizes o he inpu ansis o s a e
inc eased o supp ess licke noise [7].
3) PVT Conside a ion: As men ioned ea lie , MOS an-
sis o s a e biased in he weak in e sion in he p oposed OTA
and in such a egion MOS pa ame e s show a g ea luc u-
a ion in he p esence o PVT a ia ions esul ing in a se e
deg ada ion in he pe o mance o he p oposed ∆ΣM. Taking
PMOS ansis o s in o accoun , i.e. M2,4,6 o example, his
luc ua ion can be desc ibed as ollows. In he p esence o he
slow-slow (SS) co ne , he ansconduc ance and d ain cu en
o PMOS ansis o s dec eases esul ing in a mal unc ion in he
p oposed ∆ΣM. This luc ua ion shows i sel an inc ease in
he powe consump ion when p ocess co ne is as - as (FF).
To mi iga e his issue, bulk biasing echnique is employed
o modi y he p oposed OTA as depic ed in Fig. 12(b). As
shown in his igu e, sensing ansis o s, which a e biased in
he weak in e sion, sense he luc ua ion o he main ansis o s
and decide p ope eac ion. In he p esence o he SS co ne ,
he sensing ansis o s, M2BP and M6BP o example, de ec
he luc ua ion and hus educing he d ain cu en . The e o e,
VBP 1and VBP 2a e dec eased and hus he h eshold ol age,
V h,p, o he PMOS ansis o esul ing in an inc ease in he
ansconduc ance and d ain cu en o he PMOS ansis o s.
When a FF p ocess, he d ain cu en o he sensing ansis o
(a)
(b)
(c)
Fig. 13. Simula ed pe o mance o he on -end SBB in e e -based OTA
o e PVT a ia ions: (a) DC-gain, (b) GBW and (c) s a ic powe .
inc eases esul ing in an inc ease in VBP 1and VBP 2and so
does he V h,p. Howe e , an addi ional posi i e and nega i e
le els mus be in oduced o le his echnique be e ec i e
a he FF p ocess [29]. As will be shown, he SB in e e -
based OTA ails a SS p ocess o low VDD and mee s
he equi emen s a he FF p ocess. The e o , no addi ional
posi i e and nega i e le els a e in oduced in he p oposed
SBB in e e -based OTA.
All in eg a o s in Fig. 11 ha e been designed using SBB
in e e -based OTAs depic ed in Fig. 12(b). Howe e , due o
he di e en elec ical speci ica ions equi ed o each OTA
(see Table II), wo di e en OTA designs a e used o he i s
in eg a o (OTA1) and he es o he in eg a o s (OTA2,3,4),
espec i ely. Excep o he i s OTA, he o he OTAs a e
ela i ely less c i ical and he cu en and pe o mance a e
hence scaled down.
Figu e 13 shows he simula ion esul s o some AC pe o -
mance me ics and powe consump ion o he OTA1, conside -
ing di e en co ne s and ypical condi ion. These simula ions
include 10% a ia ion in he 0.9-V supply ol age o e h ee
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 9
empe a u e alues, namely: −40◦C, 27◦C and 80◦C. Co ne
cases a e de ined in he igu e (i.e, condi ion, supply, empe -
a u e). As shown in Fig. 13(a), a wo s -case DC-gain o 51.04
dB (abou 1-dB less han he ypical condi ion) is obse ed in
his analysis. Such a DC-gain mee s he equi emen indica ed
in Fig. 8 and able II. Figu e 13(b) illus a es he GBW o
he p oposed OTA wi h/wi hou bulk biasing echnique. Fo
he ypical co ne , he p oposed OTA shows a GBW o 37.18
MHz and 34.61 MHz wi h and wi hou bulk biasing echnique.
A he SS p ocess co ne , C3co ne o example, he GBW
le els o o 10.67 MHz when bulk biasing is no ac i a ed
while he GBW is es o ed o a alue o 34.8MHz wi h
ac i a ed bulk biasing. Simila ly, he same compensa ion can
be pe o med when low VDD occu s. Figu e 13(c) shows he
powe consump ion o he p oposed SBB in e e -based OTA
ac oss di e en co ne s. Again C3co ne o an example, due
o an inc ease in he d ain cu en o PMOS ansis o , powe
consump ion le els up o 56.2-µW (96% o he ypical alue).
The phase ma gin o he SBB in e e -based OTA is 86.34◦
wi h de ia ion ange o less han 2% ac oss di e en p ocess
co ne s.
As men ioned ea lie , he p oposed SBB in e e -based OTA
can mee he GBW equi emen o e PVT a ia ions. I is also
wo h examining he se ling beha io o he p oposed OTA.
Acco ding o Spec e® simula ion, depic ed in Fig. 14(a),
he SB in e e -based OTA’s se -up ime is 39.2-ns a he
ypical co ne while i canno comple ely se le-down a slow
p ocess co ne , achie ing 71-ns se ling- ime. SBB in e e -
based OTA, howe e , p ope ly se le-down wi hin abou 39.8-
ns i.e. 20.3% o he sampling pe iod. Figu e 14(b) shows he
simula ed esul s o he p oposed OTA o e PVT a ia ions.
As can be seen om his igu e, he ailu e o e he slow
p ocess co ne o low supply ol age can be es o ed by he
p oposed OTA such ha he in eg a o can se le-down wi hin
less han 22% o he sampling pe iod.
Table III lis s he pos -layou simula ion esul s o he
designed OTAs. Unde ypical-co ne condi ions, OTA1 has
a DC-gain o abou 52 dB and a GBW o 37 MHz, which
is su icien o he equi ed modula o pe o mance, as con-
i med by beha io al simula ions, acco ding o Table II. The
o he OTAs show a DC-gain o abou 52 dB as well and a
GBW o abou 16 MHz. Al hough, 40-dB DC-gain is good
enough o a oid SNDR deg ada ion, he DC-gain is kep a
52-dB wi h a negligible powe penal y.
4) PSRR Conside a ions: I is known ha a single-ended
in e e -based OTA shows a poo PSRR due o high supply
ol age gain [20]. A pseudo-di e en ial opology, as depic ed
in Fig. 12(b), is employed o imp o e he PSRR. Ideally
ma ched inpu ansis o s esul s in an in ini ely high PSRR.
Howe e , he e is always misma ches be ween inpu ansis o s
in he ac ual implemen a ion. Fig. 15 illus a es he PSRR
o he i s OTA e sus equency o di e en ansis o
misma ch condi ions. The OTA shows a posi i e PSRR o 76.5
dB and a nega i e PSRR o 83.4dB o a 2% misma ch o only
he NMOS inpu ansis o s i.e. M1,3. Fo a 2% misma ch o
only he PMOS inpu ansis o s, he OTA shows a posi i e
and nega i e PSRR o 91.7dB and 90.5dB, espec i ely.
Conside ing a 2% misma ch o bo h NMOS and PMOS inpu
(a)
(b)
Fig. 14. Simula ed s ep esponse o he i s in eg a o (a) compa ison o SB
and SBB in e e -based OTA o slow co ne and (b) se ling- ime o e PVT
a ia ions.
TABLE III
SIMULATED PERFORMANCE OF THE OTAS
Pa ame e OTA 1 OTA 2,3,4
DC gain (dB) 52.15 52.07
GBW (MHz) 37.18 16.68
Phase ma gin (deg ee) 86.34 88.1
Supply ol age (V) 0.9 0.9
Powe consump ion (µW) 58.3 5.19
ansis o s, i is shown ha he o e all posi i e and nega i e
PSRR a e almos de e mined by he misma ch be ween he
NMOS inpu ansis o s. The eason is ha he aspec a io o
he PMOS ansis o is h ee imes ha o he NMOS inpu
ansis o s in he designed OTA. The e o e, special ca e mus
be aken when laying ou he NMOS inpu ansis o s, M1,3.
5) CMRR Conside a ions: Single-ended in e e -based
OTA shows a common mode ejec ion a io (CMRR) o 0
dB while pseudo di e en ial in e e -based OTA su e s om
a poo CMRR due o he lack o a ail cu en o egula e
he o al cu en lows h ough he in e e . Howe e , he ail
ansis o s, i.e. M5,6, allow o imp o e he CMRR in he
p oposed SBB in e e -based OTA. The p oposed OTA CMRR
e sus equency is depic ed in Fig. 16. The p oposed OTA
shows a CMRR o abou 95 dB o 5% ansis o misma ch
o e he desi ed 20-kHz signal bandwid h.
B. Compa a o
As s a ed ea lie , a single-bi quan ize (i.e. a compa a o ) is
used in he p oposed modula o . A egene a i e la ch p eceded
by a SC-ne wo k and ollowed by an SR-la ch, as depic ed
in Fig. 17, is used o implemen he compa a o in o de