A 0.9-V 100-mu W Feedforward Adder-Less Inverter-Based MASH Delta Sigma Modulator With 91-dB Dynamic Range and 20-kHz Bandwidth

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 1 A 0.9-V 100-µW Feedforward Adder-Less Inverter-based MASH ∆Σ Modulator with 91-dB Dynamic Range and 20-kHz Bandwidth Mohammad Honarparvar, Student Member, IEEE, Jos´ e M. de la Rosa, Senior Member, IEEE, and Mohamad Sawan, Fellow, IEEE Abstract—A 0.9-V ∆Σ modulator integrated in a 0.18-µm CMOS technology for digitizing signals in low-power devices is presented in this paper. To do so, a cascade (MASH) architecture based on an adder-less feedforward structure is proposed. The proposed modulator has a unity signal transfer function in both stages of the modulator in order to reduce the integrators output swings. To mitigate the failure of slow process corner in the weak inversion as well as to further diminish the power consumption of the presented modulator, a fully differential self and bulk biased (SBB) inverter-based OTA is proposed. Experimental results are shown to demonstrate the efficiency of the proposed ∆Σ converter, showing state-of-the-art performance, by featuring 88.7-dB SNR, 86.4-dB SNDR and 91-dB DR within a signal bandwidth of 20-kHz, with a power dissipation of 103.4-µW when the circuit is clocked at 5.12-MHz. Index Terms—Analog-to-digital conversion, delta-sigma modulation, switched-capacitor circuits, inverter-based OTAs. I. INTRODUCTION THE need for hand-held devices, smart-phones and medical implantable microelectronic systems, is remarkably growing up. However, keeping all these electronic devices power optimized is one of the main challenges due to the lack of life-time batteries utilized to power them up. One of the most critical building blocks of such devices is the analog-to-digital converter (ADC), since it needs to efficiently digitize acquired signals in a hostile environment. Compared to other ADC techniques, Delta-Sigma Modulators (∆ΣMs) have been widely used in those devices due to the unique features they offer and they are capable of being effectively power optimized at both architectural and circuit levels [1]- [2]. Nevertheless, special care must be taken into account to optimize the performance of ∆ΣMs. Indeed, many state-of- the-art high-resolution (>14-bit) low-bandwidth (<25-kHz) ∆ΣMs have been reported, including single-stage architectures [3]-[4] and cascade topologies – also referred to as Multi stAge noiSe sHaping (MASH) [1]-[5]. Among other ∆Σ loopfilter topologies, the so-called feedforward (FF) structure has M. Honarparvar and M. Sawan are with the Polystim Neurotech Lab, Department of Electrical Engineering, Polytechnique Montreal, Montreal, QC, Canada, H3T 1J4, e-mail: mohammad.honarparv[email protected]. J.M. de la Rosa is with Instituto de Microelectronica de Sevilla, IMSECNM, CSIC/Univ. de Sevilla, Sevilla, Spain. The authors acknowledge the National Sciences and Engineering Research Council of Canada for the support and CMC Microsystems for the design tools. This work was also partially supported by the Spanish Min. of Econ. and Comp. (supported by European RDF) under contract TEC2016-75151- C3-3-R. been successfully used by some designers to implement singlestage high-order (third-order or more) noise shaping [6]-[7]. However, the main limitation of FF structures is the powerhungry adder required at the input of the quantizer. This adder constitutes one of the main design bottlenecks of FF ∆ΣMs employed in ADCs, where the energy consumption becomes critical. In order to mitigate this limitation, some authors have proposed alternative implementations of the FF loop-filter. Thus, the ∆ΣM reported in [6] includes a fourth-order FF loop-filter with a passive adder. However, this technique suffers from both reduction of signal swing at the input of the comparator, and mismatch between capacitors. A similar strategy has been adopted in [7], where a 1.5-bit (3-level), fourth-order FF structure is proposed for digitizing signals with a 20-kHz bandwidth. Another approach consists of using switch matrix feedback compensation based on a direct summation technique as proposed in [8]. While such technique is well-suited for multi-bit quantizers, it is not applicable to single-bit ∆ΣMs. Moreover, employing multibit quantizers in high-resolution applications is limited by the inherited nonlinearity of the DAC used in the feedback path of the ∆Σ modulator. This requires using linearization techniques, such as dynamic element matching (DEM), which obviously leads to increasing the circuit complexity as well as the power consumption. Similar FF topologies have been addressed in [9]-[10] where the last integrator serves as an integrator and an adder simultaneously. However, an extra DAC in the feedback path is needed to retrieve the noise transfer function (NTF) of the modulator. It is worth noting that in all above-mentioned topologies, an extra DAC is required to extract the quantization noise if they are supposed to be used in a MASH configuration and hence adds circuit complexity. Apart from the strategies to optimize the performance of ∆ΣMs at system level, an important effort should be put also at circuit level. Scaling of CMOS technologies brings significant improvements in terms of functionality, speed, size, form factor and power consumption to the digital circuits. However, such an aggressive process scaling comes along with the reduced supply voltage to ensure the proper functionality of the device and reduces the intrinsic gain of CMOS transistors. The mentioned constraints make the design of the analog building blocks, e.g. operational transconductance amplifiers (OTAs), in a ∆Σ converter very challenging such that it limits the application of the traditional OTA topologies [11]. On IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 2 the other hand, a lower supply voltage reduces the voltage headroom and the available signal swing. This results in the dynamic range being limited by thermal noise. It also confines the choice of circuit architectures. Besides the mentioned drawbacks, biasing a circuit in the weak inversion, to minimize the power dissipation, is still of interest. However, such a biasing region makes the circuit severely susceptible to the process variations due to fluctuations in MOS parameters and it may decay the performance of a complex system like ∆Σ converters. Having discussed from that point of view, not only is an appropriate OTA topology needed, but proper remedy must be taken when biasing the OTA in the weak inversion [12]. This paper contributes to improve the performance of FF ∆ΣMs by exploring two approaches at the architectural and circuit levels, in order to mitigate the mentioned problems to realize a high-efficiency, high-resolution ∆ΣM, which covers the audio band (20-kHz) in a sub-1V environment using a 0.18-µm CMOS technology. To this end, a fourth-order adderless MASH ∆ΣM operating at 0.9-V is presented in this work as an extension and improved version of the paper presented by the authors in [11]. Although the alternative sturdy MASH structure based on the adder-less FF loop-filter, proposed in [13], relaxes the OTA DC-gain requirement, it will be shown that only a DC-gain of 50 dB is sufficient for the proposed MASH structure. Therefore, the main focus of this work at the circuit level is to keep the OTA structure as simple as possible and power efficient. A fully differential SBB inverter-based OTA, operating in the weak inversion, is therefore proposed to implement the integrators of the proposed ∆ΣM. It is shown that the proposed OTA is robust against slow corners and low supply voltage. The paper is organized as follows. Section II describes the proposed ∆ΣM architecture and some system-level design considerations. High-level synthesis, analysis and optimization are addressed in Section III. Section IV demonstrates the circuit level implementation of the proposed ∆ΣM including SBB inverter-based OTA, switches and comparator. Experimental results are given in Section V and finally a conclusion is drawn in SectionVI. II. PROPOSED ADDER-LESS MASH FF ∆ΣM As mentioned in the introduction, FF ∆ΣM is a wellsuited topology to implement low-voltage low-power ∆ΣMs. However, the key bottleneck of the FF structure is the adder before the quantizer, which could be realized either using active or passive circuits. Although an active adder, which allows for an accurate summation, is more reliable, a fast power-hungry OTA needs to be realized in order to incorporate into the active adder. Alternatively, a passive adder can be used. Although such technique is well-suited for low-power applications, signal swings and the quantizer input step are degraded due to the parasitics [3]. In addition, the quantizer kick-back noise as well as capacitor mismatches may severely degrade the overall signal to noise plus distortion ratio (SNDR) of the modulator. Finally, the area occupied by passive circuit elements may impose significant restrictions [14]. Fig. 1. Adder-less FF ∆ΣM with single (multi)-bit quantizer. Fig. 2. Quantization error extraction: conventional method (red) and proposed method used in the adder-less FF ∆ΣM (blue). A. Adder-less Single-stage Feedforward Architecture 1) Dynamic Behavior of the Adder-less ∆ΣM: The approach to overcome the aforementioned problem is to perform the signal summation at the input of the last integrator instead of the quantizer input, as depicted in Fig. 1. In other words, the last integrator is shared to serve as an integrator and as an adder simultaneously. Consequently, both the circuit complexity and the power consumption can be reduced. Without loss of generality, all coefficients are assumed to be set to unity in Fig. 1, i.e. b1= 1 and ai= 1,i= 1,2,3,4. In this case, the NTF and STF of the modulator can thus be respectively written as follows: NT F (z) = (1 −z−1) (1 −z−1) + z−1·I2(z)·(1 + G(z)) (1) ST F (z) = z−1·I2(z)·(1 + G(z)) + H(z)·I2(z) (1 −z−1) + z−1·I2(z)·(1 + G(z)) (2) Comparing (1) and (2) to that of the conventional second order FF structure with an NT F (z) = (1 −z−1)2,I2(z), G(z)and H(z), as depicted in Fig. 1, are considered to have a second-order noise shaping as well as a unity STF as follows. It is worth noting that any arbitrary NTF can be mapped onto the ∆ΣM in Fig. 1, resulting in different coefficient values. I2(z) = 1 (1 −z−1)(3) G(z) = H(z)=1−z−1(4) It is valuable to write the integrator outputs for the adderless modulator, depicted in Fig. 1. As can be seen from (5) and (6), the first integrator processes the quantization noise while the output of the second integrator includes the input signal component. Note that any non-idealities caused by the second-order integrator are shaped by the loop-filter, so that IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 3 these non-idealities do not severely influence the performance of the modulator. V1(z) = −z−1·(1 −z−1)·E(z)(5) V2(z) = X(z)−z−1·(1 −z−1)·E(z)(6) 2) Quantization Error Extraction of the Adder-less ∆ΣM: The conventional method to extract the quantization error in a MASH ∆ΣM is to subtract the quantizer output from the quantizer input, as shown in Fig. 2. However, such an approach exacerbates the complexity of the quantization error extraction, especially when the number of quantizer level increases. This is due to the fact that the quantizer output is represented in thermometer code and a multi-bit switched capacitor (SC)- DAC is needed to perform such a subtraction. As shown in [15], [16], a delayed version of the quantization error is available at the output of the second integrator in the FF topology, which makes this topology desirable for a MASH structure as well as for extended counting incremental ADCs. However, this is not the case in the proposed ∆ΣM since the quantization error is high-pass filtered at the output of the first integrator and the second integrator processes both the input signal and the quantization error as well. Fortunately, the quantization error is available in the proposed architecture if the signals at different nodes of the modulator are properly traced. Setting all coefficients at unity- to simplify the analysisresults in a second-order NTF i.e. NT F (z) = (1−z−1)2and the output of the second integrator, V2(z), can be expressed as a function of input signal, X(z), and first integrator output, V1(z)as follows: V2(z) = X(z) + 2−z−1 1−z−1·V1(z)(7) Substituting (5) and (7) in expression (8) shows that with proper combination of the input signal of the modulator, X(z), and the output of the first and second integrators (V1(z)and V2(z)), a delayed version of the quantization error can be extracted in the adder-less FF topology, yielding: X(z) + V1(z)−V2(z) = z−1·E1(z)(8) where E1(z)is the quantization error of the front-end stage. B. Proposed Adder-less MASH Feedforward Architecture In order to ensure a high performance power optimized ∆ΣM, its system-level parameters, i.e. the order of the loopfilter, the OSR and the number of bits of the embedded quantizer, must be carefully determined. Moreover, the selection between a single-stage and a MASH structure is another important decision to make. Increasing the quantizer resolution leads to increasing the SNDR of the modulator at the expense of circuit complexity and power consumption. Moreover, linearization techniques are required to suppress nonlinear behavior of the feedback DAC. To get rid of these problems, a single-bit quantizer is considered in this design. Although a higher SNDR can be achieved with a higher order modulator, it makes the modulator susceptible to instability. Single-bit quantizer even exacerbates the stability issue. Alternatively, a MASH ∆ΣM is a suitable solution in which Fig. 3. System-level diagram of the proposed adder-less MASH ∆ΣM. the order of the modulator can be increased by cascading loworder (typically first-order and second-order) stages, which are inherently stable, and hence the overall ∆ΣM structure is stable [17]. Based on these considerations, a MASH ∆ΣM with single-bit quantizer is chosen in this work. In order to determine the OSR and the order of the modulator, an extensive analysis, fine tuned by behavioral simulation, is carried out to maximize the SNDR of the ∆ΣM with the minimum power consumption. As depicted in Fig. 3, a fourthorder MASH structure ∆ΣM (MASH 2-2), which consists of the two stages second-order adder-less ∆ΣMs with a singlebit quantizer, is considered for this design. Note that the quantization error is extracted as described in the previous section and the explicit adder at the input of the second stage is for illustrative purposes only. In a practical implementation, all signals are summed up at the input of the third and fourth integrators, as will be detailed in Section IV. An OSR of 128 with the sampling frequency of 5.12 MHz is selected to make the proposed modulator operate over a 20-kHz signal bandwidth. Assuming the NTF of (1 −z−1)2for each stage of the proposed ∆ΣM, the output of the first and second stage can be respectively expressed as: Y1(z) = X(z) + (1 −z−1)2·E1(z)(9) Y2(z) = z−1·E1(z) + (1 −z−1)2·E2(z)(10) and the overall z-domain output signal of the proposed ∆ΣM is given by: YP roposed−MASH (z) = Y1(z)·H1(z) + Y2(z)·H2(z)(11) where H1(z)and H2(z)are the digital cancellation logics (DCLs) to cancel the quantization error of the first stage i.e. E1(z).Y1(z)and Y2(z)represent the outputs of the first and second stages, respectively. Assuming H1(z) = −z−1and H2(z) = (1 −z−1)2, the quantization error of the first stage, E1(z), is ideally cancelled, while E2(z)is shaped by a fourthorder NTF. III. HIGH-LEVEL SYNTHESIS The analysis presented above considers ideal ∆ΣM building blocks. However, this ideal performance degrades in practice by the action of circuit error mechanisms [18]. A detailed analysis of the main nonidealities is therefore necessary in order to set the electrical specifications of the ∆ΣM subcircuits and to optimize their design. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 4 (a) (b) (c) (d) (e) (f) Fig. 4. Integrator output swing (normalized to the ∆ΣM full scale) versus input signal level: (a) Single-bit modulator synthesized through an NTF of (1 −z−1)4and before scaling, (b) Single-bit modulator through an NTF of (1 −z−1)4and after scaling, (c) 1.5-bit modulator synthesized through an NTF of (1 −z−1)4and before scaling, (d) 4-bit modulator synthesized through an NTF of (1 −z−1)4and before scaling, (e) Single-bit modulator synthesized through an NTF with an out-of-band gain of 1.5(Hinf = 1.5) and before scaling, (f) Single-bit modulator synthesized through an NTF with an out-of-band gain of 1.5(Hinf = 1.5) and after scaling. A. Modulator Loop Filter Coefficients Scaling The proposed adder-less MASH ∆ΣM, depicted in Fig. 3, is synthesized with an NTF of (1 −z−1)4, and all loop coefficients are initialized to one, while the output swing of each integrator is not considered. Therefore, it is more likely that the integrators will be saturated in an actual implementation if the output voltage level becomes critically large. Moreover, distortion, which deteriorates the performance of the ∆ΣM, is the major consequence of the saturated integrators. Therefore, it is beneficial to observe the integrator output swings and to properly scale the coefficients of the modulator in order to guarantee a reasonable signal swing at each integrator output. This results in a reduced power consumption and an improved dynamic range (DR). Behavioral simulations are carried out to monitor the output swing of all integrators versus input signal level, as shown in Fig. 4. Fig. 4(a) shows the output swing of all integrators while all coefficients are initialized to one resulting in an overall NTF Fig. 5. Histogram of the integrator output swings relative to the FS voltage. of (1 −z−1)4. It is clear that the input of the first integrator must be scaled down by a factor of 8to accommodate integrator’s output swing in sub-1-V environment. This factor must be larger for the second and third integrators. It must be mentioned that larger scaling down factor leads to higher integrating capacitor value for a given sampling capacitor, and hence increased modulator power consumption. The fourth integrator is problematic as an unbounded output swing is observed at its output. In this condition the modulator tends to be unstable. Figure 4(b) shows the scaled modulator with a factor of 8. Note that, even using such a large scale factor for all integrators, an unbounded output swing is obtained at the output of the fourth integrator. As stated above, multi-bit quantization alleviates this issue at the expense of requiring DAC linearizion techniques, with a resulting penalty in power consumption. Fig. 4(c) and (d) shows the output swing of the integrators with a 1.5-bit and a 4-bit quantizer, respectively. For the case of a 1.5bit quantizer per stage, the modulator still needs to be scaled down with large factors. As a single-bit quantizer is assumed in this design, the NTF out-of-band gain (Hinf ) is reduced to 1.5and the coefficients of the modulator are re-synthesized. As shown in Fig. 4(e), the output swing of all integrators are bounded to 1before scaling of the modulator. The output swing of integrators after coefficient scaling is shown in Fig. 4(f). It can be seen that the output swings do not tend to be saturated even close to an input level of 0dBFS. The output swing of the integrators are better illustrated in the histograms depicted in Fig. 5, where a −6-dBFS input signal level is considered after coefficients scaling. As can be seen from this figure, the output swings for all integrators are within 23% of the full-scale (FS) voltage. Due to such a relaxed headroom requirement, a high slew-rate OTA is not required, resulting in the ability to design a lower power circuit. The coefficients selected for the modulator after scaling are summarized in Table I. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 5 TABLE I COEFFICIENTS OF THE PROPOSED ∆ΣMAFTER SCALING Coefficient a11 a12 a13 b11 c11 a21 Value 0.15 0.3 0.75 0.15 0.15 0.15 Coefficient a22 a23 b21 c21 d d1,2 Value 0.3 0.75 0.15 0.15 1 5 Fig. 6. Maximum IBN versus integration capacitor size of the first integrator. B. Sampling Capacitor of the Front-end Integrator Careful selection of the sampling capacitor, especially for the first integrator, is an important task since it determines the KT Cnoise, which constitute the ultimate limiting factor in the noise floor of the modulator. On the other hand, the front-end sampling capacitor has a direct contribution on the capacitive load of the integrator and hence, on the settling requirement and the power consumption. The procedure given in [17] is followed to determine the sampling capacitor of the first integrator. In this design, for the target signal to noise ratio (SNR) of 90 dB at −3-dBFS, the signal power is v2 s= 0.25 V2. Therefore, the in-band noise of v2n,in−band = 2.5×10−10 V2results in total noise of v2n= 3.2×10−8V2for an OSR of 128. The calculated sampling capacitor would thus be of about 0.5-pF. Ensuring some design margin, the final sampling capacitor is selected to be 1-pF. It should be noted that the integration capacitor can be calculated according to a11 =Cs1 Ci1. A behavioral simulation is also carried out to optimize the integration capacitor of the first integrator, as shown in Fig. 6. The maximum in-band noise (IBNmax) is monitored as a function of the first integrating capacitor. Having the integrating capacitor of 6.7pF results in an IBNmax of about −105 dB. Considering that a11 = 0.15, the sampling capacitor is calculated as 1-pF, which confirms our calculations. C. OTA Specifications The settling behavior of the integrator at the end of integration phase, which depends on the OTA parameters i.e. finite DC-gain, unity gain-bandwidth (GBW) and slew-rate (SR), play a crucial role in the overall performance of a highresolution ∆ΣM. This requires careful design of these parameters to ensure proper operation. However, overdesigning parameters in order to meet the requirements is not a viable approach as it would result in excessive power consumption, a critical parameter to minimize in the target low-power devices. Fig. 7. SQNR versus GBW and SR in the front-end OTA. Fig. 8. Maximum in-band noise versus OTA DC-gain. Therefore, the objective of this section is to determine the minimum requirements for the OTAs used in the integrators of the proposed ∆ΣM. Since GBW and SR both determine the settling behavior of the modulator, it is beneficial to examine the simultaneous effect of GBW and SR, depicted in Fig. 7. It must be mentioned that the integrating capacitor of the first integrator is set to 6.7-pF for this simulation. As can be inferred from this simulation, to attain the target effective number of bit (ENOB) of 14-bit, the GBW and SR need to be more than 20-MHz and 15-V/µS, respectively. Giving some margin helps to avoid SNDR degradation due to other circuit imperfections not considered at this design stage. Finite DC-gain of the OTA determines the accuracy of the final settled value at the end of the integration phase. An isolated evaluation is performed to extract the IBNmax of the modulator as a function of OTAs’ DC-gain, as shown in Fig. 8. It should be mentioned that this evaluation is performed for the scaled modulator with a −6-dBFS sinusoidal input at the OSR of 128. As can be seen from this figure, the ideal quantization noise floor remains intact down to about 50-dB OTA DC-gain. This value could be scaled down for the rest of the integrators. D. Jitter effect It is well-known that a SC-∆ΣM is less sensitive to clock jitter error as compared to its CT counterpart and this is due to the fact that the SC-integrator is designed to be well-settled within half of the clock period. The jitter modulated by the signal frequency, however, might degrade the performance of the SC-∆ΣM when increasing the input frequency. Assuming that the clock jitter has a Gaussian random distribution with IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 6 Fig. 9. SJNR versus input signal frequency and clock jitter standard deviation. the standard deviation of σ∆t, the signal to jitter noise ratio (SJNR) is expressed as follows [17]: SJNR =OSR 4π2f2 inσ2 ∆t (12) where fin is the input signal frequency. To examine the effect of clock jitter while increasing the input signal frequency, a behavioral simulation is carried out as depicted in Fig. 9. It is shown that the proposed modulator can tolerate clock jitter of up to 400-ps without significantly SJNR degradation. E. Capacitor Mismatch The integrator gain coefficients, depicted in Fig. 3, are implemented as capacitor ratios of Cs,i CI,i i= 1, ..., 4. Therefore, any deviation of these values from the nominal ones, due to variation in process technology parameters or changes the pole/zero location of the NTF may make the modulator unstable. In the case of single-loop ∆ΣMs, a small deviation is not significant since the filtering provided by the integrators remains unchanged. Moreover, capacitor mismatch may have a significant impact on the performance of the MASH ∆ΣM since the gain deviation of the integrators is not compensated by the digital coefficients of the DCL, and consequently the modulator has a quantization error leakage at its output with low order noise shaping. Considering the OTAs’ specifications determined in the previous section, the capacitor mismatch requirement is determined by executing a 500-run Monte Carlo analysis with a Gaussian distributed random mismatch. As depicted in Fig. 10, SNDR deviates 2-dB from its nominal value for 0.1% coefficient mismatch. Capacitor mismatch beyond 0.1% is a pessimistic design scenario, as a capacitor mismatch lower than 0.1% can be achieved by careful layout techniques. Table II summarizes the results of the high-level sizing process, considering the main circuit non-ideal parameters associated to the ∆ΣM building blocks. These parameters define the electrical specifications for the circuit-level design described in the next section. IV. CIRCUIT-LEVEL IMPLEMENTATION Figure 11 depicts a conceptual schematic of the proposed adder-less MASH 2-2 ∆ΣM along with the its clock-phase timing diagram. Although a single-ended schematic is shown for simplicity, the actual implementation is fully differential. (a) (b) (c) (d) Fig. 10. Monte Carlo simulation results by considering a capacitor-ratio mismatch of: (a) 0.1%, (b) 0.2%, (c) 0.3% and (4) 0.4%. TABLE II HIGH-LEVEL SIZING OF THE PROPOSED ∆ΣM Simulation setup @ −6-dBFS, OSR = 128 SNDR (dB) Quantization noise only 108 Integrating capacitor of 6.7-pF for the first integrator 95.7 OTAs DC-gain (dB) OTA1 50 93.6 OTA2,3,4 40 GBW (MHz) OTA1 >20 94.85 OTA2,3,4 >10 SR (V/µs) OTA1 >15 OTA2,3,4 >5 Quantizer Hysteresis + offset (mV) Q1 70 95.24 Q2 70 To realize both stages of the proposed modulator, a delayed integrator followed by a non-delayed integrator serve as a loopfilter as well as summing amplifier. The first integrator samples the input signal at Φ1and the integration is performed at subsequent Φ2. Meanwhile, the output of the first integrator is directly sampled by the second integrator at Φ2and integrated during the Φ1phase. The second integrator also sums the two another signals coming from the input signal and output of the first integrator, simultaneously. Proper switching techniques are employed to guarantee low switch on-resistance and hence offering enough settling accuracy during the operation time. Locally bootstrapped switches (BT-SW) [8], highlighted in Fig. 11, are utilized in the signal paths to provide enough sampling linearity to avoid degrading the performance of the proposed modulator over a wide range of input swings. As explained earlier, the integrating capacitor of the first integrator needs to be 6.7-pF to achieve a half SNDR of about 95 dB. For the rest of the integrators, the integrating capacitors are scaleddown to 1-pF, due to the noise suppression inside the loop, and to diminish the power consumption. The rest of capacitors IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 7 Fig. 11. Schematic (single-ended) of the proposed adder-less MASH 2-2 ∆ΣM. are determined according to the corresponding coefficients. Non-overlapping clock phases, i.e. Φ1and Φ2, are needed for normal operation of the SC-∆ΣM. The delayed version of the main phases i.e. (Φ1dand Φ2d) are also needed to diminish the clock feed-through. Analog implementation of the switches can be problematic when the supply voltage is reduced to half of the nominal voltage rating of the 0.18-µm CMOS process (i.e. 1.8-V). To circumvent this issue, locally BT-SW [8] are used in the ∆ΣM chip. Dummy switches are also utilized for the sake of clock feed-through suppression. A. Proposed Self and bulk Biased OTA The selection of an appropriate OTA topology is the most critical part of the design of a ∆ΣM especially in the case of low-power high-resolution ∆ΣMs. Compared to other OTA topologies, inverter-based OTAs have been employed in different ∆ΣMs [19]-[20]. One of the main drawbacks of these kinds of OTAs is that they need a dedicated low dropout regulator to make some of their performance parameters insensitive to process, voltage and temperature (PVT) [21]- [22]. To tolerate PVT variations, a dynamic biasing technique has also been addressed in [23] at the expense of limiting the bandwidth of inverter-based OTA which makes this technique undesirable for MHz range sampling frequency. To accommodate the speed limitation of the dynamic biasing technique, an active parasitic compensation is proposed in [24] at the expense of extra current drawing due to the use of copying the quiescent current of the inverter and adding more circuit complexities. It is known that self-biasing techniques provide robustness against PVT variation and remove the need for regulators. Thus, a self-biased single-ended inverter-based OTA was introduced in [25], while [26] addresses a pseudodifferential inverter-based OTA with complex circuities and both are biased in the strong inversion. It is favorable to bias the inverter-based OTA in the weak inversion to maximize gm ID and minimize the power consumption [24]. However, it was shown that sub-threshold circuits do not meet the requirements over slow and fast process corner [12]. Fig. 12. Inverter-based OTA, (a) Proposed SB inverter-based OTA in the weak inversion, (b) Proposed SBB inverter-based OTA in the weak inversion, (c) CMFB circuit. As shown in Section III, unlike [20] where an OTA with a gain boosting technique is required, a DC-gain of 50 dB is sufficient to maintain the SNDR of the proposed ∆ΣM intact. Therefore, the main objective is to keep the structure of the inverter-based OTA as simple as possible while making it robust over process corner. Beginning with the proposed self-biased (SB) inverter-based OTA in the weak inversion region, it will be shown that it provides the target DC-gain over the process corners. However, it fails at slow process corner or low VDD. The aforementioned issues are avoided by proposing a SBB inverter-based OTA as described in the following sections. 1) Power-Efficiency Considerations: Figure 12(a) shows the schematic of a SB fully differential current starved inverterbased OTA biased in the weak inversion. Due to the use of a differential OTA, a common mode feedback (CMFB) circuit is used to sense the output common-mode voltage and maintain the output voltage at a certain level which is the mid-supply voltage, i.e. 0.45-V. Transistors M5,6along with the CMFB make the DC-gain of the SB inverter-based OTA robust to PVT variation by providing a negative feedback loop. It will be shown that the DC-gain of the OTA is always above 51-dB over the process corners which meets the target specifications. A SC implementation of the CMFB, shown in Fig. 12(c), is used to save on power consumption and not to limit the swing of the OTAs. The switches connected to the OTA outputs are implemented as locally BT-SW to accommodate wider voltage swings. The OTA structure in Fig. 12(a) presents a very high transconductance efficiency whereas both devices (i.e. NMOS and PMOS) contribute to the overall transconductance of the OTA so that Gm,total =gm,NMOS +gm,P MOS . Assuming the same transconductance for both NMOS and PMOS, the tail current of the inverter-based OTA can be expressed as follow: Itail =GBW.2π.n.VT.CL(13) Comparing (12) to the results shown in [11], not only does the inverter-based OTA exhibit a lowest tail current, but it also shows a rail-to-rail output swing, resulting in a higher IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 8 SR. Unlike floating inverter-based OTAs, the proposed SB OTA in Fig. 12(a), is sandwiched between a PMOS current source at the top and an NMOS current sink at the bottom. These current source/sinks help to improve the positive power supply rejection ratio (PSRR) and negative PSRR as well, of course at the expense of extra voltage headroom. This is not an issue since all of the transistors are biased in the weak inversion region. Furthermore, MOS operation in weak inversion can provide a large value of gm IDin comparison to transistors operating in strong inversion, resulting in a better current efficiency [27]. 2) Noise: In addition to the thermal noise, dictated by the sampling capacitor, the input referred noise of the OTA is another limiting factor that needs to be taken into account. In this design, L1−4=Ln,W2,4= 3×W1,3= 3×Wnand µn=3×µpare chosen, resulting in total input referred noise given by: v2 n,in =4 3·KF CoxWnLn ·1 f+4kT γ gm (14) where KFis the flicker noise coefficient; fis frequency; Cox is the oxide capacitance, gm,Wand Lrepresent the transconductance, width and length of the transistor, respectively; kis the Boltzmann’s constant; Tis the absolute temperature value and γis approximately 1 2in the weak inversion region. Flicker noise is the dominant noise source at low frequencies. In order to attenuate its effect, well-known chopper stabilization and correlated double sampling techniques can be used. However, the first one may modulate the shaped high-frequency quantization noise back down to the baseband and the latter can cause additional thermal noise and coupling clock noise induced by the added switches in the sampling front-end [28]. Considering the above issues, none of the mentioned flicker-noise attenuation techniques are used in this design. Instead, device sizes of the input transistors are increased to suppress flicker noise [7]. 3) PVT Consideration: As mentioned earlier, MOS transistors are biased in the weak inversion in the proposed OTA and in such a region MOS parameters show a great fluctuation in the presence of PVT variations resulting in a sever degradation in the performance of the proposed ∆ΣM. Taking PMOS transistors into account, i.e. M2,4,6for example, this fluctuation can be described as follows. In the presence of the slow-slow (SS) corner, the transconductance and drain current of PMOS transistors decreases resulting in a malfunction in the proposed ∆ΣM. This fluctuation shows itself an increase in the power consumption when process corner is fast-fast (FF). To mitigate this issue, bulk biasing technique is employed to modify the proposed OTA as depicted in Fig. 12(b). As shown in this figure, sensing transistors, which are biased in the weak inversion, sense the fluctuation of the main transistors and decide proper reaction. In the presence of the SS corner, the sensing transistors, M2BP and M6BP for example, detect the fluctuation and thus reducing the drain current. Therefore, VBP 1and VBP 2are decreased and thus the threshold voltage, Vth,p, of the PMOS transistor resulting in an increase in the transconductance and drain current of the PMOS transistors. When at FF process, the drain current of the sensing transistor (a) (b) (c) Fig. 13. Simulated performance of the front-end SBB inverter-based OTA over PVT variations: (a) DC-gain, (b) GBW and (c) static power. increases resulting in an increase in VBP 1and VBP 2and so does the Vth,p. However, an additional positive and negative levels must be introduced to let this technique be effective at the FF process [29]. As will be shown, the SB inverterbased OTA fails at SS process or low VDD and meets the requirements at the FF process. Therefor, no additional positive and negative levels are introduced in the proposed SBB inverter-based OTA. All integrators in Fig. 11 have been designed using SBB inverter-based OTAs depicted in Fig. 12(b). However, due to the different electrical specifications required for each OTA (see Table II), two different OTA designs are used for the first integrator (OTA1) and the rest of the integrators (OTA2,3,4), respectively. Except for the first OTA, the other OTAs are relatively less critical and the current and performance are hence scaled down. Figure 13 shows the simulation results of some AC performance metrics and power consumption of the OTA1, considering different corners and typical condition. These simulations include 10% variation in the 0.9-V supply voltage over three IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS – I: REGULAR PAPERS 9 temperature values, namely: −40◦C, 27◦C and 80◦C. Corner cases are defined in the figure (i.e, condition, supply, temperature). As shown in Fig. 13(a), a worst-case DC-gain of 51.04 dB (about 1-dB less than the typical condition) is observed in this analysis. Such a DC-gain meets the requirement indicated in Fig. 8 and table II. Figure 13(b) illustrates the GBW of the proposed OTA with/without bulk biasing technique. For the typical corner, the proposed OTA shows a GBW of 37.18 MHz and 34.61 MHz with and without bulk biasing technique. At the SS process corner, C3corner for example, the GBW levels off to 10.67 MHz when bulk biasing is not activated while the GBW is restored to a value of 34.8MHz with activated bulk biasing. Similarly, the same compensation can be performed when low VDD occurs. Figure 13(c) shows the power consumption of the proposed SBB inverter-based OTA across different corners. Again C3corner for an example, due to an increase in the drain current of PMOS transistor, power consumption levels up to 56.2-µW (96% of the typical value). The phase margin of the SBB inverter-based OTA is 86.34◦ with deviation range of less than 2% across different process corners. As mentioned earlier, the proposed SBB inverter-based OTA can meet the GBW requirement over PVT variations. It is also worth examining the settling behavior of the proposed OTA. According to Spectre® simulation, depicted in Fig. 14(a), the SB inverter-based OTA’s set-up time is 39.2-ns at the typical corner while it cannot completely settle-down at slow process corner, achieving 71-ns settling-time. SBB inverterbased OTA, however, properly settle-down within about 39.8- ns i.e. 20.3% of the sampling period. Figure 14(b) shows the simulated results of the proposed OTA over PVT variations. As can be seen from this figure, the failure over the slow process corner or low supply voltage can be restored by the proposed OTA such that the integrator can settle-down within less than 22% of the sampling period. Table III lists the post-layout simulation results of the designed OTAs. Under typical-corner conditions, OTA1 has a DC-gain of about 52 dB and a GBW of 37 MHz, which is sufficient for the required modulator performance, as confirmed by behavioral simulations, according to Table II. The other OTAs show a DC-gain of about 52 dB as well and a GBW of about 16 MHz. Although, 40-dB DC-gain is good enough to avoid SNDR degradation, the DC-gain is kept at 52-dB with a negligible power penalty. 4) PSRR Considerations: It is known that a single-ended inverter-based OTA shows a poor PSRR due to high supply voltage gain [20]. A pseudo-differential topology, as depicted in Fig. 12(b), is employed to improve the PSRR. Ideally matched input transistors results in an infinitely high PSRR. However, there is always mismatches between input transistors in the actual implementation. Fig. 15 illustrates the PSRR of the first OTA versus frequency for different transistor mismatch conditions. The OTA shows a positive PSRR of 76.5 dB and a negative PSRR of 83.4dB for a 2% mismatch of only the NMOS input transistors i.e. M1,3. For a 2% mismatch of only the PMOS input transistors, the OTA shows a positive and negative PSRR of 91.7dB and 90.5dB, respectively. Considering a 2% mismatch of both NMOS and PMOS input (a) (b) Fig. 14. Simulated step response of the first integrator (a) comparison of SB and SBB inverter-based OTA for slow corner and (b) settling-time over PVT variations. TABLE III SIMULATED PERFORMANCE OF THE OTAS Parameter OTA 1 OTA 2,3,4 DC gain (dB) 52.15 52.07 GBW (MHz) 37.18 16.68 Phase margin (degree) 86.34 88.1 Supply voltage (V) 0.9 0.9 Power consumption (µW) 58.3 5.19 transistors, it is shown that the overall positive and negative PSRR are almost determined by the mismatch between the NMOS input transistors. The reason is that the aspect ratio of the PMOS transistor is three times that of the NMOS input transistors in the designed OTA. Therefore, special care must be taken when laying out the NMOS input transistors, M1,3. 5) CMRR Considerations: Single-ended inverter-based OTA shows a common mode rejection ratio (CMRR) of 0 dB while pseudo differential inverter-based OTA suffers from a poor CMRR due to the lack of a tail current to regulate the total current flows through the inverter. However, the tail transistors, i.e. M5,6, allow to improve the CMRR in the proposed SBB inverter-based OTA. The proposed OTA CMRR versus frequency is depicted in Fig. 16. The proposed OTA shows a CMRR of about 95 dB for 5% transistor mismatch over the desired 20-kHz signal bandwidth. B. Comparator As stated earlier, a single-bit quantizer (i.e. a comparator) is used in the proposed modulator. A regenerative latch preceded by a SC-network and followed by an SR-latch, as depicted in Fig. 17, is used to implement the comparator in order