Citations refer to the original publication, not to a Scieee localized version.
Guerrero Martos, D., Bellido Díaz, M. J., Juan Chico, J., Millán Calderón, A., Ruiz de Clavijo Vázquez, P., Ostúa Arangüena, E., & Viejo Cortés, J. (2007). Automatic logic synthesis for parallel alternating latches clocking schemes. SPIE Digital Library. https://doi.org/10.1117/12.723664
Guerrero Martos, David, et al. Automatic logic synthesis for parallel alternating latches clocking schemes. SPIE Digital Library, 2007. https://doi.org/10.1117/12.723664.
Guerrero Martos, David, Manuel Jesús Bellido Díaz, Jorge Juan Chico, Alejandro Millán Calderón, Paulino Ruiz de Clavijo Vázquez, Enrique Ostúa Arangüena, and Julián Viejo Cortés. Automatic logic synthesis for parallel alternating latches clocking schemes. SPIE Digital Library, 2007. https://doi.org/10.1117/12.723664.
Guerrero Martos, D. et al. (2007) Automatic logic synthesis for parallel alternating latches clocking schemes. SPIE Digital Library. Available at: https://doi.org/10.1117/12.723664.
D. Guerrero Martos et al., “Automatic logic synthesis for parallel alternating latches clocking schemes,” SPIE Digital Library, 2007, doi: 10.1117/12.723664.
@misc{guerreromartos2007automatic,
author = {Guerrero Martos, David and Bellido Díaz, Manuel Jesús and Juan Chico, Jorge and Millán Calderón, Alejandro and Ruiz de Clavijo Vázquez, Paulino and Ostúa Arangüena, Enrique and Viejo Cortés, Julián},
title = {Automatic logic synthesis for parallel alternating latches clocking schemes},
year = {2007},
publisher = {SPIE Digital Library},
doi = {10.1117/12.723664},
url = {https://doi.org/10.1117/12.723664}
}
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