Automatic logic synthesis for parallel alternating latches clocking schemes

skew a) skew b) CLK1 < hold C L lip− lop logic skew Q0 D1 CLK2 K1 K2CL LK1C LOGIC CIRCUIT lip− lop 1 D0 DQ lip− lop lip− lop 2 D1 QQ1 ∆ C Au oma ic logic syn hesis o pa allel al e na ing la ches clocking schemes D. Gue e o, M. Bellido, J. Juan, A. Millan, P. Ruiz, E. Os ua, J. Viejo Dep . o Elec onic Technology, Uni e si y o Se ille, Escuela Técnica Supe io de Ingenie ía In o má ica, A da. de Reina Me cedes S/N, 41012 Se illa, Spain ABSTRACT This pape p oposes a VHDL coding echnique ha allows o he au oma ic syn hesis o digi al ci cui s using he so called Pa allel Al e na ing La ches Clocking Schemes (PALACS). The p oposed me hod g ea ly imp o es he applicabili y o PALACS and i s bene i s. This echnique is e i ied h ough design examples in h ee di e en CMOS p ocesses and using logic le el simula ion, wi h success ul esul s in all he cases. Keywo ds: Clock skew ole ance, high speed CMOS design, CAD ci cui design 1. INTRODUCTION VLSI digi al sys ems ha e e ol ed o big and mo e complex sys ems being clocked a e y high equency. This e olu ion has eached a poin ha he o e head o he clock in he o m o powe consump ion has become unaccep able. This is con i med by wha is obse ed in high-pe o mance mic op ocesso s1. So, educing he powe due o clock signal dis ibu ion is a manda o y issue in digi al design. On he o he hand, while he ga e size and, as a consequence, he ga e delay is ge ing smalle , he die size is ising. Since he delay in in e connec ion lines inc eases quad a ically wi h he line leng h, i becomes longe han ga e delay. Because o ha he skew inc eases signi ican ly. So, he simples clocking scheme based on edge- igge ed lip- lops should no be used o high-speed designs2,3,4 as illus a ed in Figu e 1a: As we can see, i he clock skew is e y long and he logic ci cui is as enough, he ac i e edge o he clock can each lip- lop 2 oo la e, i.e. nea he ins an when i s inpu is going o change. No e ha his p oblem can no be sol ed by enla ging he clock cycle5. To sol e his p oblem, i has been sugges ed ha he clock signal should each i s he egis e s a he end o he da a pa h. Clock skew could cause mal unc ion anyway, as we can see in Figu e 1b: I he clock skew is e y long, lip- lop 2 could be igge ed oo ea ly. This could be sol ed by enla ging he clock cycle, bu e- ou ing he clock pa h is no a solu ion i eedback exis s in he da a pa h. logic Q0 D LK2 b) < se up lip− lop logic skew Q0 D1 a) Fig. 1. Skew ela ed p oblems in a single-phase sys em wi h lip- lops. In o de o p e en he clock skew om causing mal unc ion, a wo-phase clocking scheme may be used. Two-phase clocking sys ems use wo dis inc clocks gene a ed om he main clock a he las bu e ing s age. An example o wo- phase clocking scheme is he wo-phase Mas e -Sla e clocking scheme (MSCS), which uses Mas e -Sla e s uc u es o implemen he egis e block. A Mas e -Sla e egis e wo king and i s ch onog am is shown in Figu e 2, whe e i is assumed ha he egis e s a e anspa en a he high le el o he load signal. skew skew 0 01 01 0 C LK C LK 1 0 C LK Q 1 0 D´ sepa a ion sla e a) 01001 hold logic LATCH MASTER SLAVE LATCH LATCH MASTER SLAVE LATCH D CLK CLK CLK´ CLK´ LOGIC load load load load CIRCUIT QQD’ Q’ Q’ b) Fig. 2. Mas e -Sla e clocking scheme a) Ci cui b) Ch onog am. An al e na i e o MSCS a e he Pa allel Al e na ing La ches Clocking Schemes (PALACS)6,7. Like MSCS, PALACS p o ides skew ole ance by using mul iple clock signals, bu ha e ema kable ad an ages in powe consump ion and ope a ion speed6,7. Besides, ha dwa e desc ip ion languages (HDL) a e e y con enien ools o design digi al ci cui s, and logic syn hesis so wa e is commonly used o p oduce logic-le el desc ip ions om high le el HDL code. When coding a design in a HDL, he designe mus ollow a se o ules o ensu e he desc ip ion can be p ope ly handled by he au oma ic syn hesis ool. Thus, so-called canonical coding s yles whe e combina ional and sequen ial beha iou a e clea ly de ined a e p e e ed by logic syn hesis ools, ha usually deal wi h implemen a ion de ails like he elec ion o lip- lops and o he logic blocks om he s anda d lib a y p o ided by he echnology iles. In a ull synch onous design, he usual coding echniques will ypically p oduce single-edge- igge ed lip- lops con olled by he same clock signal. In o de o make use o PALACS in HDL desc ip ions, he sequen ial elemen s mus be coded in a way ha he logic syn hesis ools can manage. In his pape he au ho s desc ibe VHDL coding echniques o au oma ically syn hesise a bi a y ci cui s employing wo- phase PALACS and ou -phase PALACS. Ta ge ing his objec i e, his pape is o ganised as ollows: In he nex sec ion he PALACS clocking schemes will be summa ised. In he ollowing sec ion a VHDL coding echnique o desc ibe ci cui s employing PALACS will be in oduced. In he ou h sec ion he co ec ness o hese desc ip ions will be checked h ough au oma ic logic syn hesis and logic-le el simula ion. Finally he conclusions summa ised. 2. PARALLEL ALTERNATING LATCHES CLOCKING SCHEME 2.1 Two-phase PALACS A ema kable al e na i e o he one-phase single-edge igge ed lip- lop clocking scheme is he one-phase double-edge igge ed lip- lop clocking scheme8,9. This scheme uses he lip- lop shown in Figu e 3, ha is igge ed by bo h, alling and ising ansi ions o he clock signal. The powe consump ion o he clock dis ibu ion ne wo k in his scheme is smalle han using single-edge igge ed lip- lops since he e is an only clock ansi ion pe compu a ion cycle. D load LATCH 0 load LATCH 1 D QD clk clk 0 Q1 s Q MUX Fig. 3. Double-edge igge ed lip- lop. We could say ha he one-phase single-edge- igge ed lip- lop clocking scheme is a pa icula case o he MSCS whe e he sla e clock signal is ob ained by in e ing he mas e clock signal, i.e. a pa icula case whe e he non-o e lapping ime be ween he clock signals is ze o. The ad an age o he gene al MSCS is ha i p o ides ole ance o an a bi a y skew by enla ging he non-o e lapping egion. In a simila way, he wo-phase Pa allel Al e na ing La ches Clocking Scheme ( wo-phase PALACS)6 depic ed in Figu e 4 is a gene alisa ion o he one-phase double-edge- igge ed lip- lop clocking scheme. The memo y elemen used in his scheme consis s o wo la ches connec ed in pa allel sha ing he same inpu , and a swi ch a he ou pu o each la ch whose ou pu s a e connec ed. The load e minals o bo h la ches a e con olled by sepa a e phases, and he swi ches a e also con olled by opposi e phases. This scheme, unlike he Mas e -Sla e scheme, allows eading and w i ing he egis e block simul aneously du ing he ac i e le el o each clock phase. When clock signal CLK0 is ac i e, la ch 0 loads he cu en inpu while la ch 1 holds he p e ious inpu . The la ch 1 da a is ead in he ac i e phase o CLK0, since i s swi ch is con olled by CLK0. When CLK0 becomes inac i e, la ch 0 s ops being anspa en . Then bo h phases emain inac i e a ime in e al long enough o a oid clock-skew ela ed p oblems. Du ing his in e al bo h swi ches a e in high impedance (H.I.) s a e, bu he p e ious da a alue emains loaded a he swi ches ou pu due o pa asi ic capaci ances. When CLK1 ac i a es, he ead-w i e mechanism wo ks again, bu bo h la ches al e na e hei unc ion, i.e. la ch 1 loads a new alue while la ch 0 is ead. We could say ha his clocking scheme is he wo-phase coun e pa o he one-phase double-edge igge ed lip- lop clocking scheme6,7. a) CLK1 CLK0 CLK1CLK0 CLK1CLK0 CLK0 D Q0 Q1 Q CLK1 S0 S2 S0 S1 S2 S3 S1 S3S−1 S − 1 S0 S1 S2 Q’ LOGIC Q0 QD’ D load Q1 load Q’0 load Q’1 load LATCH 0 LATCH 1 LATCH 0 LATCH 1 CIRCUIT CLK1 CLK0 b) Fig. 4. Two-phase PALACS. a) Ci cui b) Ch onog am. The mos impo an ad an age o PALACS e sus MSCS is ha he clock equency is educed by 50% o he same da a a e. This has conside able bene i s, mainly in he educ ion o he powe consumed by he clock dis ibu ion ne wo k. In PALACS, he numbe o clock ansi ions is wo pe compu a ion cycle whe eas in MSCS i is ou . This means ha hei powe dissipa ion can be educed up o 50%. Ano he in e es ing ad an age is ha , o some implemen a ions, he p opaga ion delay o he PALACS s uc u e is smalle han he p opaga ion delay o he Mas e - Sla e since wi h he MSCS he inpu signal has o p opaga e h ough wo la ches whe eas in PALACS i has o p opaga e h ough one la ch and a swi ch (whose delay is usually smalle han he delay o a la ch). This p oduces an imp o emen in he ope a ion speed o he sys em. 2.2 Fou -phase PALACS A d awback o he wo phase PALACS is ha he aising edges o he load con ol signals a e ha d edges10. This means ha , ega dless o he ins an when a da a i em eaches a la ch ou pu , i will no keep p opaga ing h ough he ci cui un il he load con ol signal o he opposi e la ch ecei e he nex aising edge. In ou -phase PALACS (Figu e 5), he load con ol signals and he ou pu enable con ol signals a e no he same. So, a da a i em a he ou pu o a la ch can begin o p opaga e h ough he ci cui e en i ha i em has no been la ched ye p o ided ha he con amina ion delay o he logic ci cui is long enough. So, he pe o mance o he sys em can be imp o ed by using ime bo owing echniques10 a he expense o using addi ional clock phases. a) b) OE0 Q0 Q1 Q D C LK1 C LK0 S0 S1 S2 S3 S1 S2 S3 S4 S0 S2 S1 S3 OE1 Q’ LOGIC CIRCUIT Q0 QD’ D load LATCH 0 Q1 OE1 load LATCH 1 Q’0 OE0 load LATCH 0 Q’1 OE1 load LATCH 1 OE0CLK0 CLK1 CLK0 CLK1 Fig. 5. Fou -phase PALACS. a) Ci cui b) Ch onog am. 3. VHDL CODING TECHNIQUES FOR PALACS As i was s a ed in he in oduc ion, he possibili y o desc ibe digi al ci cui s using PALACS using ha dwa e desc ip ion languages is essen ial o apply his clocking scheme in an ex ensi e manne . The objec i e o his sec ion is o p esen a VHDL coding echnique o PALACS ha is ully syn hesizable by common logic syn hesis ools, so ha PALACS can be easily included in he s anda d digi al design p ocess. The p ocess o code a design using PALACS can be di ided in h ee s eps: • Desc ip ion o a la ch wi h i-s a e ou pu • Desc ip ion o he PALACS s uc u e • Coding he combina ional pa and ins an ia ion o he PALACS s uc u es The i s s ep, shown in Figu e 6, is common o any design using PALACS and desc ibes a single la ch ollowed by a i- s a e bu e , which is he basic building block o PALACS. Logic syn hesis ools will ypically ende he s uc u e in a single lib a y la ch wi h an ou pu -enable con olling signal, o a la ch plus a i-s a e bu e , depending on wha is a ailable in he s anda d lib a y. Fig. 6. VHDL desc ip ion o a i-s a e ou pu la ch. In The second s ep, which is also common o any design, wo ins ances o he p e ious desc ip ion a e used o build up he PALACS s uc u e using he s uc u al VHDL desc ip ion o Figu e 7. The use o a s uc u al desc ip ion makes i possible o ha e be e con ol o e he au oma ic syn hesis p ocess and p e en he syn hesis ools om changing he desi ed opology. en i y palacs4 is po (d, noe0, noe1, clk0, clk1, ncl : in s d_logic;q : ou s d_logic); end palacs4; a chi ec u e mys uc o palacs4 is componen la chOEcl po (d, noe, ld, ncl : in s d_logic; q : ou s d_logic); end componen ; begin la ch0 : la chOEcl p o ma p ( d=>d,noe=>noe0,ld=>clk0,ncl =>ncl , q => q) ; en i y la chOEcl is gene ic( n: in ege := 1); po (d,noe, ld, ncl : in s d_logic;q: ou s d_logic); end la chOEcl ; a chi ec u e beha iou o la chOEcl is signal qi: s d_logic; begin assign: p ocess(ld, d, ncl ) begin i ld='1' hen qi<=d; end i ; i ncl ='0' hen qi<='0'; end i ; end p ocess; myou pu : p ocess(qi,noe) begin q<='Z'; i noe='0' hen Fig. 7. VHDL desc ip ion o he PALACS s uc u e. In he hi d s ep, ins ances o he PALACS s uc u e a e added o he design in o de o implemen he sequen ial pa . As an example, a ising ou -bi coun e is desc ibed in Figu e 8. This desc ip ion is simila o he canonical s a e machine coding s yle, whe e he p ocess con olling he e olu ion o he nex s a e has been subs i u ed by he placemen o a se o PALACS cells using a gene a e s a emen . No e ha bo h, wo-phase PALACS and ou -phase PALACS can be implemen ed in his way, since wo-phase PALACS is a pa icula case o ou -phase PALACS whe e he ou pu enable signals a e he same ha he load con ol signals. Fig. 8. VHDL desc ip ion o a ou bi coun e . 4. VERIFICATION OF THE VHDL DESCRIPTION STYLE FOR PALACS In o de o e i y his VHDL coding echnique, he desc ip ion o he ou -bi coun e o Figu e 8 has been used. Two- phase PALACS has been employed. To check he unc ionali y, he ci cui has been simula ed a he logic le el. The esul is shown in Figu e 9. As we can see, he coun e wo ks p ope ly. Rema kably, he s a e signals a e in high impedance when bo h ou pu enable signals a e disabled. This will no eally occu due o pa asi ic capaci ances6,7. en i y cn Mod16 is po (noe0,noe1,clk0,clk1,ncl : in s d_logic; myou pu : ou s d_logic_ ec o (3 down o 0)); end cn Mod16; a chi ec u e mys uc o cn Mod16 is signal s d_cn ,nx _s d: unsigned (3 down o 0); componen palacs4 po (d,noe0,noe1,clk0,clk1,ncl : in s d_logic;q: ou s d_logic); end componen ; begin my_logic: p ocess(s d_cn ) begin myou pu <=s d_logic_ ec o (s d_cn ); nx _s d<=s d_cn +1; end p ocess; gene a e_ egis e s: o i in 3 down o 0 gene a e Fig. 9. Logic simula ion o he ou -bi coun e . Also, in o de o check ha he code can be syn hesized in any echnology, he code has been compiled using he Design Analyse ool om Synopsis11. The componen s we e success ully syn hesized in a 0.35 µm CMOS p ocess om Aus ia Mic o Sys ems12, as well as in a 0.18 µm and 0.13 µm p ocesses om Uni ed Mic oelec onics Co po a ion13, gi ing simila esul s. As an example, Figu e 10 shows he esul ing implemen a ion o he la ch-bu e block (Figu e 10a), and he PALACS s uc u e (Figu e 10b) o he 0.18 µm echnology. I can be easily obse ed how he logic syn hesis ool has selec ed app op ia e componen s om he s anda d lib a y p o ided by he ound y while keeping he desi ed unc ionali y and opology o he PALACS s uc u e. The ne lis gene a ed o he ou -bi coun e is depic ed in Figu e 11. Fou PALACS s uc u es has been placed as indica ed in he VHDL desc ip ion (Figu e 8) and addi ional logic has been au oma ically syn hesized o achie e he desi ed unc ionali y. d ld n cl n oe d clk0 cl noe0 clk1 noe1 b)a) q LATRNB4 INVTD12 la chOEcl la chOEcl q Fig. 10. Ci cui s syn hesized by he ool a) T i-s a e ou pu la ch b) PALACS s uc u e. clk0 clk1 ncl n oe0 n oe1 INVD1 NAND2D1 NOR2M1D1 EXOR2D1 EXNOR2D1 EXNOR2D1 myou pu {3:0} palacs4_0 palacs4_1 palacs4_2 palacs4_3 Fig. 11. The ne lis gene a ed by he ool o he ou -bi coun e . 5. CONCLUSIONS In p e ious wo ks, new clocking schemes called PALACS we e in oduced in o de o sol e clock skew ela ed p oblems. In his pape , a VHDL coding echnique is explo ed so ha a bi a y sequen ial ci cui s can be au oma ically syn hesized using PALACS. This echnique is easily applied by e-de ining he egis e block o he design. A sample VHDL design has been success ully implemen ed in h ee CMOS p ocesses om wo di e en ound ies showing ha he p oposed VHDL desc ip ions a e ully syn hesizable and p oduce he igh s uc u es and beha iou , which has been checked h ough logic-le el simula ion. This esul allow o a much wide and easie applica ion o PALACS o gene al digi al design. ACKNOWLEDGEMENTS This wo k has been pa ially suppo ed by he Spanish Go e nmen ’s MEC META p ojec TEC-2004-00840-MIC and he Andalusian Regional Go e nmen ’s CICE DHPMNDS p ojec s EXC-TIC-1023 and EXC-TIC-635. REFERENCES 1. V. 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