Edi o ial
Powe and iming modelling, op imisa ion and simula ion
P ac ical implemen a ions o digi al VLSI ci cui s a e mo e
and mo e limi ed by powe and iming cons ain s. On one
hand, dissipa ing and educing he inc easing powe densi y
in mode n high pe o mance VLSI co es has become a
ypical design cons ain ; on he o he hand, a wide
spec um o po able appliances demands o lowe powe
consump ions in o de o sa e ba e y li e. All o hese
powe -de i ed cons ain s come oge he wi h he highe
pe o mance demands ha call o agg essi e iming
op imisa ion echniques.
In his scena io, he design and e i ica ion o cu en
VLSI ci cui s and sys ems hea ily elies on powe and
iming es ima ion echniques commonly implemen ed
in CAD ools h ough he use o beha iou al models.
The de elopmen o hese models and ools has become
a majo issue in he las decade, oge he wi h he
imp o emen o low-powe and high-pe o mance design
me hods.
Since VLSI in eg a ion has eached he le el o
hund eds o million ansis o s in a single chip, ull
sys em e i ica ion a he ansis o o ga e le els is no
longe easible, leading o a a ie y o powe and iming
es ima ion and design echniques ha apply o di e en
le els o abs ac ion wi h e y di e en co e age and
accu acy objec i es. The e a e se e al aspec s ha need
a en ion om bo h esea ch and de elopmen , including:
†Low-powe design
†Timing-d i en design
†Powe and iming modelling
†Logic-le el powe and iming simula ion
†High-le el powe and iming simula ion
†Ins uc ion-le el op imisa ion
†Low-powe encoding echniques.
The mo i a ion behind b inging oge he his Special
Sec ion was bo n a he In e na ional Wo kshop on Powe
and Timing Modelling, Op imisa ion and Simula ion
(PATMOS) held in Tu in in Sep embe 2003. This was he
hi een h in a se ies o in e na ional wo kshops held in
se e al loca ions in Eu ope. O e he yea s, PATMOS has
gained ecogni ion as one o he majo Eu opean e en s
de o ed o he powe and iming aspec s o in eg a ed
ci cui and sys em design. P oceedings o his mee ing a e
a ailable h ough Sp inge -Ve lag’s Lec u e No es in
Compu e Science collec ion. Some o he mos app ecia ed
con ibu ions o his edi ion o he wo kshop, co e ing majo
opics o he a ea, ha e been expanded and upda ed o his
Special Sec ion o IEE P oceedings Compu e & Digi al
Techniques. All his has been possible hanks o he excellen
wo k and suppo o he IEE edi o ial s a and he PATMOS
Technical P og am Commi ee.
JORGE JUAN
DIMITRIOS SOUDRIS
ENRICO MACII
IEE P oceedings online no. 20059075
doi:10.1049/ip-cd :20059075
D Jo ge Juan ecei ed a BSc
deg ee (1994) and a PhD deg ee in
physics (2000) om he Uni e si y
o Se ille, Spain. He has been
wi h he Elec onics Technology
Depa men a he same uni e si y
since 1995. He is also wi h he
Ins i u e o Mic oelec onics o
Se ille, pa o he Na ional Cen e
o Mic oelec onics in Spain
(CNM-CSIC), since 1995. D Juan
has done esea ch in he a eas o me as abili y, delay
modelling, logic le el simula ion and ac i i y and powe
es ima ion, whe e he has au ho ed wo books, and mo e
han 50 esea ch pape s in in e na ional jou nals
con e ences. He has been gues edi o o Sp inge -
Ve lag’s Lec u e No es in Compu e Science and he IEE
P oceedings Compu e s & Digi al Techniques.Heis
membe o he s ee ing and p og am commi ees o he
IEEE Wo kshop on Powe and Timing Modelling
(PATMOS), being gene al chai in 2002 and p og am
chai in 2003. He has also ac ed as e iewe o a numbe
o in e na ional jou nals such as IEEE T ansac ions on
Compu e s, Else ie ’s In eg a ion, and in e na ional
con e ences such as ISCAS and DATE. He has pa icipa ed
in a numbe o Eu opean and na ional p ojec s ounded by
he Spanish go e nmen .
Dimi ios Soud is ecei ed his
diploma in elec ical enginee ing
om he Uni e si y o Pa as,
G eece, in 1987. He ecei ed his
PhD in elec ical enginee ing
om he Uni e si y o Pa as in
1992. He is cu en ly wo king as
an assis an p o esso in he
Depa men o Elec ical and
Compu e Enginee ing, Democ i us
Uni e si y o Th ace, G eece. His
esea ch in e es s include low-powe design, embedded
sys ems design, and VLSI signal p ocessing. He has pub-
lished mo e han 120 pape s in in e na ional jou nals and
con e ences. He is leade and p incipal in es iga o in
nume ous esea ch p ojec s unded om he G eek go e n-
men and indus y as well as he Eu opean Commission
(ESPRIT II-III-IV and 5 h IST). He has se ed as gene al
chai and p og am chai o he In e na ional Wo kshop
on Powe and Timing Modelling, Op imisa ion, and
Simula ion (PATMOS). Recen ly, he ecei ed an awa d
om INTEL and IBM o he p ojec esul s o LPGD
#25256 (ESPRIT IV) and awa ds om VLSI 2005 and
ASP-DAC 05 o he esul s o he p ojec AMDREL
IST-2001-34379. Finally, he is a membe o he IEEE, he
VLSI Sys ems and Applica ions Technical Commi ee o
IEEE CAS and he ACM.
IEE P oc.-Compu . Digi . Tech., Vol. 152, No. 6, No embe 2005 721
En ico Macii holds a DEng deg ee
in elec ical enginee ing om
Poli ecnico di To ino, I aly, a DSc
deg ee in compu e science om
Uni e si a’ di To ino, and a PhD
in compu e enginee ing om
Poli ecnico di To ino. F om 1991
o 1994 he was an adjunc acul y
a he Uni e si y o Colo ado a
Boulde . Cu en ly, he is a ull
p o esso o compu e enginee ing
a Poli ecnico di To ino. His esea ch in e es s include
se e al aspec s o he compu e -aided design o in eg a ed
ci cui s and sys ems. He has au ho ed o e 250 jou nal
and con e ence a icles in hese a eas including a pape
ha ecei ed he ‘Bes Pape ’ awa d a he 1996
IEEE Eu oDAC con e ence. En ico Macii is an associa e
edi o o he IEEE T ansac ions on CAD and an
associa e edi o o he ACM T ansac ions on Design
Au oma ion. He was he echnical p og am co-chai o he
IEEE Alessand o Vol a Memo ial Wo kshop on Low
Powe Design in 1999, he echnical p og am co-chai and
he gene al chai o he ACM/IEEE In e na ional
Symposium on Low Powe Elec onics and Design
(ISLPED) in 2000 and 2001, espec i ely, he gene al
chai and he echnical p og am chai o he IEEE
PATMOS wo kshop in 2003 and 2004, espec i ely. He is
a senio membe o he IEEE, and a membe o he
boa d o go e no s o he IEEE Ci cui s and Sys ems
Socie y.
IEE P oc.-Compu . Digi . Tech., Vol. 152, No. 6, No embe 2005722