Power and timing modelling, optimisation and simulation

Editorial Power and timing modelling, optimisation and simulation Practical implementations of digital VLSI circuits are more and more limited by power and timing constraints. On one hand, dissipating and reducing the increasing power density in modern high performance VLSI cores has become a typical design constraint; on the other hand, a wide spectrum of portable appliances demands for lower power consumptions in order to save battery life. All of these power-derived constraints come together with the higher performance demands that call for aggressive timing optimisation techniques. In this scenario, the design and verification of current VLSI circuits and systems heavily relies on power and timing estimation techniques commonly implemented in CAD tools through the use of behavioural models. The development of these models and tools has become a major issue in the last decade, together with the improvement of low-power and high-performance design methods. Since VLSI integration has reached the level of hundreds of million transistors in a single chip, full system verification at the transistor or gate levels is no longer feasible, leading to a variety of power and timing estimation and design techniques that apply to different levels of abstraction with very different coverage and accuracy objectives. There are several aspects that need attention from both research and development, including: †Low-power design †Timing-driven design †Power and timing modelling †Logic-level power and timing simulation †High-level power and timing simulation †Instruction-level optimisation †Low-power encoding techniques. The motivation behind bringing together this Special Section was born at the International Workshop on Power and Timing Modelling, Optimisation and Simulation (PATMOS) held in Turin in September 2003. This was the thirteenth in a series of international workshops held in several locations in Europe. Over the years, PATMOS has gained recognition as one of the major European events devoted to the power and timing aspects of integrated circuit and system design. Proceedings for this meeting are available through Springer-Verlag’s Lecture Notes in Computer Science collection. Some of the most appreciated contributions to this edition of the workshop, covering major topics of the area, have been expanded and updated for this Special Section of IEE Proceedings Computer & Digital Techniques. All this has been possible thanks to the excellent work and support of the IEE editorial staff and the PATMOS Technical Program Committee. JORGE JUAN DIMITRIOS SOUDRIS ENRICO MACII IEE Proceedings online no. 20059075 doi:10.1049/ip-cdt:20059075 Dr Jorge Juan received a BSc degree (1994) and a PhD degree in physics (2000) from the University of Seville, Spain. He has been with the Electronics Technology Department at the same university since 1995. He is also with the Institute of Microelectronics of Seville, part of the National Centre of Microelectronics in Spain (CNM-CSIC), since 1995. Dr Juan has done research in the areas of metastability, delay modelling, logic level simulation and activity and power estimation, where he has authored two books, and more than 50 research papers in international journals conferences. He has been guest editor for SpringerVerlag’s Lecture Notes in Computer Science and the IEE Proceedings Computers & Digital Techniques.Heis member of the steering and program committees of the IEEE Workshop on Power and Timing Modelling (PATMOS), being general chair in 2002 and program chair in 2003. He has also acted as reviewer for a number of international journals such as IEEE Transactions on Computers, Elsevier’s Integration, and international conferences such as ISCAS and DATE. He has participated in a number of European and national projects founded by the Spanish government. Dimitrios Soudris received his diploma in electrical engineering from the University of Patras, Greece, in 1987. He received his PhD in electrical engineering from the University of Patras in 1992. He is currently working as an assistant professor in the Department of Electrical and Computer Engineering, Democritus University of Thrace, Greece. His research interests include low-power design, embedded systems design, and VLSI signal processing. He has published more than 120 papers in international journals and conferences. He is leader and principal investigator in numerous research projects funded from the Greek government and industry as well as the European Commission (ESPRIT II-III-IV and 5th IST). He has served as general chair and program chair for the International Workshop on Power and Timing Modelling, Optimisation, and Simulation (PATMOS). Recently, he received an award from INTEL and IBM for the project results of LPGD #25256 (ESPRIT IV) and awards from VLSI 2005 and ASP-DAC 05 for the results of the project AMDREL IST-2001-34379. Finally, he is a member of the IEEE, the VLSI Systems and Applications Technical Committee of IEEE CAS and the ACM. IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 6, November 2005 721 Enrico Macii holds a DEng degree in electrical engineering from Politecnico di Torino, Italy, a DSc degree in computer science from Universita’ di Torino, and a PhD in computer engineering from Politecnico di Torino. From 1991 to 1994 he was an adjunct faculty at the University of Colorado at Boulder. Currently, he is a full professor of computer engineering at Politecnico di Torino. His research interests include several aspects of the computer-aided design of integrated circuits and systems. He has authored over 250 journal and conference articles in these areas including a paper that received the ‘Best Paper’ award at the 1996 IEEE EuroDAC conference. Enrico Macii is an associate editor of the IEEE Transactions on CAD and an associate editor of the ACM Transactions on Design Automation. He was the technical program co-chair of the IEEE Alessandro Volta Memorial Workshop on Low Power Design in 1999, the technical program co-chair and the general chair of the ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED) in 2000 and 2001, respectively, the general chair and the technical program chair of the IEEE PATMOS workshop in 2003 and 2004, respectively. He is a senior member of the IEEE, and a member of the board of governors of the IEEE Circuits and Systems Society. IEE Proc.-Comput. Digit. Tech., Vol. 152, No. 6, November 2005722