QESNN: Quan um-Enhanced Spiking Neu al
Ne wo k on FPGA o Real-Time Indus ial
Anomaly De ec ion
Deena hayalan A1
Depa men o Elec onics and Communica ion Enginee ing
SRM Ins i u e o Science and Technology
Chennai, India
[email p o ec ed]
Tanush ee RG2
Depa men o Elec onics and Communica ion Enginee ing
SRM Ins i u e o Science and Technology
Chennai, India
[email p o ec ed]
Kee ana P3
Depa men o Elec onics and Communica ion Enginee ing
SRM Ins i u e o Science and Technology
Chennai, India
[email p o ec ed]
Abs ac —Indus ial B ushless DC mo o sys ems equi e
eal- ime anomaly de ec ion wi h s ingen powe and la ency
cons ain s unsui able o adi ional deep lea ning app oaches.
We p esen QESNN, a Quan um-Enhanced Spiking Neu al
Ne wo k implemen ed on low-cos FPGA ha dwa e, achie ing
92.12% classi ica ion accu acy wi h 4.10ms in e ence la ency and
265mW powe consump ion. The sys em in oduces quan um-
inspi ed Spike-Timing-Dependen Plas ici y (Q-STDP) lea ning
ha cap u es mul i-spike empo al co ela ions, ou pe o ming
classical SNNs by 27.9% in accu acy while educing powe
consump ion by 45.4%. Implemen ed on a Sipeed Tang Nano
4K FPGA (2,124 LUTs, 46% u iliza ion), he neu omo phic a -
chi ec u e p ocesses 246.28 samples/second wi h 100% p ecision
and 0.869 F1 Sco e on IMAD indus ial senso da a. Comp e-
hensi e benchma king ollowing SNABSui e and Neu oBench
p o ocols alida es QESNN as p oduc ion- eady o ba e y-
powe ed edge compu ing, enabling p edic i e main enance wi h
sub-3000 INR ha dwa e cos . The e en -d i en design achie es
0.0014 mJ/in e ence ene gy e iciency, demons a ing p ac ical
neu omo phic compu ing a scale.
Index Te ms—Neu omo phic Compu ing, Spiking Neu al Ne -
wo ks, FPGA Implemen a ion, Anomaly De ec ion, STDP Lea n-
ing, Edge AI, Indus ial IoT
I. INTRODUCTION
Indus ial b ushless mo o sys ems gene a e con inuous
ime-se ies da a equi ing eal- ime anomaly de ec ion o p e-
dic i e main enance [1]. T adi ional deep lea ning app oaches
ace c i ical deploymen ba ie s: Con olu ional Neu al Ne -
wo ks (CNNs) consume 920mW wi h 15.2ms la ency, while
LSTMs equi e 1150mW and 22.5ms—bo h unsui able o
ba e y-powe ed edge de ices [2]. Classical Spiking Neu al
Ne wo ks (SNNs) o e e en -d i en e iciency bu achie e
only 72% accu acy wi h limi ed empo al lea ning capaci y
[3].
A. Mo i a ion
The neu omo phic compu ing pa adigm, inspi ed by biolog-
ical neu al p ocessing, encodes in o ma ion in spike iming
a he han ac i a ion a es [4]. This enables h ee c i ical ad-
an ages: (1) ene gy e iciency h ough spa se compu a ion—
neu ons consume powe only du ing spike e en s; (2) em-
po al pa e n ecogni ion h ough Spike-Timing-Dependen
Plas ici y (STDP); (3) ha dwa e pa allelism ia e en -d i en
p ocessing [5].
Howe e , exis ing FPGA-based SNNs su e om wo lim-
i a ions: classical pai -based STDP cap u es only di ec p e-
pos spike iming, ailing on complex empo al sequences [6],
and ha dwa e implemen a ions lack on-chip lea ning, equi ing
o line aining [7].
B. Con ibu ions
This wo k in oduces QESNN, a comple e neu omo phic
sys em add essing hese gaps:
•Quan um-Enhanced STDP: No el lea ning mechanism
wi h empo al ace egis e s enabling mul i-spike co e-
la ion lea ning, achie ing 27.9% accu acy imp o emen
o e classical STDP.
•Ha dwa e-Op imized A chi ec u e: Syn hesizable Ve -
ilog design wi h 30 pa allel Q-STDP synapses and 10
Leaky In eg a e-and-Fi e (LIF) neu ons on 4608-LUT
FPGA.
•End- o-End Sys em: Comple e pipeline om IMAD
da ase p ep ocessing h ough UART-based eal- ime in-
e ence wi h bidi ec ional communica ion.
•Comp ehensi e Benchma king: Valida ion ollow-
ing SNABSui e/Neu oBench p o ocols demons a ing
92.12% accu acy, 4.10ms la ency, 265mW powe , and
0.869 F1 Sco e.
The QESNN sys em alida es neu omo phic compu ing ea-
sibili y on sub-3000 INR educa ional ha dwa e, democ a izing
access o b ain-inspi ed AI accele a o s.
II. RELATED WORK
A. Neu omo phic Compu ing Sys ems
La ge-scale neu omo phic pla o ms including In el Loihi
[8], IBM T ueNo h [9], and SpiNNake [10] demons a e
million-neu on implemen a ions bu cos $500–$5000 pe chip.
Recen FPGA-based SNNs achie e 88.5% accu acy a 180mW
[11] bu lack on-chip lea ning mechanisms.
B. STDP Lea ning Algo i hms
Classical pai -based STDP [12] upda es weigh s h ough
exponen ial ace decay: ∆w=A+exp(−∆ /τ+) o p e-
be o e-pos iming. Ex ensions including iple -STDP [13]
and me a-plas ici y [14] imp o e empo al lea ning bu equi e
complex analog ci cui s unsui able o digi al FPGA imple-
men a ion.
C. Indus ial Anomaly De ec ion
The IMAD da ase [1] p o ides eco dings om indus-
ial b ushless mo o machines wi h labeled no mal/anomaly
segmen s. S a e-o - he-a app oaches include au oencode s
(74% accu acy, 850mW) [15] and GANs (76%, 920mW) [16].
Classical SNNs achie e 72% a 485mW [17], lea ing a 20-
poin accu acy gap mo i a ing his wo k.
III. QESNN ARCHITECTURE
A. Sys em O e iew
QESNN implemen s a hyb id ha dwa e-so wa e co-
design.The PC p ep ocessing pipeline con e s MIMII senso
da a o spike ains, ains he Q-STDP ne wo k o line, and
s eams es da a ia UART. The FPGA subsys em execu es
eal- ime in e ence h ough ou Ve ilog modules: UART e-
cei e , spike decode , synap ic laye , and LIF neu on laye .
Fig. 1. QESNN ha dwa e–so wa e a chi ec u e.
B. Quan um-Enhanced STDP Synapse
The Q-STDP synapse ex ends classical STDP wi h pe sis-
en ace egis e s:
∆w=
+5 i pos -spike ∧p e- ace ac i e
−5i p e-spike ∧pos - ace ac i e
0o he wise
(1)
Unlike exponen ial decay equi ing loa ing-poin
ope a ions, bina y aces (p e_ ace_ac i e,
pos _ ace_ac i e) enable single-cycle ha dwa e
upda es. T aces pe sis ac oss mul iple clock cycles (up
o 234 cycles = 8.68µs a 27MHz), cap u ing mul i-spike
pa e ns wi hin 10ms windows.
The ha dwa e implemen a ion uses 24 LUTs pe synapse:
always @(posedge clk) begin
i (pos _spike && p e_ ace_ac i e) begin
i (weigh < 250) weigh <= weigh + 5;
p e_ ace_ac i e <= 0;
end else i (p e_spike && pos _ ace_ac i e) begin
i (weigh > 10) weigh <= weigh - 5;
pos _ ace_ac i e <= 0;
end else begin
i (p e_spike) p e_ ace_ac i e <= 1;
i (pos _spike) pos _ ace_ac i e <= 1;
end
end
C. LIF Neu on Dynamics
Each ou pu neu on main ains 16-bi memb ane po en ial
Vmupda ed pe clock cycle:
Vm( +1) = (0i Vm( )≥V h esh
Vm( ) + Piwisi( )−Vleak o he wise
(2)
whe e wia e 8-bi synap ic weigh s, si( )a e inpu spikes,
V h esh = 800, and Vleak = 1. High h eshold equi es empo al
summa ion o 6–8 spikes, il e ing single-spike noise while
esponding o bu s pa e ns.
The pa allel neu on implemen a ion (10 ins ances) con-
sumes 890 LUTs (19.3% o o al):
gene a e
o (j = 0; j < 10; j = j + 1) begin: neu ons
eg [15:0] memb ane_po en ial = 0;
always @(posedge clk) begin
i (memb ane_po en ial >= V_THRESH)
memb ane_po en ial <= 0;
else i (|inpu _spikes)
memb ane_po en ial <= memb ane_po en ial +
weigh ed_sum[j] - V_LEAK;
else i (memb ane_po en ial > V_LEAK)
memb ane_po en ial <= memb ane_po en ial - V_LEAK;
end
assign ou pu _spikes[j] =
(memb ane_po en ial >= V_THRESH);
end
endgene a e
D. UART Communica ion P o ocol
Bidi ec ional 115200-baud UART enables PC-FPGA
s eaming. The ecei e dese ializes 8-bi spike da a h ough
a 4-s a e FSM (Idle →S a Bi →8 Da a Bi s →S op Bi ),
equi ing 234 clock cycles (8.68µs) pe by e a 27MHz. Spike
encoding maps by es o one-ho ep esen a ion:
By e b→Spike ec o s= [s0, s1, s2]whe e si=δb,i (3)
The ansmi e se ializes i ing neu on IDs (0x00–0x09) o
classi ica ion ou pu .
IV. IMPLEMENTATION
A. Ha dwa e Pla o m
Ta ge FPGA: Sipeed Tang Nano 4K (Gowin GW1NSR-
LV4C), 4608 LUTs, 180KB BRAM, 27MHz clock, cos : 2850
INR. SRAM p og amming mode enables apid i e a ion (sub-
10s econ igu a ion).
B. Resou ce U iliza ion
Syn hesis in Gowin EDA 1.9.9 yields:
TABLE I
FPGA RESOURCE UTILIZATION
Module LUTs Regis e s Ins ances
UART RX 124 32 1
UART TX 156 38 1
Q-STDP Synapses 720 300 30
LIF Neu ons 890 160 10
Con ol Logic 234 85 1
To al 2124 615 43
Capaci y 4608 3456 –
U iliza ion 46.1% 17.8% –
Maximum achie able clock equency: 68.2MHz (152%
iming ma gin). Ze o BRAM usage enables pu e combina-
ional/sequen ial logic implemen a ion.
C. Da ase and P ep ocessing
MIMII obo ic a m da ase [1]: 10-hou eco dings om
accele ome e , gy oscope, mic ophone senso s. P ep ocessing
pipeline: (1) 100ms sliding windows wi h 50ms o e lap, (2)
ampli ude no maliza ion o [0, 1], (3) a e coding: senso alue
xmaps o spike p obabili y p=x, (4) bina y encoding: spike
e en s se ialized o 0x00/0x01/0x02 by e s eams.
T aining se : 7000 no mal samples, 2000 anomaly samples.
Tes se : 241 ull chunks (7720 by es). G ound u h: 70%
no mal, 30% anomaly ( ealis ic indus ial dis ibu ion).
V. EXPERIMENTAL RESULTS
A. Benchma k P o ocol
E alua ion ollows SNABSui e [18] and Neu oBench [19]
s anda ds ac oss h ee ials pe me ic. Hos sys em: Windows
10, Py hon 3.10, PySe ial 3.5. Communica ion: UART o e
USB-se ial (CH340 b idge, COM8).
B. Pe o mance Me ics
Table II summa izes QESNN pe o mance agains baselines:
Accu acy: 92.12% classi ica ion accu acy wi h con usion
ma ix: TN = 169 FP = 0
FN = 19 TP = 53
Pe ec p ecision (100%) elimina es alse ala ms, c i ical o
indus ial deploymen . Recall o 73.6% cap u es 3 o 4 ac ual
anomalies.
La ency: A e age 4.10ms ±0.418ms ac oss 100 ials.
B eakdown: UART RX (0.87ms) + neu al p ocessing (2.80ms)
+ UART TX (0.87ms) + hos o e head (0.40ms). The 14.6%
imp o emen o e classical SNN s ems om pa allel synapse
compu a ion (30 simul aneous mul iply-accumula e ope a-
ions).
Th oughpu : 246.28 samples/second (239.7% imp o emen
o e classical SNN’s 72.5 samples/s). Pipeline o e lap—
FPGA p ocesses chunk Nwhile ansmi ing esul N−1—
exceeds heo e ical maximum o 228 samples/s.
Ene gy E iciency: 0.0014 mJ/in e ence = 714,285 in e -
ences/joule. A 265mW, a 20,000mAh powe bank enables
21+ hou s con inuous ope a ion. The 45.4% powe educ ion
e sus classical SNN esul s om spa se spiking (68% neu on
u iliza ion) and high h eshold il e ing (800 equi es 6–8 spike
in eg a ion, educing spu ious i ing by 89%).
C. Abla ion S udies
Table III quan i ies Q-STDP con ibu ions:
Remo ing empo al aces educes accu acy by 17.77 poin s,
alida ing mul i-spike co ela ion lea ning. Weigh bounds [10,
250] p e en sa u a ion, con ibu ing 6.14 poin s.
VI. DISCUSSION
A. Quan um-Enhanced Lea ning Analysis
The 27.9% accu acy imp o emen s ems om Q-STDP’s
abili y o co ela e spike sequences. Classical pai -based STDP
wi h exponen ial decay τ= 20ms cap u es only di ec p e-pos
iming:
∆wclassical =A+exp −|∆ |
τ o |∆ |< τ (4)
Spikes sepa a ed by >20ms con ibu e negligible weigh
upda es (<5% o A+). In con as , Q-STDP’s bina y aces
pe sis o 234 clock cycles (8.68µs a 27MHz), enabling
co ela ion windows up o 50ms h ough ace chaining ac oss
mul iple synapses.
Weigh dis ibu ion analysis e eals dis inc clus e ing: neu-
ons 0–4 (NORMAL) exhibi mean weigh 178 ±31, while
TABLE II
PERFORMANCE COMPARISON AGAINST STATE-OF-THE-ART METHODS
Me hod Accu acy (%) La ency (ms) Powe (mW) F1 Sco e Ene gy (mJ)
QESNN (This Wo k) 92.12 4.10 265.00 0.869 0.0014
Classical SNN [17] 72.00 4.80 485.00 0.685 0.0023
CNN Baseline 74.00 15.20 920.00 0.712 0.0140
LSTM Baseline 76.00 22.50 1150.00 0.735 0.0258
Imp o emen s SNN +27.9% -14.6% -45.4% +26.9% -38.1%
TABLE III
ABLATION STUDY RESULTS
Con igu a ion Accu acy (%) F1 Sco e
QESNN (Full) 92.12 0.869
w/o Tempo al T aces 74.35 0.702
w/o Weigh Bounds 68.21 0.641
Fixed Weigh s (no STDP) 62.88 0.589
neu ons 5–9 (ANOMALY) show 112 ±28. This 59% sep-
a a ion c ea es obus decision bounda ies, educing alse
nega i es by 41% e sus classical SNN.
B. Ha dwa e E iciency
E en -d i en p ocessing elimina es con inuous ac i a ion
calcula ions. Neu ons consume dynamic powe (265mW) only
du ing spike e en s (3.2 spikes/in e ence ×241 in e ences =
771 o al spikes). A 68% neu on u iliza ion, 32% idle ime
educes a e age powe below s a ic + dynamic sum.
The high h eshold (V h esh = 800) equi es empo al sum-
ma ion o ≈6–8 spikes, il e ing >90% o single-spike noise.
This educes swi ching powe Pdyn ∝ spike ×Cload ×V2
DD.
Slow leak (Vleak = 1) p ese es po en ial du ing 234-cycle
UART in e -spike in e als, enabling bu s de ec ion wi hou
p ema u e ese .
C. Limi a ions and Fu u e Wo k
Missed Anomalies: 19 alse nega i es (26.4% o anoma-
lies) co espond o: (1) sub- h eshold ib a ions (ampli ude
<0.3), (2) in e mi en ailu es (<4spikes/window), (3)
no el ailu e modes (ou side aining dis ibu ion). Adap i e
h eshold scheduling—dynamically adjus ing V h esh based on
exponen ial mo ing a e age o memb ane po en ial—could
educe alse nega i es by es ima ed 40%.
Scalabili y: Cu en 46% LUT u iliza ion limi s scaling
o ≈20 ou pu neu ons on Tang Nano 4K. Mul i-laye deep
SNNs equi e 4K–8K LUT FPGAs (Tang Nano 9K, cos :
4500 INR). Al e na i e: dis ibu ed p ocessing ac oss mul iple
FPGAs wi h spike-based in e -chip communica ion.
Weigh Pe sis ence: SRAM p og amming loses lea ned
weigh s on powe cycle. In eg a ion wi h on-boa d SPI lash
(W25Q128, 16MB, cos : 150 INR) enables non- ola ile s o -
age. Eme ging memo y de ices (ReRAM, PCM) o e in-si u
analog weigh s o age wi h 100×densi y imp o emen .
VII. CONCLUSION
QESNN demons a es p ac ical neu omo phic compu ing on
sub-3000 INR FPGA ha dwa e, achie ing 92.12% accu acy
wi h 265mW powe consump ion—compa able o special-
ized neu omo phic ASICs a 1/50 h he cos . The quan um-
enhanced STDP lea ning mechanism wi h empo al ace
egis e s enables 27.9% accu acy imp o emen o e classical
SNNs h ough mul i-spike co ela ion lea ning, alida ed on
MIMII indus ial senso da a.
Comp ehensi e benchma king ollowing SNAB-
Sui e/Neu oBench p o ocols con i ms eal- ime capabili y
(4.10ms la ency, 246 samples/s h oughpu ) wi h 100%
p ecision c i ical o p oduc ion deploymen . The e en -d i en
a chi ec u e achie es 0.0014 mJ/in e ence ene gy e iciency,
enabling 21+ hou s ba e y ope a ion.
Fu u e ex ensions include: (1) mul i-laye deep SNN a chi-
ec u es wi h con olu ional spike laye s, (2) adap i e h eshold
mechanisms o dynamic inpu s a is ics, (3) ASIC ape-ou
a ge ing 65nm CMOS o 50mW powe a 100MHz, (4)
neu omo phic a chi ec u e sea ch o au oma ed opology op-
imiza ion. This wo k alida es he democ a iza ion o neu o-
mo phic compu ing, posi ioning b ain-inspi ed AI accele a o s
as p ac ical edge compu ing in as uc u e.
ACKNOWLEDGMENT
The au ho s hank S.R.M Ins i u e o Science and Tech-
nology o p o iding FPGA ha dwa e esou ces and compu-
a ional in as uc u e & aluable guidance on neu omo phic
sys em design.
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