Citations refer to the original publication, not to a Scieee localized version.
Ríos Navarro, J. A., Tapiador Morales, R., Jiménez Fernández, Á. F., Domínguez Morales, M. J., Amaya Rodríguez, C. A., & Linares Barranco, A. (2018). Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator. IEEE Computer Society. https://doi.org/10.1109/NANO.2018.8626313
Ríos Navarro, José Antonio, et al. Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator. IEEE Computer Society, 2018. https://doi.org/10.1109/NANO.2018.8626313.
Ríos Navarro, José Antonio, Ricardo Tapiador Morales, Ángel Francisco Jiménez Fernández, Manuel Jesús Domínguez Morales, Claudio Antonio Amaya Rodríguez, and Alejandro Linares Barranco. Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator. IEEE Computer Society, 2018. https://doi.org/10.1109/NANO.2018.8626313.
Ríos Navarro, J. A. et al. (2018) Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator. IEEE Computer Society. Available at: https://doi.org/10.1109/NANO.2018.8626313.
J. A. Ríos Navarro, R. Tapiador Morales, Á. F. Jiménez Fernández, M. J. Domínguez Morales, C. A. Amaya Rodríguez, and A. Linares Barranco, “Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator,” IEEE Computer Society, 2018, doi: 10.1109/NANO.2018.8626313.
@misc{riosnavarro2018performance,
author = {Ríos Navarro, José Antonio and Tapiador Morales, Ricardo and Jiménez Fernández, Ángel Francisco and Domínguez Morales, Manuel Jesús and Amaya Rodríguez, Claudio Antonio and Linares Barranco, Alejandro},
title = {Performance evaluation over HW/SW co-design SoC memory transfers for a CNN accelerator},
year = {2018},
publisher = {IEEE Computer Society},
doi = {10.1109/NANO.2018.8626313},
url = {https://doi.org/10.1109/NANO.2018.8626313}
}
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