Citations refer to the original publication, not to a Scieee localized version.
Feitoza, R. S., Barragan, M. J., Ginés Arteaga, A. J., & Mir, S. (2020). On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter. Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/ETS48528.2020.9131588
Feitoza, Renato S., et al. On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter. Institute of Electrical and Electronics Engineers (IEEE), 2020. https://doi.org/10.1109/ETS48528.2020.9131588.
Feitoza, Renato S., Manuel J. Barragan, Antonio José Ginés Arteaga, and Salvador Mir. On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter. Institute of Electrical and Electronics Engineers (IEEE), 2020. https://doi.org/10.1109/ETS48528.2020.9131588.
Feitoza, R. S. et al. (2020) On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter. Institute of Electrical and Electronics Engineers (IEEE). Available at: https://doi.org/10.1109/ETS48528.2020.9131588.
R. S. Feitoza, M. J. Barragan, A. J. Ginés Arteaga, and S. Mir, “On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter,” Institute of Electrical and Electronics Engineers (IEEE), 2020, doi: 10.1109/ETS48528.2020.9131588.
@misc{feitoza2020onchip,
author = {Feitoza, Renato S. and Barragan, Manuel J. and Ginés Arteaga, Antonio José and Mir, Salvador},
title = {On-chip Reduced-code Static Linearity Test of Vcm-based Switching SAR ADCs Using an Incremental Analog-to-digital Converter},
year = {2020},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
doi = {10.1109/ETS48528.2020.9131588},
url = {https://doi.org/10.1109/ETS48528.2020.9131588}
}
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