Citations refer to the original publication, not to a Scieee localized version.
Avedillo de Juan, M. J., & Núñez Martínez, J. (2015). Improving speed of tunnel FETs logic circuits. Institute of Electrical and Electronics Engineers. https://doi.org/10.1049/el.2015.2416
Avedillo de Juan, María José, and Juan Núñez Martínez. Improving speed of tunnel FETs logic circuits. Institute of Electrical and Electronics Engineers, 2015. https://doi.org/10.1049/el.2015.2416.
Avedillo de Juan, María José, and Juan Núñez Martínez. Improving speed of tunnel FETs logic circuits. Institute of Electrical and Electronics Engineers, 2015. https://doi.org/10.1049/el.2015.2416.
Avedillo de Juan, M. J. and Núñez Martínez, J. (2015) Improving speed of tunnel FETs logic circuits. Institute of Electrical and Electronics Engineers. Available at: https://doi.org/10.1049/el.2015.2416.
M. J. Avedillo de Juan and J. Núñez Martínez, “Improving speed of tunnel FETs logic circuits,” Institute of Electrical and Electronics Engineers, 2015, doi: 10.1049/el.2015.2416.
@misc{avedillodejuan2015improving,
author = {Avedillo de Juan, María José and Núñez Martínez, Juan},
title = {Improving speed of tunnel FETs logic circuits},
year = {2015},
publisher = {Institute of Electrical and Electronics Engineers},
doi = {10.1049/el.2015.2416},
url = {https://doi.org/10.1049/el.2015.2416}
}
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