Citations refer to the original publication, not to a Scieee localized version.
Núñez Martínez, J., & Avedillo de Juan, M. J. (2017). Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/TNANO.2016.2629264
Núñez Martínez, Juan, and María José Avedillo de Juan. Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. Institute of Electrical and Electronics Engineers, 2017. https://doi.org/10.1109/TNANO.2016.2629264.
Núñez Martínez, Juan, and María José Avedillo de Juan. Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. Institute of Electrical and Electronics Engineers, 2017. https://doi.org/10.1109/TNANO.2016.2629264.
Núñez Martínez, J. and Avedillo de Juan, M. J. (2017) Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs. Institute of Electrical and Electronics Engineers. Available at: https://doi.org/10.1109/TNANO.2016.2629264.
J. Núñez Martínez and M. J. Avedillo de Juan, “Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs,” Institute of Electrical and Electronics Engineers, 2017, doi: 10.1109/TNANO.2016.2629264.
@misc{nunezmartinez2017comparison,
author = {Núñez Martínez, Juan and Avedillo de Juan, María José},
title = {Comparison of TFETs and CMOS using optimal design points for power-speed trade-offs},
year = {2017},
publisher = {Institute of Electrical and Electronics Engineers},
doi = {10.1109/TNANO.2016.2629264},
url = {https://doi.org/10.1109/TNANO.2016.2629264}
}
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