Low-Voltage 0.81mW, 1-32 CMOS VGA with 5% Bandwidth variations and 38dB DC rejection

Received May 7, 2020, accepted May 18, 2020, date of publication June 1, 2020, date of current version June 17, 2020. Digital Object Identifier 10.1109/ACCESS.2020.2999315 Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection HECTOR DANIEL RICO-ANILES 1, JAIME RAMIREZ-ANGULO 1,2, (Life Fellow, IEEE), JOSE MIGUEL ROCHA-PEREZ 2, ANTONIO J. LOPEZ-MARTIN 3, (Senior Member, IEEE), AND RAMON GONZALEZ CARVAJAL 4, (Fellow, IEEE) 1Klipsch School of Electrical and Computer Engineering, New Mexico State University, Las Cruces, NM 88003, USA 2National Institute of Astrophysics, Optics and Electronics, Puebla 72840, Mexico 3Smart Cities Institute, Public University of Navarre, 31006 Pamplona, Spain 4Electronics Department, University of Seville, 41092 Seville, Spain Corresponding author: Hector Daniel Rico-Aniles ([email protected]) This work was supported by AEI/FEDER under Grant TEC2016-80396-C2. The work of Hector Daniel Rico-Aniles was supported by the Mexican Consejo Nacional de Ciencia y Tecnologia (CONACYT) for the Academic Scholarship under Grant 408946. ABSTRACT A CMOS low-voltage amplifier with approximately constant bandwidth and DC rejection is introduced. The design is based on the cascade of a wide linear input range OTA, an op-amp and a servo-loop with extremely large time constants. It operates with ±0.45Vsupplies and a power consumption of 0.81mW in 180nm technology. The bandwidth changes only from 9.08MHz to 9.54MHz over a gain range from 1 to 32, it has a 9.8Hz low cutoff frequency and a DC attenuation of 38dBs. DC floating voltage sources are used to keep the gates of all differential pairs at a constant value close to a supply rail in order to operate the amplifier circuit with minimum supply voltage. The proposed circuit has small and large signal figures of merit FOMSS =5380 (MHz*pF/mW) and FOMLS =0.0085((V/ns)*pF/mA) for a nominal gain A =32. INDEX TERMS Low-voltage, low power, CMOS amplifiers, transresistance amplifier, linear transconductors. I. INTRODUCTION The amplifier is an essential block in analog circuits. In many applications variable gain amplifiers (VGAs) are required with DC rejection, low bandwidth variations over the gain adjustment range, reduced supply voltage and power dissipation, i. e. wireless systems [1] and biomedical systems [2]. The widely used conventional op-amp based inverting amplifier shown in Fig. 1has a gain given by G= −(R2/R1). The loop gain determines the bandwidth (BW) of the circuit according to the expression BW =GB/(1 +R2/R1); where GB is the gain-bandwidth product of the op-amp. The bandwidth (BW) decreases as the gain increases (G). A common amplifier approach that ideally has a constant bandwidth is achieved by replacing the op-amp with a current feedback operation amplifier (CFOAs) as explained in [3]. It requires CFOAs with extremely low input impedance |Zin| over the amplifier’s bandwidth in the low impedance input terminal of the CFOA. |Zin|  R1is very difficult to accomplish in practice. In [4] an AC-coupled ultra low-voltage The associate editor coordinating the review of this manuscript and approving it for publication was Yuh-Shyan Hwang. FIGURE 1. Conventional op-amp-based inverting amplifier. VGA with constant bandwidth based on the conventional op-amp approach was presented. This configuration has DC rejection. The bandwidth is maintained constant by having a fixed negative feedback factor β=1/GMAX independent of the selected gain G. The drawback of this approach is that it results in a constant but minimum bandwidth with value BW =BWMIN =GB/GMAX . Moreover, the AC coupling capacitors lead to frequency dependent loading of the signal 106310 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ VOLUME 8, 2020 H. D. Rico-Aniles et al.: Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection FIGURE 2. Low-voltage LOTA-TRA constant bandwidth amplifier. source since the impedance of coupling capacitors is reduced at high frequencies. Another alternative to achieve low bandwidth variations is the cascade combination of a linear OTA (LOTA) and an op-amp-based transresistance amplifier (TRA) as shown in Fig. 2. Using this configuration both building blocks (LOTA and TRA) as well as the combination of the two have an ideally constant and maximum bandwidth independent of the gain. We denote here this configuration as LOTA-TRA amplifier. It has been also called Cherry-Hooper amplifier [5]–[8]. The explanation of why the LOTA-TRA amplifier has low bandwidth variations over the gain adjustment range is reviewed in the following section. In many practical situations, like in biomedical or communication systems, the signals have a very small AC component superimposed on a large DC component. In these cases the high gain required to amplify the small AC signal can also lead to amplifier saturation given that the DC components and the op-amp’s offset are also amplified by the gain G. A common approach is to use AC coupled architectures to reject the DC component of the input signal, but they are difficult to implement on chip for the very low cutoff frequencies required in some applications. Servo-loops (SLs) are also used to provide the amplifier with DC attenuation [9]–[11]. The VGA with a SL circuit performs as a high-pass filter in the low frequency band attenuating all frequencies below its cutoff frequency, including the DC component of the signal and the DC offset of the op-amp. Commonly, an active SL is implemented using an integrator and the amplifier’s low cutoff frequency fLdepends on the unity gain frequency of the SL integrator f0=1/(2πRInt CInt ). Where CInt and RInt are the capacitor and resistor used in the integrator [12], [13]. In order to have a very-low cutoff frequency (in the Hertz range) very large CInt and/or RInt values are needed which are very difficult to integrate on chip. The other challenge that analog and mixed-signal circuits face is the low available supply voltage to operate ICs in modern CMOS technologies. This supply voltage has decreased as CMOS feature sizes have been scaled down; i. e. in 180nm technology the nominal supply voltage is Vsupply ≈VDD −VSS ≈1.8V while in 16nm technology is 0.7V. On the other hand, the threshold voltages (VTH ) have not decreased at the same rate. So, for the 180nm CMOS technology VTH ≈0.55V, while for 16nm VTH ≈0.4V. The headroom of the differential pair given by HRDP = VGS +VDSsat , where VGS ,VDSsat are the gate-source and drain-source saturation voltages respectively, severely constrains the input signal swing and leads to minimum supply requirements VsupplyMIN =2HRDP. The headroom of the differential pair assuming VDSsat ≈0.1V constraints the design to operate with a minimum supply VsupplyMIN ≈1.5V in 180nm technology. This without considering headroom that might be required by input signal swing. In modern deep sub-micrometer CMOS technologies the situation is more adverse, so for 16nm CMOS technology this corresponds to aHRDP ≈0.6V and a minimum supply VsupplyMIN ≈1.2V which is larger than the nominal supply of this technology. For this reason, conventional VGA architectures are not even functional in these technologies with transistors operating in strong inversion. Also, in higher feature size (older) CMOS technologies it is convenient to operate ICs with reduced supply voltage in order to decrease power dissipation. In this paper we propose a low-voltage implementation of a linear VGA using a LOTA-TRA amplifier with high attenuation for DC and offset and a low cutoff frequency (fL) in the order of Hertz. This scheme is characterized by a large differential input voltage swing and low bandwidth variations over the gain adjustment range from 1 to 32. It uses a servoloop to attenuate the input signal DC component as well as the op-amp offset. The proposed circuit can be operated with much lower bias currents in order to be used in biomedical applications where power dissipation is the main concern. This will reduce the bandwidth as discussed in the simulation results section. However, biomedical signals require very low bandwidths. Additionally, the proposed circuit has high input impedance, therefore it does not load the signal source, so that a low impedance (buffered) signal source is not necessary as it is the case for the inverting amplifier of Fig. 1. The paper is organized as follows: section II describes the proposed circuit. In section III simulated results in 180nm technology are discussed and conclusions are presented in section IV. II. CIRCUIT DESCRIPTION OF THE PROPOSED VGA WITH DC ATTENUATION A. CONSTANT BANDWIDTH OPERATION OF LOTA-TRA CIRCUIT The proposed implementation of the low-voltage LOTA-TRA amplifier is shown in Fig. 3. It uses a wide input range low voltage linear operational transconductor amplifier (LOTA) to transform the input differential voltage Vsinto complementary LOTA output currents with value IOTA =Gm1Vs. VOLUME 8, 2020 106311 H. D. Rico-Aniles et al.: Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection FIGURE 3. Proposed low-voltage LOTA-TRA amplifier with constant bandwidth and DC rejection. It is important to have a linear V-I conversion, thus the OTA transconductance Gm1should have a linear behavior over a wide input differential range. The LOTA implementation uses two low-voltage linear current control units (LCCUs) and it is described in the following subsection. The currents generated by the low-voltage LOTA are then converted into the output voltage by an op-amp based low-voltage transresistance amplifier through feedback resistors RFaccording to Vout = 2IOTARF. The voltage gain of the LOTA-TRA amplifier is then given by G=2Gm1RF. The transconductance of the low-voltage LOTA is determined by a resistor Rused in the low-voltage LCCU and the scaling factor Nof the transistors in the output branches of the OTA as Gm1=N/R. Therefore, the low-voltage LOTA-TRA amplifier’s voltage gain is given by G=2NRF/R. The TRA and LCCUs are described in detail in the following subsections. The bandwidth of the LOTA-TRA is maintained constant because both the LOTA and the TRA have a constant bandwidth independent of the values of RFand Rthat determine the VGA voltage gain. In the case of the LOTA the bandwidth is constant because the output terminals of the LOTA are connected to the low impedance input terminals of the TRA that can be seen ideally as an AC ground. Therefore, the bandwidth of the LOTA is determined only by the internal high frequency pole of the LOTA BWLOTA =fpOTA. This allows the LOTA to work with maximum and constant bandwidth. On the other hand the TRA has also a maximum and constant bandwidth independent of gain because from its point of view the LOTA performs as high impedance input current sources whose internal resistances correspond to the high output resistance of the LOTA RoutLOTA. Given that the TRA uses a Miller op-amp, the bandwidth of the TRA is given by BWTRA =GBop−amp/(1+RF/RoutLOTA), for RFRoutLOTA, BWTRA ≈GBop−amp independent of the value of RFthat determines the transresistance gain. Thus, the TRA has ideally maximum bandwidth for all values of RF. In practice for high gain values RFcan be comparable to RoutLOTA in which case it leads to some bandwidth reduction. This is typically avoided by connecting a capacitor CFin parallel with RF. This capacitor scales down as RFincreases. The bandwidth of the LOTA-TRA amplifier BWLOTA−TRA is determined by the bandwidths of the LOTA and TRA and is approximated by equation (1) [14]. Since, ideally these bandwidths are constant the low-voltage LOTA-TRA also exhibits a constant bandwidth. BW(LOTA−TRA)=1 q1 BW2 LOTA +1 BW2 TRA (1) B. IMPLEMENTATION OF LOW-VOLTAGE LINEAR OTA The low-voltage linear current control unit (LCCU) circuit shown in Fig. 4is used as a core block to implement 106312 VOLUME 8, 2020 H. D. Rico-Aniles et al.: Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection FIGURE 4. a) Low voltage linear current control unit, b) symbol. FIGURE 5. a) Differential amplifier (DA) with active load used in the V to I conversion unit, b) floating voltage source implementation. the low-voltage LOTA and the DC floating voltage sources shown in Fig. 5b. These voltage sources allow the low voltage operation of the TRA. The LCCU circuit uses a current mirror loaded differential amplifier (DA) with NMOS input transistors, whose transistor level schematic is shown in Fig. 5a and it operates as follows: A voltage, VDDP which is very close to VDD, (VDDP ≈ VDD −0.07V), is connected to the negative input terminal of the DA. Negative feedback causes the voltage VAat the positive terminal of the DA to have the same value VDDP at its negative input terminal. This provides a headroom for the DA with value HRDP =Vsupply −0.07Vwhich allows the circuit to operate with very low supply voltage VDDmin =HRDP = VGS +VDSsat +0.07V. The output voltages of the LCCU, VCtrlP and VCtrlN , are connected to the gates of PMOS and NMOS transistors MPBat and MNBat . These transistors generate matched sourcing and sinking currents, IR, that flow through R.IRsatisfies the conditions of eqs. (2) and (3), where IQ=VDDP/Rand iout =VS/R. The current IRcan be replicated using the voltages VCtrlP and VCtrlN in other branches and allows implementation of floating DC voltage sources with value VBat =VDDP −Vsas shown in Fig. 5b. IR=VDDP −Vs R=VDDP R−Vs R(2) IR=IQ−iout (3) Fig. 6shows the implementation of a low-voltage LOTA. In this scheme two linear current control units (LCCU) whose inputs are connected to complementary input signals Vs/2 and −Vs/2 are used. They generate four control output voltages VCtrlP1and VCtrlN1from Vs/2 and VCtrlP2and VCtrlN2 from −Vs/2 that drive the two output branches of the LOTA with transistor scaled by a factor Nthat generate offset-free complementary output currents ±iout with value iout =N· (Vs/R). In the first branch VCtrlP1induces a current IR1on the PMOS transistor while VCtrlN2drives the NMOS transistor producing a current IR2to flow on the same branch. The values of IR1and IR2are given by eq. (4) and (5) respectively. The difference of these two currents yields an output current iout =N·(Vs/R). Similarly, the second branch generates a complementary output current signal −iout . In this branch the VOLUME 8, 2020 106313 H. D. Rico-Aniles et al.: Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection FIGURE 6. Low voltage linear OTA with complementary outputs based on two LCCUs. LCCU1 output voltage VCtrlN1drives the NMOS transistor while the LCCU2 output voltage VCtrlP2drives the PMOS transistor. In practice the LOTA does not require complementary input signals Vs/2, −Vs/2. It also generates complementary output currents ±iout with unbalanced signals Vs1and Vs2that have non-zero common mode component and whose difference is given by Vs=Vs1−Vs2. The common mode component is cancelled when the currents IR1and IR2are subtracted at the output branch. IR1=NVDDP R−Vs 2R=NIQ−iout 2(4) IR2=NVDDP R+Vs 2R=NIQ+iout 2(5) C. LOW-VOLTAGE TRANSRESISTANCE AMPLIFIER The low voltage transresistance amplifier is implemented using the two-stage fully differential free class AB Miller opamp reported in [15] and shown in Fig. 7. Class AB operation is achieved using capacitors Cbat and large resistor values Rlarge. This way high speed changes are transferred from nodes Vo1pand Vo1nto nodes Xand X0through capacitors Cbat , forcing both output transistors to be active as amplifiers and perform as a push-pull class AB amplifier with a high symmetrical slew rate at the output. In this structure the maximum positive and negative output currents are not limited by the bias currents. To achieve low-voltage operation the input terminals ViP and ViN of the op-amp are DC level shifted close to a value VDDP. To do so, floating voltage sources with constant value VBat =VDDP are used as shown in Fig.3. They are implemented using a resistor RBat , and sinking and sourcing current sources with value IBat =VDDP/RBat as shown in Fig. 5b. The control voltages for IBat are generated using an additional LCCU with a resistance RBat and whose input terminal is connected to ground. FIGURE 7. Free class AB two stage Miller op-amp. FIGURE 8. Low-voltage common mode feedback network. A low-voltage common mode feedback network (LVCMFN) that sets the output common mode voltage of the op-amp to the midsupply voltage VCMRef =(VDD +VSS )/2 is shown in Fig. 8. Just as for the op-amp low voltage operation of the CMFN requires the gates of transistors MN and MN0to operate at a voltage close to the upper rail. This is achieved through a resistive voltage divider formed by RCM and RPullUp, where pull-up resistors RPullUp ≈0.6RCM are used. D. LOW-VOLTAGE SERVOLOOP WITH VERY LOW 3dB FREQUENCY A servo-loop (SL) is used to obtain a high-pass characteristic in the amplifier’s low frequency range that attenuates the DC component of the input signal by a large factor but that amplifies signals starting at very low frequencies. The block diagram of the circuit including the servo-loop that uses an integrator and a transconductor is shown in Fig. 9. This configuration yields to the system transfer function described by equation (6), where HTRA and HInt are the transfer functions of the TRA and the integrator respectively. The transfer function of the TRA is defined by equation (7), where ω3TRA is its 3dB frequency and the transresistance gain is defined by the feedback resistor RF. The transfer function of the integrator is given by (8). In practice the integrator as a low-pass response with DC gain AOLInt and a 3dB frequency ω3Int =ω0/AOLInt , where ω0is the unity gain frequency of the integrator given by ω0=1/RInt CInt . The frequency response of the proposed LOTA-TRA circuit with servoloop is depicted in solid line in Fig. 10 and defined by equation (9), where Gm1and Gm2are the 106314 VOLUME 8, 2020 H. D. Rico-Aniles et al.: Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection FIGURE 9. Block diagram of the servoloop. FIGURE 10. Frequency response of the proposed LOTA-TRA circuit with servoloop. transconductance gains of the input LOTA and the feedback transconductor respectively. It is assumed that ω3Int ωL ω3TRA, where ωLis the low cutoff frequency of the VGA. The response of the integrator is inverted due to the fact that it is used in the negative feedback path of the amplifier. The lowpass response of the integrator provides the amplifier with the high-pass characteristic at low frequencies. For DC (ω=0) the SL has a gain AOLInt Gm2leading to a high DC attenuation with value H∗(0) =Gm1/(Gm2AOLInt ) as expressed by equation (10). It has a zero and a pole in the low frequency range at ω3Int and ωLrespectively, where ωL=ω0Gm2RF (11). The amplifier has a unity gain in the low frequency band at (Gm2/Gm1)ω0as described by equation (12). At ω=ωL the SL begins to have a negligible effect over the response of the amplifier, the gain is given by equation (13). At ωωL, the servo-loop has very low gain and the transfer function of the VGA at these frequencies can be approximated by equation (14). It can be seen that ω3TRA is the 3dB frequency in the high frequency range. In order to achieve very low frequencies ωL(in the hertz range) the servoloop requires the unity gain frequency of the integrator ω0to be much smaller than ωL,ω0ωL. Very low values for ω0(in the sub-hertz range) can be obtained on chip by implementing RInt with quasi-floating gate transistors [16], [17] that have equivalent resistance values RInt on the order of hundreds of Gs which in combination with typical integrated capacitor CInt in the order of pF leads to the required time constants in the order of seconds. If constant values for ωLindependent of the gain are required CInt can be implemented as a digitally programmable capacitor array that scales CInt with RFSo that the ratio RF/CInt that determines ωLremains constant with changes in RF. H(jω)=Vout Vin =Gm1HTRA 1+Gm2HInt HTRA (6) HTRA(jω)=−RF 1+jω ω3TRA (7) HInt (jω)=AOLInt 1+jω ω3Int (8) H(jω)=Gm1 Gm2AOLInt ·1+jω ω3Int  1+jω ωL1+jω ω3TRA (9) where |H(0)| = Gm1 Gm2·1 AOLInt (10) |H(ω3Int )| = Gm1 Gm2·√2 AOLInt (11)     HGm2 Gm1ω0   =1 (12) |H(ωL)| = Gm1RF √2(13) H(jω)≈Gm1HTRA ≈Gm1RF 1+jω ω3TRA (14) The transistor level schematic of the low voltage integrator is shown in Fig. 11. It uses resistors RLCMF =100kas a local common mode feedback (LCMF) [18] and has a DC gain AInt =gm1(RLCMF ||ro1||ro3). Similar to the op-amp in the TRA, low voltage operation is achieved by inserting floating DC batteries with values VDDP in series with transistors M1 and M1’. This DC shifts their gates close to the upper rail. The schematic of the SL transconductor is shown in Fig. 12. It consist of a differential amplifier with active loads and a transconductance gain Gm2. In order for this circuit to operate with low supply voltage it is required that the DC operating of nodes A, B at its inputs are close to VDD. This is achieved by inserting a diode connected transistor MShift with very small bias current in the integrator. This transistor acts as a floating battery with approximate value of VTthat DC shifts the output nodes (A) and (B) of the integrator to a value close to VDD. The outputs of the integrator are connected to the inputs of the SL OTA shown in Fig 12. The SL transconductor transform the output voltage of the integrator into complementary currents ISL that are subtracted at nodes X and X’ from the currents IOTA generated by the LOTA circuit. III. SIMULATION RESULTS The proposed LOTA-TRA amplifier circuit of Fig. 3was designed and simulated using Cadence Framework II with a commercial 180nm technology CMOS n-well process design kit provided by MOSIS. This process has nominal supply voltage VDDNominal =1.8V as well as PMOS and NMOS VOLUME 8, 2020 106315 H. D. Rico-Aniles et al.: Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection FIGURE 11. Transistor level schematic of low-voltage SL integrator with resistive local common mode feedback and output DC level shift. FIGURE 12. Transistor level schematic of SL OTA. threshold voltages VTHn ≈ |VTHp| ≈ 0.55V. The designed circuit is capable to work with supply voltages as low as ±0.45Vwith a total power consumption of 0.81mW and wide linear input range. The bandwidth is maintained within small variations of less than 10% across gains 1 to 32 with a DC attenuation of −38dB and constant fL=9.8Hz. The LOTA was designed using two LCCU circuits as shown in Fig. 6and utilizes bias currents IbiasLCCU = 12.5µA. The output transistors were sized with N=4. The floating voltage sources VBat in the TRA and the integrator required an additional LCCU with its input connected to ground. All LCCUs use a resistor with value RBat =23.2k. The fully differential op-amp of Figs. 7and 8was used in the TRA with bias currents IBias =50µA. The resistances used in the CMFN of Fig. 8have a value of RCM =800k. With the bias currents used, PMOS and NMOS transistors have gatesource voltages |VGS | ≈ 490mV and VDSsat ≈70mV . The characterization parameters of the implemented low-voltage op-amp and LOTA circuits are summarized in Table 1and Table 2respectively. The integrator used in the SL has a 3dB frequency of f3Int =11.29mHz, a unity gain frequency f0=5.8Hz and a DC gain AOLInt =54.2dB. FIGURE 13. Transient simulation of proposed LOTA-TRA with SL for gains 1-32, with a triangular input that has a 50mV DC component. FIGURE 14. Transient simulation of proposed LOTA-TRA without SL for gains 1-32, with a triangular input that has a 50mV DC component. FIGURE 15. Transient analysis with 900mVpp 2MHz triangular input. Figs. 13 and 14 show the simulated transient output voltage of the proposed low-voltage LOTA-TRA amplifier with and 106316 VOLUME 8, 2020 H. D. Rico-Aniles et al.: Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection FIGURE 16. THD versus Vin simulations for different gains: a) G =1, b) G =2, c) G =4 and d) G =8. TABLE 1. Low-voltage op-amp characteristics. TABLE 2. Low-voltage LOTA characteristics. without servo-loop, respectively. The amplifier was configured for gains (G≈1,2,4,8,16,32) with a 20mVpp, 2MHz triangular input signal that had superimposed a 50mV DC voltage. The gain is controlled by the value of RF. It can be seen that the proposed circuit using the servo-loop is capable of attenuating the offset. In the version that does not have a servo-loop the offset is also amplified leading to output DC shift and saturation for high gains. The circuit exhibits a linear behavior that is preserved for small and large input signal amplitudes as well. This is depicted in Fig. 15 where the circuit has a unity gain and a ±450mV , 2MHz triangular signal is applied at the input, linearity is maintained approximately over a range of ±425mV . The architecture has a THD =0.047% and SNR = 66dBs with a 200mVpp, 2MHz sinusoidal input signal that had TABLE 3. Values of resistor RFand capacitor CFused in the transresitance amplifier. a DC component of 10mV and a gain G=2. Fig. 16 depicts the THD as function of the amplitude of the input signal for four different gains: a) G=1, b) G=2, c) G=4 and d) G=8. The AC response of the proposed LOTA-TRA with SL circuit is shown in Fig. 17. The gain is varied by changing the value of RFfrom 2.9kto 92.8k. The capacitance CFis changed along with RFfrom 0.1pF to 7pF in order to maintain the pole at ω3TRA constant. Table 3shows the values used for RFand CFfor the different VGA gains. The circuit exhibits a 38dB attenuation at DC. The high cutoff frequency fTRA has small variations ranging from 9.08MHz to 9.54MHz while the low cutoff frequency varies from 0.6Hz to 9Hz. These variations in the low cutoff frequency can be significantly reduced by varying the integrator capacitance Cint along with the adjustment of gain. As shown in Fig. 18 variations in the low cutoff frequency are maintained within a range of 8.97Hz to 9.86Hz. Fig. 19 shows the AC response of the conventional inverting amplifier, it can be seen that this scheme suffers from large bandwidth variations that range from 42.79MHz to 1.95MHz within the gain range of 1 to 32. VOLUME 8, 2020 106317 H. D. Rico-Aniles et al.: Low-Voltage 0.81mW, 1-32 CMOS VGA With 5% Bandwidth Variations and −38dB DC Rejection TABLE 4. Comparison with other related works. FIGURE 17. Frequency response of LOTA-TRA amplifier with SL. The total quiescent power dissipation is 0.81mW for the LOTA-TRA and 630µW for the conventional fullydifferential inverting amplifier. The performance of the proposed circuit and the conventional amplifier can be compared using the small signal and large signal figures of merit given by FOMSS =(GBW ·CL)/PDiss and FOMLS =(SR · CL)/IQtotal respectively, where IQtotal is the total quiescent current. Having both the same load capacitance CL=15pF, the LOTA-TRA prevails upon the conventional as the gain increases. At the maximum gain the LOTA-TRA exhibits a FOMSS =5380(MHz ∗pF/mW ) while the conventional inverting amplifier has a FOMSS =1000(MHz ∗pF/mW ). The conventional inverting amplifier and the proposed VGA FIGURE 18. Frequency response of LOTA-TRA amplifier with SL and constant 5Hz low cutoff frequency. use the same output stage and they exhibit the same slew rate performance SR =0.505V/us. This SR leads to a large signal figure of merit FOMLS =0.0085(V/ns)·pF/(mA) in the proposed architecture. On the other hand, the conventional inverting amplifier has a slightly higher large signal figure of merit FOMLS =0.0121(V/ns)·pF/(mA) but at the expense of loading the signal source and not cancelling the offset and/or input common mode signals. Despite wide gain variation, the bandwidth of the proposed scheme has moderate changes compared to the large bandwidth changes in the conventional amplifier. In Table 4a comparison with other works is summarized. It must be pointed out that the 106318 VOLUME 8, 2020