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Automatic synthesis of analog fuzzy controllers

Abstract

In this paper, a silicon compiler for analog fuzzy controllers is presented. The layout is automatically generated automatically, startingfrom a set of user specificationssuch as numberof rules, number of inputs and maximum current (power consumption). This tool relies on a library of parametrizable basic cells designed in a CMOS 0.7 m technology.The structure of the defuzzificationpart of the controller is based on the modular definiton made in [1]. This structure allows multi–input, multi–output fuzzy logic based controllers. It also a allows an easy extension of the controller (Serial or parallel conection of them to obtain controllers with more inputs or rules).

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Automatic synthesis of analog fuzzy controllers

Author: González Carvajal, Ramón; Torralba Silgado, Antonio Jesús; Colodro Ruiz, Francisco; García Franquelo, Leopoldo
Year: 1997
Source: https://idus.us.es/bitstreams/f25b59f6-f53a-4713-ae02-c91a14bee946/download
Au oma ic Syn hesis o Analog Fuzzy Con olle s
R. G. Ca ajal, A. To alba, F. Colod o and L. G. F anquelo
Dp o. de Ingenie ´ıaElec ´
onica
EscuelaSupe io de Ingenie os,
A da. ReinaMe cedes s/n, Se illa–41012(SPAIN)
e–mail: [email p o ec ed]
Abs ac —In hispape ,asiliconcompile o analog uzzycon olle s
is p esen ed. The layou is au oma ically gene a ed au oma ically,
s a ing omase o use speci ica ionssuchasnumbe o ules,num-
be o inpu s and maximum cu en (powe consump ion). This ool
elies on a lib a y o pa ame izablebasic cells designedin a CMOS
0.7
m
echnology.Thes uc u eo hede uzzi ica ionpa o hecon-
olle is based on he modula de ini on made in [1]. This s uc u e
allows mul i–inpu , mul i–ou pu uzzy logic based con olle s. I
also a allows an easy ex ension o he con olle (Se ial o pa allel
conec iono hem o ob aincon olle s wi hmo e inpu so ules).
I. INTRODUCTION
In he las ew yea s, uzzycon olle s ha e ound
a la ge numbe o applica ions in ields such as
au omo i e indus y, obo ics, powe d i es and
home appliances [2]. The e o e, i is no longe
s ange o ind uzzy sys emsembedded in indus-
ial ASICs. Hence, he a chi ec u e o hese con-
olle s is so equen ly epea ed, ha au oma ion
is possible. Au oma ion signi ica i ely sho ens
he design ime, educing he design cos . Di e -
en oolsha e ecen ly been p oposed oau oma e
he ha dwa e design o uzzy con olle s using a
digi al app oach [3], [4], [5] o an analog app oach
[6]. Analog ci cui s a e known o be inhe en ly
as e han digi al ci cui s wi h signi ican ly less
powe consump ionand silicon a ea. On heo he
hand, digi al ci cui s a e supe io in accu acy, ex-
endabili y and ease o design. Bu in he bo h
cases he design e o is high, so he de elopme
o ools o au oma e he design cycle is e y con-
enien .
In his pape a silicon compile o he au oma ic
syn hesis o analog uzzy con olle s is desc ibed.
I is based on he modula s uc u e p oposed in
[1]. This s uc u e allows o spli in o modules,
ha uses a cu en mode app oach. These mod-
ules o m a lib a y o pa ame izable basic cells
which a e ins an ia ed o build he con olle ha
mee s a se o use eque imen s. Once he ne lis
isgene a ed, he inallayou can beob ainedusing
Cadence So wa e.
This pape is o ganized as ollows. Sec ion II de-
sc ibes hedesign low. Thea chi ec u eo hecon-
olle is de ailed in Sec ion III. Sec ion IV p esen s
some esul s and ad ances u u e esea ch.
II. DESIGN FLOW
S uc u al
o analog
desc ip ion
ci cui
Es ima ed
Selec ion
A chi ec u e
Reque imen s
Use
NO
Pe o mances Accep ? YES
LAYOUT
Accep ?
YES
NO
(Ex e nal o he Compile )
Figu e 1: Design Flow
The design lowisdepic ed in igu e 1. In a ypical
design, use speci ica ions a e ela ed o numbe
o inpu s, numbe o ou pu s, numbe o ules,
maximum bias cu en (powe consum ion) and
desi ed h oughpu .
The silicon compile akes ad an age o he ac
ha ha dwa e uzzy con olle s a e, in p ac ice,
composed o a se o basic building blocks, such
as membe ship gene a o s, max–min blocks and
de uzzi ie s.
III. ARCHITECTURE OF THE FUZZY COTROLLER
The loo -plan o he uzzy con olle is shown in
igu e 2. As men ioned be o e i uses he mod-
ula s uc u e p oposed in [1]. This s uc u e is
based on he uzzy single on algo i hm wi h he
Mandani– ype in e ence p ocess and he cen e o
g a i y de uzzi ie me hod.
As can be seen in he igu e, hiss uc u e allowsa
a iable numbe o inpu s, ou pu s and ules. The
au oma ic syn hesize conec s hese basic modules
(lib a y cells) o o m he comple e con olle . The
ollowing building blocks can be iden i ied in he
uzzy con olle [7]–[8]:
1. The (MBF) Membe ship Func ion Gene a o .
I uses he ci cui p oposed in [9] which is
based on a linea unable OTA p oposed in
[10]. I p oduces a ully p og ammableMBF’s
1
Iw
Iy
Ic
Is
IY
IsIwi
=
Σ
ι
Ici Iwi
Iyi Is
=*
IsIwi
=
Σ
ι
Ici Iwi
*
=
Σ
ι
Iy
I
Ic1
s
MBF MBF
MIN
MIN
MBFMBF
XX
1nIw1 Iy1
CM
CM1
PROG
PROG
One ou pu De uzzi ie
Xi(inpu s)
(ou pu )
Figu e 2: A chi ec u e o he FuzzyCon olle
wi h a T iangula /T apezoidal shape, as can
be seen in igu e 3. As he ci cui os based in
a linea ansconduc o , i pe o ms he ian-
gula and apezoidal shapes be e han he
commonlyusedOTAbasedon hedi e en ial
pai .
2. The In e ence Machine (IM). The IM blocks
pe o ms heMamdani– ypeo in e ence p o-
cess( igu e4)using heANDope a o s,which
a e implemen ed wi h a MIN ci cui . Figu e
µR
w1
Rule 1
Rule 2
MIN
z
z
0
x21
0
x
w2
In e ed
Fuzzy Se
Figu e 4: Mamdani– ype in e ence p ocess, using single on as membe -
ship unc ions o he ou pu a iable
I
MBF2
I
MBFK
I
MBFmax
I
MBF1
V
Vdd
bias
Figu e 5: Max Ci cui y
5 shows he MAX ci cui , which is based on
he Winne –Take–All ci cui p oposed in [11]
and la e imp o ed in ([12]); he only modi-
ica ion included he e is a cascode ou pu o
imp o e he esponse o he ou pu cu en
mi o s. This ci cui also buil s he MIN op-
e a o , using he De Mo gan’s Law and he
complemen ope a o [13]. (Figu e 6)
I
MBF1
I
amp
I
MBF1
I
amp
MBFmin
I
Vbias
I
MBF1
I
MBF
MAX
CIRCUIT
I
MBFmax
Figu e 6: Min Ci cui y
3. The De uzzi ie Block (DF). The de uzzi ie
block implemen es he cen e o he g a i y
me hod wi h single ons as he ule conse-
quen s. Equa ion (1) esumes he compu a-
ions o be pe o med.
ou pu
=
P
i
=
i
=
1
w
i
c
i
P
i
=
i
=
1
w
i
(
1
)
whe e
is he numbe o ules,
w
i
is he in-
e ed ou pu o ule
i
, and
c
i
is he single on
o he consequen o ule
i
. These compu a-
ionscanbepe o medbe e incu en -mode
(inaci cui node heou pu cu en is hesum
o heinpu cu en s), using hecu en mul i-
plie /di ide p oposedin[14]anddepic edin
igu e 7. I makes he De uzzi ie Block as e
and simple.
IV. RESULTS AND FUTURE RESEARCH
HSPICE simula ions using a s anda d 0.7
m
CMOS echnology we e pe o med. In igu e 10, 9
and 8 can be seen he unabili y o he posi ions ,
2
I
MBF
Vpos1
Vpos2
I
MBF
Vslop2
Vslop1
Vpos2
Vpos1
IN
V
I
amp
I
amp
Vslop1
Vslop2
I
amp
I
MBF1
I
VIN
I1
V
slop2
I2
Vpos2
I= 1
-I
2
MIN
Ci cui
MBF2
IMBF2
Figu e 3: Membe ship Func ion Gene a o
b
I
x
I
y
I
x
I
x
I
y
I
=*
2*I
b
ou
I
Vdd
Figu e 7: Cu en mode Mul iplie /Di ide
slope and shapes o he membe ship unc ions. In
igu e 11 can be seen he ansien ansien o he
MIN ci cui . Finally in igu e 13 is showed he DC
pe o manceo hecu en mul iplie andin igu e
?? is showed he ansien esponse o his mul i-
plie . P esen ly a lib a y o cells is being designed
using Cadenca So wa e.
V. ACKNOWLEDGMENTS
The au ho s would like o acknowledge inancial
suppo byCICYT h ough heTIC86-0860p ojec .
Figu e 8: Tunabili y o he posi ion o he MBF
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