Tool s o Au oma ed Design o ΣΔ Modula o s 1
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
Tools Fo Au oma ed Design o ΣΔ Modula o s
F. Medei o, J.M. de la Rosa, B. Pé ez-Ve dú and A. Rod íguez-Vázquez
Cen o Nacional de Mic oelec ónica-Uni e sidad de Se illa
Edi icio CICA, C/Ta ia sn, 41012-Se illa, SPAIN
Phone #34 5 4239923, FAX #34 5 4231832
email: [email protected]
Abs ac
We p esen a se o CAD ools o design ΣΔ modula o s. They use s a is ical op imiza ion o
calcula e op imum speci ica ions o he building blocks used in he modula o s, and op imum sizes
o he componen s in hese blocks. Op imiza ion p ocedu es a he modula o le el a e equa ion-
based, while p ocedu es a he cell le el a e simula ion-based. The oolse inco po a es also an
ad anced ΣΔ beha io al simula o o moni o ing and design space explo a ion. We include mea-
su emen s aken om wo silicon p o o ypes: 1) a 17bi @40kHz ou pu a e ou h-o de low-pass
modula o ; and 2) a [email p o ec ed] cen al eq@10kHz bandwid h band-pass modula o . The i s
uses SC ully-di e en ial ci cui s in a 1.2μm CMOS double-me al double-poly echnology. The sec-
ond uses SI ully-di e en ial ci cui s in a 0.8μm CMOS double-me al single-poly echnology.
Foono e
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Tool s o Au oma ed Design o ΣΔ Modula o s 2
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
Tools Fo Au oma ed Design o ΣΔ Modula o s
I. INTRODUCTION
The pe o mance o a ΣΔ con e e IC is ul ima ely limi ed by i s analog ci cui y: he ΣΔ mod-
ula o on -end. Thus, e o s o enhance he pe o mance o widen he applica ion ange o hese
con e e s concen a e mos ly on he modula o and ollow wo pa allel and la gely co ela ed di ec-
ions: explo a ion o high-o de a chi ec u es and/o mul ibi quan ize s and, pushing he speci ica-
ions o analog cells used in he modula o s a hei pe o mance edges [1][2][3]. The con on a ion
o hese issues poses signi ican di icul ies o IC designe s. Some o he p oblems encoun e ed a e
gene al o analog IC design: la ge numbe o speci ica ions, complica ed ela ionships be ween spec-
i ica ions and design pa ame e s, in ol ed analysis, c i ical speci ica ions signi ican ly sensi i e o
misma ch, e c. O he s a e speci ic o ΣΔ modula o s; in pa icula , i s accu a e simula ion is cos ly
due o i s highly non-linea dynamics and he necessi y o use long ime-se ies o da a o e alua ion
pu poses [5][6][7]. These di icul ies ende he design o ΣΔ modula o ICs a ime- and esou ce-
consuming p ocess, and ha e p omp ed he de elopmen o ools which can help o inc ease designe
p oduc i i y and, hus, educe ime- o-ma ke and p oduc ion cos o o hcoming gene a ions o ΣΔ-
based mixed-signal ASICs.
This chap e p esen s a se o CAD ools o compu e -aided design o CMOS swi ched-capac-
i o (SC) and swi ched-cu en (SI) ΣΔ modula o s o low-pass and band-pass applica ions. These
ools use op imiza ion a he modula o and cell le els, ad anced beha io al simula ion a he mod-
ula o le el, and include he capabili y o as design space explo a ion o modula o a chi ec u es.
The ools a e e ically in eg a ed o suppo op-down design o ΣΔ modula o s, om he high-le el
speci ica ions o he sizes o he cells. Thei use is demons a ed in he pape h ough wo ully-di -
e en ial silicon p o o ypes in CMOS echnologies: a ou h-o de wo-s age SC ΣΔ modula o and
a ou h-o de band-pass SI ΣΔ modula o .
II. TOOL DIAGRAM
Fig. 1 shows he design low o ΣΔ modula o s. I comp ises op-down syn hesis asks:
1. Topology selec ion, i.e., o iden i y he bes sui ed modula o a chi ec u e o he equi ed
high-le el con e e speci ica ions (signal baseband, esolu ion, e c.);
2. Modula o sizing, i.e., o map hese high-le el speci ica ions in o speci ica ions o he basic
building blocks (such as gain-bandwid h p oduc o he opamp, slew- a e, compa a o hys e -
esis, e c.);
3. Analog cell selec ion, i.e., o choose he cell schema ics acco ding o he speci ica ions;
4. Cell sizing, i.e., o map he cell speci ica ions in o alues o hei componen s;
5. Layou .
Tool s o Au oma ed Design o ΣΔ Modula o s 3
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
These op-down asks a e complemen ed wi h bo om-up analyses:
6. Modula o simula ion a he a chi ec u al le el, o e i y co ec ness o he esul s o high-
le el syn hesis. Due o he la ge ci cui complexi y, and he need o long ime se ies a he
modula o ou pu , his analysis is mo e con enien ly handled h ough dedica ed beha io al
simula ion.
7. Cell simula ion, o e i y syn hesis a he elec ical le el using SPICE-like simula o s [4].
8. Ex ac ed layou simula ion a elec ical le el -- e y cos ly in CPU ime and memo y
esou ces. Thus, i is ypically used jus o check connec i i y and e alua e block pe o -
mance deg ada ion due o layou pa asi ics (no shown in Fig. 1).
The selec ion asks (ei he modula o s o cells) in ol e knowledge issues. The p oposed
ools include p ocedu es o help designe s in gaining insigh abou he ope a ion o di e en
modula o a chi ec u es, and hence guiding hei selec ion. On he o he hand, he sizing
asks in ol e p incipally op imiza ion issues -- ealized in ou design amewo k h ough he use o
s a is ical op imiza ion echniques. Fig. 2 is a low diag am o he op-down e ical in eg a ion
o he se o ools desc ibed in his chap e [8].
III. DESIGN EQUATION DATABASE
These ep esen he beha io o ypical modula o a chi ec u es ealized wi h swi ched-capac-
i o (SC) and swi ched-cu en (SI) building blocks. The da abase has been concei ed o be easily
Modula o
Speci ica ions
Block speci ica ions
Opamps Quan ize s Swi ches
Simula ion ok?
LAYOUT
Topology selec ion
Cell selec ion
Simula ion ok?
Fig. 1.Modula o design ope a ion low
Y
I2
XE
g2
-g2'
g1
-g1'
D/A
I1
− +o+o−
b1
b2
b3
b4
Tool s o Au oma ed Design o ΣΔ Modula o s 4
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
ex endible and includes single-loop as well as cascaded a chi ec u es, low-pass and band-pass, sin-
gle-bi and mul i-bi . Equa ions desc ibing hese a chi ec u es a e classi ied in h ee ca ego ies:
•A chi ec u e- ela ed. These ep esen he quan iza ion noise as a unc ion o he non-ide-
ali ies ha a ec i s shaping. Thei analy ical exp essions may be la gely di e en o he
di e en modula o a chi ec u es [8].
•Ci cui - ela ed. These ep esen noise sou ces o he han quan iza ion: he mal noise,
incomple e se ling, ha monic dis o ion, e c [8].
•Fundamen al limi s. They co e ade-o s be ween powe consump ion, esolu ion,
speed, e c., o he di e en opologies. They a e used o guide modula o selec ion
[1][11][13][15].
Table I summa izes he noise and dis o ion con ibu ions co e ed in he wo i s ca ego ies
abo e, oge he wi h he esponsible building block. As an example, Table II shows he app oxima e
exp essions o he powe o noise and ha monic dis o ion o a cascaded SC 2-2 a chi ec u e (see
Fig. 10(a) [11][16]) .
IV. SIZING
Speci ica ions con empla ed o sizing include cons ain s on he pe o mance pa ame e s and
design objec i es. Thei meaning is cla i ied conside ing o ins ance an opamp wi h he ollowing
Beha io al
models
Modula o Specs.
Equa ions
Fas a chi ec u e
explo a ion
High-le el
syn hesis
Cell
sizing
Elec ical
simula o
Op imize
LAYOUT
Beha io al
simula ion
Fig. 2.Tool block diag am
Tool s o Au oma ed Design o ΣΔ Modula o s 5
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
speci ica ions: DC-gain > 70dB; gain-bandwid h p oduc > 5MHz; phase ma gin > 60 deg ee; inpu
equi alen noise < 3μV; wi h minimum powe consump ion and silicon a ea occupa ion. We call
cons ain s o he ou i s speci ica ions ha include > o < symbols, and design objec i es o he
las wo, whose goal is o maximize o minimize some magni ude.
Sizing i sel is pe o med h ough a sequence o mo emen s in he design space un il a cos
unc ion eaches a minimum. The main ela ed issues a e cos unc ion o mula ion, and he gene a-
TABLE I
NON-IDEALITIES CONSIDERED IN THE TOOL
Building Blocks Non-ideali ies Consequences
Opamps
DC-gain, ini e and
non-linea
Inc eased quan iza ion
noise, ha monic dis o ion.
SR, limi ed Se ling noise, ha monic
dis o ion.
GB, limi ed Incomple e se ling noise.
O.S. limi ed O e loading.
The mal Noise Whi e noise.
Swi ches ON- esis ance, eed-
h ough
Se ling noise, whi e noise,
ha monic dis o ion.
Capaci o s Non-linea ,
misma ching
Inc eased quan iza ion
noise, ha monic dis o ion.
Clock Ji e Ji e Noise.
Compa a o s Hys e esis,
esolu ion ime
Inc eased quan iza ion
noise.
Quan ize s Non-linea i y Ha monic dis o ion.
TABLE II
APPROXIMATE ERROR POWER FOR A CASCADED ARCHITECTURE 2-2
Quan iza ion noise
Incomple e se ling noise
The mal noise
Non-linea capaci o dis o ion
Non-linea opamp dc-gain dis o ion
Ji e noise
Δ2
12
------4π2
3M3
---------- μ2δA
2π4
5M5
------------ d1
2π8
9M9
----------++
⎩⎭
⎨⎬
⎧⎫
Δ2
9M
--------1 Cp
C1
------+
⎝⎠
⎛⎞
2ς2gm
Ceq
---------TS
–
⎝⎠
⎛⎞
exp
1C12
C11
--------+
⎝⎠
⎛⎞
kT
4MC11
----------------- 1 C12
2
C11
2
---------+
⎝⎠
⎜⎟
⎛⎞
kT
6MCi
--------------kTgmRon
2MCi
----------------------+
⎝⎠
⎛⎞
+
α2
8
------Δ
2
---
⎝⎠
⎛⎞
4β2
32
------Δ
2
---
⎝⎠
⎛⎞
6
+
α121k1
+()
2
4A0
2
----------------------------------k2
4
k1
6
----- Δ
2
---
⎝⎠
⎛⎞
4α221k1
+()
2
8A0
2
----------------------------------k2
6
k1
8
----- Δ
2
---
⎝⎠
⎛⎞
6
+
Δ
2
---
⎝⎠
⎛⎞
22π bσ
()
2
2M
------------------------

Tool s o Au oma ed Design o ΣΔ Modula o s 6
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
ion o mo emen s and he managemen o he op imiza ion p ocedu e.
A. COST FUNCTION FORMULATION
The sizing o modula o s and cells a e o mula ed as cons ained op imiza ion p oblems,
(1)
whe e is he ec o o design pa ame e s, which de ines a L-dimensional
pa ame e space. F om (1) an equi alen uncons ained p oblem is de ined using di e en s a egies
o modula o s and cells.
5. Cos unc ion o modula o sizing
Calcula ed block speci ica ions mus ul ill he modula o speci ica ions and, a he same ime,
be he bes sui ed o implemen a ion. Fo ins ance, he DC-gain and GBW o he opamps should be
he lowes among he se o alues which yield easible modula o s.
The modula o speci ica ions a e mapped on o a single cons ain :
(2)
whe e is he o al in-band ou pu noise powe a he modula o ou pu , and is he
maximum powe ha gua an ees he modula o speci ica ions: esolu ion, bandwid h and maximum
inpu le el. The cos unc ion is gi en by:
(3)
whe e ep esen s he alue o he j- h block speci ica ion. The sign o he weigh pa ame e s ,
indica es i he objec i e mus be maximized o minimized. On he o he hand, he no maliza ion ac-
o s,
(4)
a e used o cope wi h la ge a ia ions o he absolu e alues o di e en block speci ica ions.
Loga i hms in (3) ende s he cos unc ion smoo he and hus, enable he ajec o y o escape
om local minima. The example o Fig. 3 illus a es he bene i s o using loga i hms. I co esponds
o,
minimize Φx()[]subjec o
φ x() 01 R≤≤;≤
xx1x2…xL
,,,()
T
=
PNx() PNmax,0≤–
PNx() PNmax,
Ψx()
Kj
xj
xjno m,
----------------
⎝⎠
⎛⎞
log
j1=
N
∑
–i xA∈
PNx()
PNmax,
-----------------
⎝⎠
⎛⎞
log i xA∉
⎩
⎪
⎪
⎪
⎨
⎪
⎪
⎪
⎧
=
xjKj
xjno m,
xjmin,i Kj0>
xjmax,i Kj0<
⎩
⎪
⎨
⎪
⎧
=
Tool s o Au oma ed Design o ΣΔ Modula o s 7
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
(5)
whe e a e cons an s. Fig. 3(a) depic s (5), which has he absolu e minimum in
, and many local minima in i s neighbo hood. The alues o he unc ion a
hese minima a e comp essed in o he in e al [0.4, 0.5]. On he o he hand, Fig. 3(b) depic s he
esul o aking he loga i hm o (5), whe e he minima a e mo e clea ly sepa a ed. Func ions like his
a e commonly ound in modula o and cell sizing [8].
A. Cos unc ion o cell sizing
Cons ain s ela ed o cell sizing a e classi ied in wo g oups:
•S ong es ic ions: These a e speci ica ions whose ul illmen is conside ed essen ial by
he designe ; o ins ance, he phase ma gin o an opamp mus be la ge han 0 o s abili y.
No elaxa ion o he speci ied alue is allowed.
•Weak es ic ions: These a e he ypical pe o mance speci ica ions equi ed o analog
building blocks, i.e. opamp DC-gain > 80dB. Unlike s ong es ic ions, weak es ic ions
allow some elaxa ion o hei a ge s, making ci cui s which do no exac ly mee he a -
ge s accep able.
The cos s unc ion o cell sizing mus e lec bo h ypes o cons ain s:
(6)
x() Kmin e–
ξxkd–()
2
k1=
N
∑
–
xkd–()cos
k1=
N
∏e
ξ–xkd–()
2
k1=
N
∑
–,xkd+()γ+cos
k1=
N
∏
⎩⎭
⎪⎪
⎪⎪
⎨⎬
⎪⎪
⎪⎪
⎧⎫
⋅=
K
ξd and γ,,
xyz,,()4 4 0,5,,()=
(a) (b)
Fig. 3.Using loga i hm o acili a e he sea ch o he global minimum
x
y
z
x
y
z
minimize yoi x() 1iP≤≤,
subjec o
ysj x() Ysj o ysj x() Ysj
≤1jQ≤≤,≥
ywk x() Ywk o ywk x() Ywk
≤1,kR≤≤≥
⎩
⎨
⎧
Tool s o Au oma ed Design o ΣΔ Modula o s 8
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
whe e deno es he i- h design objec i e; a e cons ained speci ica ions (w and s
deno e weak and s ong espec i ely) and a e he co esponding goals. The uncon-
s ained cos unc ion is de ined as:
(7)
whe e A deno es he accep ance egions, and whe e he pa ial cos unc ions a e gi en by,
(8)
is he weigh associa ed o he i- h design objec i e, a eal posi i e numbe (al e na i ely nega-
i e) i is posi i e (al e na i ely nega i e); o we ha e
(9)
is he weigh associa ed o he k- h weak es ic ion -- a eal posi i e numbe (al e na i ely neg-
a i e) i he weak es ic ion is o ype (al e na i ely ype). These weigh s a e used o
gi e p io i y o some weak es ic ions. The e is no ela ion be ween he objec i es and he weigh s
o weak es ic ions [18].
B. OPTIMIZATION ALGORITHM
Fig. 4 shows a block diag am o he ope a ion low o he p oposed i e a ion p ocedu e. The
upda ing ec o , Δxn, is andomly gene a ed a each i e a ion. The alue o he cos unc ion is cal-
cula ed a each new poin o he pa ame e space, and compa ed wi h he p e ious one. The new poin
is accep ed i he cos unc ion has a lowe alue. I may also be accep ed i he cos unc ion
inc eases, acco ding o a p obabili y unc ion,
(10)
depending on a con ol pa ame e , T ( empe a u e). This p obabili y o accep ance changes du ing
he op imiza ion p ocess, being high a he beginning ( o la ge T) and dec easing as he sys em cools
(dec easing T). This is he well known Me opolis algo i hm [17]. Ou ool enhances he basic algo-
i hms used o cooling schedule (mechanism o upda e T) and design pa ame e upda ing (mecha-
nism o gene a e Δxn).
yoi ysj y ywk
Ysj y Ywk
Ψx() Φyoi
()i xA∈
max Fsj ysj
()Fwk ywk
(),[]i xA∉
⎩
⎪
⎨
⎪
⎧
=
Φyoi
() wiyoi
()log
i
∑
–= Fsj ysj
()Ksj ysj Ysj
,()=,
Fwk ywk
() wk
ywk
Ywk
--------
⎝⎠
⎛⎞
log–=
wi
yoi Ksj .()
Ksj ysj Ysj
,() ∞– i s ong es ic ion holds
∞ o he wise
⎩
⎨
⎧
=
wk
≥≤
PP
oeΦT⁄Δ()–
=
Tool s o Au oma ed Design o ΣΔ Modula o s 9
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
1. Cooling Schedule
In classical simula ed annealing algo i hm he cooling schedule is de e mined by ou pa am-
e e s: ini ial alue o T, s op c i e ium, e olu ion law o T, and Ma ko chain leng h [17]. Ou ool
inco po a es an algo i hm based in he use o a composed empe a u e [8],
(11)
is employed o sol e possible discon inui ies o he cos unc ion in he bo de o he accep-
ance egion. On he o he hand, is a unc ion o he i e a ion coun and can a y non-mono-
onically wi h successi e e-hea ings and coolings. The ool inco po a es an adap i e mechanism o
au oma ically se he empe a u e and hus, keep a gi en accep ance a io. Fig. 5 depic s he p oce-
du e. The ins an aneous accep ance a io (one i he i e a ion has been accep ed, ze o i no )
is low-pass il e ed and he esul is compa ed o he speci ied accep ance a io (commonly
la ge a he beginning and dec easing wi h he i e a ion coun ). The di e ence be ween he ideal and
ac ual accep ance a io is in eg a ed o ob ain he new i e a ion empe a u e. The eedback loop
o ces he empe a u e o e ol e such ha ollows -- depic ed in Fig. 6. When compa ed
wi h classical cooling schedules, he p esence o spon aneous as hea ings and cooling has p o en
o be aluable o minimize complica ed mul i-minimum unc ions. In addi ion, he quali y o he
inal esul is only sligh ly dependen on he numbe o a iables -- e y con enien o analog sizing,
New
mo emen
Δxn
Fig. 4.Flow diag am o he p oposed me hodology
Ini ial pa ame e se x0
Sí
Cos unc ion e elua ion
Ψ(x)
(ELECTICAL SIMULATION)
(EQUATION DATABASE) Tepe a u e and
mo emen scale
upda ing
End
P ocess?
Me opolis
algo i hm
Disc e ize
design space
No
Local op imiza ion OPTIMIZER
Tαx()Ton()=
αx()
Ton()
an[]
in[]
n[] in[]
Tool s o Au oma ed Design o ΣΔ Modula o s 16
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
a 100MIPs wo ks a ion. These sho CPU imes a e a posi i e consequence o using equa ions, and
ende he abili y o explo e design spaces h ough i e a ions o he op imum high-le el syn hesis
p ocedu e. Fo bo h a chi ec u es he sampling capaci o was ixed o a ela i ely small alue o e al-
ua e he abili y o he p ocedu e o ob ain easible designs in spi e o a ela i ely la ge he mal noise
con ibu ion. In pa icula , he he mal noise con ibu ed by a sampling capaci o o 1pF is a he e y
bo de o easibili y o he ou h-o de SC modula o (see he bo om pa o Table III). In his
sense, he summa y o noise con ibu ions epo ed by he ool is o in e es o guide design explo a-
ion i speci ica ions a e no me , and a new i e a ion o he high-le el syn hesis p ocedu e is
equi ed.
Fig. 11 illus a es he use o he as a chi ec u e explo a ion ea u e o e alua e he in luence
o wo SI block e o s in he noise ans e unc ion (NTF) o he SI p o o ype: ou pu -inpu conduc-
ance a io e o , ; se ling e o ; and he e o due o changes in he eed-back loop gain in
he esona o block.
TABLE III
HIGH-LEVEL SYNTHESIS TOOL OUTPUT
OPTIMIZED SPECS FOR: 17bi @40kHz@±1.5V
Modula o Topology Cascade 2-2
Sampling equency (MHz) 5.12
O e sampling a io 128
Di e en ial e e ence ol age E (V) 0.75
In eg a o s Sampling capaci o Ci (pF) 1.0
Feed-back capaci o Co (pF) 2.0
Uni a y capaci ance (pF) >= 0.25
MOS swi ch-ON esis ance (kΩ) <= 1.0
Maximum clock ji e (ns) <= 0.9
Opamps DC-gain (dB) >= 70.7
DC-gain non-linea i y (V-2) <=20%
GB (MHz) >= 15.3
Slew- a e (V/us) >= 57.35
To al ou pu swing (V) >= 6.0
Inpu noise densi y (nV/sq (Hz)) <= 15.0
Compa a o s Hys e esis (V) <= 0.33
Resolu ion ime (ns) <= 24.41
Technology Cap Non-linea i y (ppm/V) <=50.0
RESOLUTION & NOISE POWER CONTRIBU-
TIONS
Dynamic ange: 104dB (17bi )
Quan iza ion noise (dB)
The mal noise (dB)
Incomple e se ling noise (dB)
Ji e noise (dB)
Ha monic dis o ion (dB)
-118.2
-104.3
-177.7
-111.2
-117.7
εgεs

Tool s o Au oma ed Design o ΣΔ Modula o s 17
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
Fig. 12(a) p esen s he schema ic o he opamp used o he SC opology: a olded-cascode
ully-di e en ial OTA wi h degene a ed mi o common-mode eedback [19]. Fig. 10(b) shows he
SI in eg a o used o implemen he esona o s in he SI p o o ype [21]. Wi h ega ds o he compa -
a o , since speed a he han hys e esis is he mo e demanding speci ica ion o bo h modula o s, we
used he egene a i e la ches: Fig. 12(b) o SC and Fig. 12(c) o SI.
The ool was used o au oma ically size he OTA, he SI in eg a o and he compa a o s o mee
/ s
ει=0.1%
ει=0.25%
ει=0.5%
/ s
0.24 0.25 0.26
-50
-40
-30
-20
-10
0.24 0.25 0.26
-50
-40
-30
-20
-10
0.24 0.25 0.26
-50
-40
-30
-20
-10
NTF () dB()
/ s
NTF () dB()
NTF () dB()
εg0≠εs0≠
εR0≠
Fig. 11. In luence o non-ideali ies on NTF(z)
M1M2
M3M4
M5
M6M7
M8M9
M10
M11
M12 M13
M14 M15
M16
M17 M18
M19 M20
M21
M22
M23 M24
M25
M26
M27
M28
Ibias
− + o+ o−
M1M2
M3M4
M10
M9
M7M5M6M8
M11
M13
M12
M14
+ −
φ1
SR
φ1φ1
φ1
φ2d
φ2d
In+
In-
RS
φ1
φ2d
(a)
(b) (c)
Fig. 12.(a) Folded-cascode OTA. (b) and (c) Regene a i e la ches
Tool s o Au oma ed Design o ΣΔ Modula o s 18
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
he speci ica ions esul ing om he high-le el syn hesis. The op imiza ion p ocess o ob ain he
sizes o he class-AB OTA equi ed 45min CPU ime, 35min o he SI in eg a o and 30min o he
compa a o s. In all cases, he sizing s a ed om sc a ch and no designe i e a ion was equi ed. As
an example, Table VI shows simula ed and measu ed pe o mances o he olded-cascode OTA
showing good conco dance wi h he speci ica ions.
Fig. 13(a) shows a die pho og aph o he comple e SC p o o ype wi h 0.94mm2 a ea and powe
consump ion o 10mW@5V. A mic opho og aph o he SI p o o ype wi h 0.43mm2 co e a ea ope -
a ing wi h 15mW@5V is shown in Fig. 13(b). To e alua e he pe o mance o he wo modula o s,
a es boa d was ab ica ed ollowing he indica ions in [20] o educe capaci i e and induc i e cou-
TABLE IV
SIMULATED AND MEASURED RESULTS FOR THE FOLDED-
CASCODE OTA
Specs Simula ed Measu ed Uni s
DC-gain ≥ 71 78.52 76.01 dB
GB (1pF) ≥ 16 34.88 −MHz
GB(12pF,
1MΩ)
4.17 4.21 MHz
PM(1pF) ≥ 60 66.28 −Deg.
PM(12pF,
1ΜΩ)
87.2 86.8 Deg.
Inpu whi e
noise
≤ 15 13.53 −nV/√Hz
SR ≥ 58 74.81 70.5 V/μs
OS ≥ ±3± 3.2 ± 3.0 V
O se − − 3.35 mV
Powe minimize 1.95 1.93 mW
In eg a o 1
In eg a o 2
In eg a o 4
In eg a o 3
Comp1
Comp2
Clock
Fig. 13.Mic opho og aphs o he (a) SC p o o ype (1.2μm CMOS), and (b) SI p o o ype (0.8μm CMOS).
(a) (b)
Tool s o Au oma ed Design o ΣΔ Modula o s 19
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
plings. The modula o inpu was p o ided using a high-quali y di e en ial sinusoidal signal sou ce
(less han -100dB THD) h ough a simple passi e low-pass il e o p e en aliasing. The ou pu
se ies we e acqui ed wi h an HP82000 uni and ans e ed o a wo ks a ion o p ocessing. The can-
cella ion logic o he ou h-o de modula o , as well as he decima ion digi al il e s, we e imple-
men ed on a wo ks a ion using he same signal p ocesso as used o simula ions.
Fig. 14(a) p esen s he SNR o he ou h-o de modula o as a unc ion o he inpu le el o
h ee alues o he o e sampling a io: 128 (nominal alue), 64, and 32 which lead o 40, 80, and
160kHz digi al ou pu a e, espec i ely. No e ha he modula o pe o mance app oaches he ideal
as he o e sampling a io dec eases, due o he ac ha o low o e sampling a io he modula o is
no he mal noise limi ed and hus, quan iza ion noise domina es. The co esponding cu e o he
SI modula o wi h +-5kHz bandwid h a ound he cen al equency is gi en in Fig. 14(b). Fig.15(a)
p esen s he baseband spec um o he SC p o o ype ob ained h ough an FFT o 65,536 consecu i e
ou pu samples. The inpu was a -9dBV@4kHz sinewa e sampled a 5.12MHz and compa ed o he
ou pu spec um o i s i s s age, a second-o de modula o . Di e ences be ween he wo noise shap-
ing unc ions a e isible. Howe e , he baseband o he ou h-o de modula o is domina ed by
unshaped he mal noise. Ou simula ions show ha his phenomena can be explained aking in o
accoun ha he inpu noise powe spec al densi y o he olded-cascode opamp was la ge han
expec ed. The ou pu spec um o he band-pass modula o o [email p o ec ed] inpu one is
shown in Fig.15. Finally Table V summa izes he pe o mance o bo h modula o s.
TABLE V
PERFORMANCE OF THE FOURTH-ORDER ΣΔ MODULATOR
SC Modula o SI Modula o
O e sampling Ra io 128 64 32 165
Resolu ion 16.7 15.5 14.8 8
SNR (dB)
signal le el (dB)
-50 -40 -30 -20 -10 0
45
40
35
30
25
20
15
10
5
-80.0 -60.0 -40.0 -20.0 0.0
INPUT LEVEL (dBV)
10.0
30.0
50.0
70.0
90.0
SNR (dB)
M=128
M=64
M=32
Fig. 14.(a)SNR o he ou h-o de p o o ype as a unc ion o he inpu le el o h ee al-
ues o he o e sampling a io; (b)SNR o he SI modula o .
(a) (b)
Tool s o Au oma ed Design o ΣΔ Modula o s 20
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
V. REFERENCES
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[2] T. Ri oniemi: “High-Speed 1-Bi ΣΔ−Modula o s”. Wo kshop on Ad ances in Analog Ci cui Design, pp. 191-203.
Del , Ap il 1992.
[3] G.C. Temes and B. Leung: “ΣΔ Da a Con e e A chi ec u es wi h Mul ibi In e nal Quan ize s”. P oc. 11 h Eu o-
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[4] “HSPICE: Use ’s Manual”. Me a So wa e Inc., 1988.
[5] S. R. No swo hy, I. G. Pos and H. S. Fe e man: “A 14-bi 80-kHz Sigma-Del a A/D Con e e : Modeling, Design
and Pe o mance E alua ion”. IEEE Jou nal o Solid-S a e Ci cui s, Vol. SC-24, pp. 256-266, Ap il 1989.
[6] C. H. Wol and L. Ca ley: “Simula ion o Δ-Σ Modula o s Using Beha io al Models”. P oc. ISCAS’90, pp. 376-
379, 1990.
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Con e e s”. P oc. ISCAS’91, pp. 2677-2680, 1991.
[8] F. Medei o: “Au oma ed Design o SC ΣΔ Modula o s”. PhD disse a ion, Uni . Se ille, 1996.
[9] “MATLAB: Use ’s Guide”. The Ma hWo ks Inc., 1991.
DR 102dB 95dB 91dB 50dB
SNR-peak 98.2dB 92.5dB 88.2dB 47dB
TSNR-peak 88dB 85dB 82dB --
Noise Floo -110dB --
Max. Inpu 1V 10μA
Max. Sampling F eq. 5.12 MHz 5 MHz
Powe (A e age) 10 mW 15 mW
A ea (wi hou pads) 0.94 mm20.46 mm2
TABLE V
PERFORMANCE OF THE FOURTH-ORDER ΣΔ MODULATOR
SC Modula o SI Modula o
O e sampling Ra io 128 64 32 165
Fig. 15.Ou pu spec ums: (a) Low-pass SC modula o , (b) Band-pass SI modula o
2nd-o de
shaped noise
4 h-o de
shaped noise
-130
-110
-90
-70
-50
-30
-10
OUTPUT SPECTRUM (dBV)
0 50 100 150 200
FREQUENCY (kHz)
(a) (b)
Tool s o Au oma ed Design o ΣΔ Modula o s 21
Wo kshop on Ad ances in Analog Ci cui Design--Lausanne, 1996
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