Tools for Automated Design of ΣΔ Modulators

Tool s for Automated Design of ΣΔ Modulators 1 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 Tools For Automated Design of ΣΔ Modulators F. Medeiro, J.M. de la Rosa, B. Pérez-Verdú and A. Rodríguez-Vázquez Centro Nacional de Microelectrónica-Universidad de Sevilla Edificio CICA, C/Tarfia sn, 41012-Sevilla, SPAIN Phone #34 5 4239923, FAX #34 5 4231832 email: [email protected] Abstract We present a set of CAD tools to design ΣΔ modulators. They use statistical optimization to calculate optimum specifications for the building blocks used in the modulators, and optimum sizes for the components in these blocks. Optimization procedures at the modulator level are equationbased, while procedures at the cell level are simulation-based. The toolset incorporates also an advanced ΣΔ behavioral simulator for monitoring and design space exploration. We include measurements taken from two silicon prototypes: 1) a 17bit@40kHz output rate fourth-order low-pass modulator; and 2) a [email protected] central freq@10kHz bandwidth band-pass modulator. The first uses SC fully-differential circuits in a 1.2μm CMOS double-metal double-poly technology. The second uses SI fully-differential circuits in a 0.8μm CMOS double-metal single-poly technology. Foonote This work has been supported by the CEE ESPRIT Program in the framework of the Project #8795 (AMFIS) © Springer. This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders. All persons copying this information are expected to adhere to the terms and constraints invoked by each author’s copyright. In most cases, these works may not be reposted without the explicit permission of the copyright holder. Tool s for Automated Design of ΣΔ Modulators 2 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 Tools For Automated Design of ΣΔ Modulators I. INTRODUCTION The performance of a ΣΔ converter IC is ultimately limited by its analog circuitry: the ΣΔ modulator front-end. Thus, efforts to enhance the performance or widen the application range of these converters concentrate mostly on the modulator and follow two parallel and largely correlated directions: exploration of high-order architectures and/or multibit quantizers and, pushing the specifications of analog cells used in the modulators at their performance edges [1][2][3]. The confrontation of these issues poses significant difficulties to IC designers. Some of the problems encountered are general of analog IC design: large number of specifications, complicated relationships between specifications and design parameters, involved analysis, critical specifications significantly sensitive to mismatch, etc. Others are specific to ΣΔ modulators; in particular, its accurate simulation is costly due to its highly non-linear dynamics and the necessity to use long time-series of data for evaluation purposes [5][6][7]. These difficulties render the design of ΣΔ modulator ICs a time- and resourceconsuming process, and have prompted the development of tools which can help to increase designer productivity and, thus, reduce time-to-market and production cost of forthcoming generations of ΣΔ- based mixed-signal ASICs. This chapter presents a set of CAD tools for computer-aided design of CMOS switched-capac- itor (SC) and switched-current (SI) ΣΔ modulators for low-pass and band-pass applications. These tools use optimization at the modulator and cell levels, advanced behavioral simulation at the modulator level, and include the capability of fast design space exploration of modulator architectures. The tools are vertically integrated to support top-down design of ΣΔ modulators, from the high-level specifications to the sizes of the cells. Their use is demonstrated in the paper through two fully-dif- ferential silicon prototypes in CMOS technologies: a fourth-order two-stage SC ΣΔ modulator and a fourth-order band-pass SI ΣΔ modulator. II. TOOL DIAGRAM Fig. 1 shows the design flow of ΣΔ modulators. It comprises top-down synthesis tasks: 1. Topology selection, i.e., to identify the best suited modulator architecture for the required high-level converter specifications (signal baseband, resolution, etc.); 2. Modulator sizing, i.e., to map these high-level specifications into specifications of the basic building blocks (such as gain-bandwidth product of the opamp, slew-rate, comparator hysteresis, etc.); 3. Analog cell selection, i.e., to choose the cell schematics according to the specifications; 4. Cell sizing, i.e., to map the cell specifications into values of their components; 5. Layout. Tool s for Automated Design of ΣΔ Modulators 3 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 These top-down tasks are complemented with bottom-up analyses: 6. Modulator simulation at the architectural level, to verify correctness of the results of highlevel synthesis. Due to the large circuit complexity, and the need for long time series at the modulator output, this analysis is more conveniently handled through dedicated behavioral simulation. 7. Cell simulation, to verify synthesis at the electrical level using SPICE-like simulators [4]. 8. Extracted layout simulation at electrical level -- very costly in CPU time and memory resources. Thus, it is typically used just to check connectivity and evaluate block performance degradation due to layout parasitics (not shown in Fig. 1). The selection tasks (either modulators or cells) involve knowledge issues. The proposed tools include procedures to help designers in gaining insight about the operation of different modulator architectures, and hence guiding their selection. On the other hand, the sizing tasks involve principally optimization issues -- realized in our design framework through the use of statistical optimization techniques. Fig. 2 is a flow diagram of the top-down vertical integration of the set of tools described in this chapter [8]. III. DESIGN EQUATION DATABASE These represent the behavior of typical modulator architectures realized with switched-capac- itor (SC) and switched-current (SI) building blocks. The database has been conceived to be easily Modulator Specifications Block specifications Opamps Quantizers Switches Simulation ok? LAYOUT Topology selection Cell selection Simulation ok? Fig. 1.Modulator design operation flow Y I2 XE g2 -g2' g1 -g1' D/A I1 v−v+o+o− vb1 vb2 vb3 vb4 Tool s for Automated Design of ΣΔ Modulators 4 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 extendible and includes single-loop as well as cascaded architectures, low-pass and band-pass, single-bit and multi-bit. Equations describing these architectures are classified in three categories: •Architecture-related. These represent the quantization noise as a function of the non-ide- alities that affect its shaping. Their analytical expressions may be largely different for the different modulator architectures [8]. •Circuit-related. These represent noise sources other than quantization: thermal noise, incomplete settling, harmonic distortion, etc [8]. •Fundamental limits. They cover trade-offs between power consumption, resolution, speed, etc., for the different topologies. They are used to guide modulator selection [1][11][13][15]. Table I summarizes the noise and distortion contributions covered in the two first categories above, together with the responsible building block. As an example, Table II shows the approximate expressions for the power of noise and harmonic distortion of a cascaded SC 2-2 architecture (see Fig. 10(a) [11][16]) . IV. SIZING Specifications contemplated for sizing include constraints on the performance parameters and design objectives. Their meaning is clarified considering for instance an opamp with the following Behavioral models Modulator Specs. Equations Fast architecture exploration High-level synthesis Cell sizing Electrical simulator Optimizer LAYOUT Behavioral simulation Fig. 2.Tool block diagram Tool s for Automated Design of ΣΔ Modulators 5 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 specifications: DC-gain > 70dB; gain-bandwidth product > 5MHz; phase margin > 60 degree; input equivalent noise < 3μV; with minimum power consumption and silicon area occupation. We call constraints to the four first specifications that include > or < symbols, and design objectives to the last two, whose goal is to maximize or minimize some magnitude. Sizing itself is performed through a sequence of movements in the design space until a cost function reaches a minimum. The main related issues are cost function formulation, and the genera- TABLE I NON-IDEALITIES CONSIDERED IN THE TOOL Building Blocks Non-idealities Consequences Opamps DC-gain, finite and non-linear Increased quantization noise, harmonic distortion. SR, limited Settling noise, harmonic distortion. GB, limited Incomplete settling noise. O.S. limited Overloading. Thermal Noise White noise. Switches ON-resistance, feedthrough Settling noise, white noise, harmonic distortion. Capacitors Non-linear, mismatching Increased quantization noise, harmonic distortion. Clock Jitter Jitter Noise. Comparators Hysteresis, resolution time Increased quantization noise. Quantizers Non-linearity Harmonic distortion. TABLE II APPROXIMATE ERROR POWER FOR A CASCADED ARCHITECTURE 2-2 Quantization noise Incomplete settling noise Thermal noise Non-linear capacitor distortion Non-linear opamp dc-gain distortion Jitter noise Δ2 12 ------4π2 3M3 ---------- μ2δA 2π4 5M5 ------------ d1 2π8 9M9 ----------++ ⎩⎭ ⎨⎬ ⎧⎫ Δ2 9M --------1 Cp C1 ------+ ⎝⎠ ⎛⎞ 2ς2gm Ceq ---------TS – ⎝⎠ ⎛⎞ exp 1C12 C11 --------+ ⎝⎠ ⎛⎞ kT 4MC11 ----------------- 1 C12 2 C11 2 ---------+ ⎝⎠ ⎜⎟ ⎛⎞ kT 6MCi --------------kTgmRon 2MCi ----------------------+ ⎝⎠ ⎛⎞ + α2 8 ------Δ 2 --- ⎝⎠ ⎛⎞ 4β2 32 ------Δ 2 --- ⎝⎠ ⎛⎞ 6 + α121k1 +() 2 4A0 2 ----------------------------------k2 4 k1 6 ----- Δ 2 --- ⎝⎠ ⎛⎞ 4α221k1 +() 2 8A0 2 ----------------------------------k2 6 k1 8 ----- Δ 2 --- ⎝⎠ ⎛⎞ 6 + Δ 2 --- ⎝⎠ ⎛⎞ 22πfbσt () 2 2M ------------------------ Tool s for Automated Design of ΣΔ Modulators 6 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 tion of movements and the management of the optimization procedure. A. COST FUNCTION FORMULATION The sizing of modulators and cells are formulated as constrained optimization problems, (1) where is the vector of design parameters, which defines a L-dimensional parameter space. From (1) an equivalent unconstrained problem is defined using different strategies for modulators and cells. 5. Cost function for modulator sizing Calculated block specifications must fulfill the modulator specifications and, at the same time, be the best suited for implementation. For instance, the DC-gain and GBW of the opamps should be the lowest among the set of values which yield feasible modulators. The modulator specifications are mapped onto a single constraint: (2) where is the total in-band output noise power at the modulator output, and is the maximum power that guarantees the modulator specifications: resolution, bandwidth and maximum input level. The cost function is given by: (3) where represents the value of the j-th block specification. The sign of the weight parameters , indicates if the objective must be maximized or minimized. On the other hand, the normalization factors, (4) are used to cope with large variations of the absolute values of different block specifications. Logarithms in (3) renders the cost function smoother and thus, enable the trajectory to escape from local minima. The example of Fig. 3 illustrates the benefits of using logarithms. It corresponds to, minimize Φx()[]subject to φrx() 01rR≤≤;≤ xx1x2…xL ,,,() T = PNx() PNmax,0≤– PNx() PNmax, Ψx() Kj xj xjnorm, ---------------- ⎝⎠ ⎛⎞ log j1= N ∑ –if xA∈ PNx() PNmax, ----------------- ⎝⎠ ⎛⎞ log if xA∉ ⎩ ⎪ ⎪ ⎪ ⎨ ⎪ ⎪ ⎪ ⎧ = xjKj xjnorm, xjmin,if Kj0> xjmax,if Kj0< ⎩ ⎪ ⎨ ⎪ ⎧ = Tool s for Automated Design of ΣΔ Modulators 7 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 (5) where are constants. Fig. 3(a) depicts (5), which has the absolute minimum in , and many local minima in its neighborhood. The values of the function at these minima are compressed into the interval [0.4, 0.5]. On the other hand, Fig. 3(b) depicts the result of taking the logarithm of (5), where the minima are more clearly separated. Functions like this are commonly found in modulator and cell sizing [8]. A. Cost function for cell sizing Constraints related to cell sizing are classified in two groups: •Strong restrictions: These are specifications whose fulfillment is considered essential by the designer; for instance, the phase margin of an opamp must be larger than 0 for stability. No relaxation of the specified value is allowed. •Weak restrictions: These are the typical performance specifications required for analog building blocks, i.e. opamp DC-gain > 80dB. Unlike strong restrictions, weak restrictions allow some relaxation of their targets, making circuits which do not exactly meet the targets acceptable. The costs function for cell sizing must reflect both types of constraints: (6) fx() Kmin e– ξxkd–() 2 k1= N ∑ – xkd–()cos k1= N ∏e ξ–xkd–() 2 k1= N ∑ –,xkd+()γ+cos k1= N ∏ ⎩⎭ ⎪⎪ ⎪⎪ ⎨⎬ ⎪⎪ ⎪⎪ ⎧⎫ ⋅= K ξd and γ,, xyz,,()4 4 0,5,,()= (a) (b) Fig. 3.Using logarithm to facilitate the search of the global minimum x y z x y z minimize yoi x() 1iP≤≤, subject to ysj x() Ysj or ysj x() Ysj ≤1jQ≤≤,≥ ywk x() Ywk or ywk x() Ywk ≤1,kR≤≤≥ ⎩ ⎨ ⎧ Tool s for Automated Design of ΣΔ Modulators 8 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 where denotes the i-th design objective; are constrained specifications (w and s denote weak and strong respectively) and are the corresponding goals. The unconstrained cost function is defined as: (7) where A denotes the acceptance regions, and where the partial cost functions are given by, (8) is the weight associated to the i-th design objective, a real positive number (alternatively negative) if is positive (alternatively negative); for we have (9) is the weight associated to the k-th weak restriction -- a real positive number (alternatively negative) if the weak restriction is of type (alternatively type). These weights are used to give priority to some weak restrictions. There is no relation between the objectives and the weights of weak restrictions [18]. B. OPTIMIZATION ALGORITHM Fig. 4 shows a block diagram of the operation flow of the proposed iteration procedure. The updating vector, Δxn, is randomly generated at each iteration. The value of the cost function is calculated at each new point of the parameter space, and compared with the previous one. The new point is accepted if the cost function has a lower value. It may also be accepted if the cost function increases, according to a probability function, (10) depending on a control parameter, T (temperature). This probability of acceptance changes during the optimization process, being high at the beginning (for large T) and decreasing as the system cools (decreasing T). This is the well known Metropolis algorithm [17]. Our tool enhances the basic algorithms used for cooling schedule (mechanism to update T) and design parameter updating (mechanism to generate Δxn). yoi ysj y ywk Ysj y Ywk Ψx() Φyoi ()if xA∈ max Fsj ysj ()Fwk ywk (),[]if xA∉ ⎩ ⎪ ⎨ ⎪ ⎧ = Φyoi () wiyoi ()log i ∑ –= Fsj ysj ()Ksj ysj Ysj ,()=, Fwk ywk () wk ywk Ywk -------- ⎝⎠ ⎛⎞ log–= wi yoi Ksj .() Ksj ysj Ysj ,() ∞– if strong restriction holds ∞ otherwise ⎩ ⎨ ⎧ = wk ≥≤ PP oeΦT⁄Δ()– = Tool s for Automated Design of ΣΔ Modulators 9 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 1. Cooling Schedule In classical simulated annealing algorithm the cooling schedule is determined by four parameters: initial value of T, stop criterium, evolution law for T, and Markov chain length [17]. Our tool incorporates an algorithm based in the use of a composed temperature [8], (11) is employed to solve possible discontinuities of the cost function in the border of the acceptance region. On the other hand, is a function of the iteration count and can vary non-mono- tonically with successive re-heatings and coolings. The tool incorporates an adaptive mechanism to automatically set the temperature and thus, keep a given acceptance ratio. Fig. 5 depicts the procedure. The instantaneous acceptance ratio (one if the iteration has been accepted, zero if not) is low-pass filtered and the result is compared to the specified acceptance ratio (commonly large at the beginning and decreasing with the iteration count). The difference between the ideal and actual acceptance ratio is integrated to obtain the new iteration temperature. The feedback loop forces the temperature to evolve such that follows -- depicted in Fig. 6. When compared with classical cooling schedules, the presence of spontaneous fast heatings and cooling has proven to be valuable to minimize complicated multi-minimum functions. In addition, the quality of the final result is only slightly dependent on the number of variables -- very convenient for analog sizing, New movement Δxn Fig. 4.Flow diagram of the proposed methodology Initial parameter set x0 Sí Cost function eveluation Ψ(x) (ELECTICAL SIMULATION) (EQUATION DATABASE) Teperature and movement scale updating End Process? Metropolis algorithm Discretize design space No Local optimization OPTIMIZER Tαx()Ton()= αx() Ton() an[] rin[] rn[] rin[] Tool s for Automated Design of ΣΔ Modulators 16 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 a 100MIPs workstation. These short CPU times are a positive consequence of using equations, and render the ability to explore design spaces through iterations of the optimum high-level synthesis procedure. For both architectures the sampling capacitor was fixed to a relatively small value to evaluate the ability of the procedure to obtain feasible designs in spite of a relatively large thermal noise contribution. In particular, the thermal noise contributed by a sampling capacitor of 1pF is at the very border of feasibility for the fourth-order SC modulator (see the bottom part of Table III). In this sense, the summary of noise contributions reported by the tool is of interest to guide design exploration if specifications are not met, and a new iteration of the high-level synthesis procedure is required. Fig. 11 illustrates the use of the fast architecture exploration feature to evaluate the influence of two SI block errors in the noise transfer function (NTF) of the SI prototype: output-input conductance ratio error, ; settling error ; and the error due to changes in the feed-back loop gain in the resonator block. TABLE III HIGH-LEVEL SYNTHESIS TOOL OUTPUT OPTIMIZED SPECS FOR: 17bit@40kHz@±1.5V Modulator Topology Cascade 2-2 Sampling frequency (MHz) 5.12 Oversampling ratio 128 Differential reference voltage E (V) 0.75 Integrators Sampling capacitor Ci (pF) 1.0 Feed-back capacitor Co (pF) 2.0 Unitary capacitance (pF) >= 0.25 MOS switch-ON resistance (kΩ) <= 1.0 Maximum clock jitter (ns) <= 0.9 Opamps DC-gain (dB) >= 70.7 DC-gain non-linearity (V-2) <=20% GB (MHz) >= 15.3 Slew-rate (V/us) >= 57.35 Total output swing (V) >= 6.0 Input noise density (nV/sqrt(Hz)) <= 15.0 Comparators Hysteresis (V) <= 0.33 Resolution time (ns) <= 24.41 Technology Cap Non-linearity (ppm/V) <=50.0 RESOLUTION & NOISE POWER CONTRIBUTIONS Dynamic range: 104dB (17bit) Quantization noise (dB) Thermal noise (dB) Incomplete settling noise (dB) Jitter noise (dB) Harmonic distortion (dB) -118.2 -104.3 -177.7 -111.2 -117.7 εgεs Tool s for Automated Design of ΣΔ Modulators 17 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 Fig. 12(a) presents the schematic of the opamp used for the SC topology: a folded-cascode fully-differential OTA with degenerated mirror common-mode feedback [19]. Fig. 10(b) shows the SI integrator used to implement the resonators in the SI prototype [21]. With regards to the comparator, since speed rather than hysteresis is the more demanding specification for both modulators, we used the regenerative latches: Fig. 12(b) for SC and Fig. 12(c) for SI. The tool was used to automatically size the OTA, the SI integrator and the comparators to meet f/fs ει=0.1% ει=0.25% ει=0.5% f/fs 0.24 0.25 0.26 -50 -40 -30 -20 -10 0.24 0.25 0.26 -50 -40 -30 -20 -10 0.24 0.25 0.26 -50 -40 -30 -20 -10 NTF f() dB() f/fs NTF f() dB() NTF f() dB() εg0≠εs0≠ εR0≠ Fig. 11. Influence of non-idealities on NTF(z) M1M2 M3M4 M5 M6M7 M8M9 M10 M11 M12 M13 M14 M15 M16 M17 M18 M19 M20 M21 M22 M23 M24 M25 M26 M27 M28 Ibias v−v+vo+vo− M1M2 M3M4 M10 M9 M7M5M6M8 M11 M13 M12 M14 v+v− φ1 SR φ1φ1 φ1 φ2d φ2d In+ In- RS φ1 φ2d (a) (b) (c) Fig. 12.(a) Folded-cascode OTA. (b) and (c) Regenerative latches Tool s for Automated Design of ΣΔ Modulators 18 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 the specifications resulting from the high-level synthesis. The optimization process to obtain the sizes for the class-AB OTA required 45min CPU time, 35min for the SI integrator and 30min for the comparators. In all cases, the sizing started from scratch and no designer iteration was required. As an example, Table VI shows simulated and measured performances of the folded-cascode OTA showing good concordance with the specifications. Fig. 13(a) shows a die photograph of the complete SC prototype with 0.94mm2 area and power consumption of 10mW@5V. A microphotograph of the SI prototype with 0.43mm2 core area operating with 15mW@5V is shown in Fig. 13(b). To evaluate the performance of the two modulators, a test board was fabricated following the indications in [20] to reduce capacitive and inductive cou- TABLE IV SIMULATED AND MEASURED RESULTS FOR THE FOLDEDCASCODE OTA Specs Simulated Measured Units DC-gain ≥ 71 78.52 76.01 dB GB (1pF) ≥ 16 34.88 −MHz GB(12pF, 1MΩ) 4.17 4.21 MHz PM(1pF) ≥ 60 66.28 −Deg. PM(12pF, 1ΜΩ) 87.2 86.8 Deg. Input white noise ≤ 15 13.53 −nV/√Hz SR ≥ 58 74.81 70.5 V/μs OS ≥ ±3± 3.2 ± 3.0 V Offset − − 3.35 mV Power minimize 1.95 1.93 mW Integrator1 Integrator2 Integrator4 Integrator3 Comp1 Comp2 Clock Fig. 13.Microphotographs of the (a) SC prototype (1.2μm CMOS), and (b) SI prototype (0.8μm CMOS). (a) (b) Tool s for Automated Design of ΣΔ Modulators 19 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 plings. The modulator input was provided using a high-quality differential sinusoidal signal source (less than -100dB THD) through a simple passive low-pass filter to prevent aliasing. The output series were acquired with an HP82000 unit and transferred to a workstation for processing. The cancellation logic of the fourth-order modulator, as well as the decimation digital filters, were implemented on a workstation using the same signal processor as used for simulations. Fig. 14(a) presents the SNR of the fourth-order modulator as a function of the input level for three values of the oversampling ratio: 128 (nominal value), 64, and 32 which lead to 40, 80, and 160kHz digital output rate, respectively. Note that the modulator performance approaches the ideal as the oversampling ratio decreases, due to the fact that for low oversampling ratio the modulator is not thermal noise limited and thus, quantization noise dominates. The corresponding curve for the SI modulator with +-5kHz bandwidth arround the central frequency is given in Fig. 14(b). Fig.15(a) presents the baseband spectrum of the SC prototype obtained through an FFT of 65,536 consecutive output samples. The input was a -9dBV@4kHz sinewave sampled at 5.12MHz and compared to the output spectrum of its first stage, a second-order modulator. Differences between the two noise shaping functions are visible. However, the baseband of the fourth-order modulator is dominated by unshaped thermal noise. Our simulations show that this phenomena can be explained taking into account that the input noise power spectral density of the folded-cascode opamp was larger than expected. The output spectrum of the band-pass modulator for [email protected] input tone is shown in Fig.15. Finally Table V summarizes the performance of both modulators. TABLE V PERFORMANCE OF THE FOURTH-ORDER ΣΔ MODULATOR SC Modulator SI Modulator Oversampling Ratio 128 64 32 165 Resolution 16.7 15.5 14.8 8 SNR (dB) signal level (dB) -50 -40 -30 -20 -10 0 45 40 35 30 25 20 15 10 5 -80.0 -60.0 -40.0 -20.0 0.0 INPUT LEVEL (dBV) 10.0 30.0 50.0 70.0 90.0 SNR (dB) M=128 M=64 M=32 Fig. 14.(a)SNR of the fourth-order prototype as a function of the input level for three values of the oversampling ratio; (b)SNR for the SI modulator. (a) (b) Tool s for Automated Design of ΣΔ Modulators 20 Workshop on Advances in Analog Circuit Design--Lausanne, 1996 V. REFERENCES [1] J. C. Candy and G. C. Temes: “Oversampling Delta-Sigma Converters”. IEEE Press, 1992. [2] T. Ritoniemi: “High-Speed 1-Bit ΣΔ−Modulators”. Workshop on Advances in Analog Circuit Design, pp. 191-203. Delft, April 1992. [3] G.C. Temes and B. Leung: “ΣΔ Data Converter Architectures with Multibit Internal Quantizers”. Proc. 11th European Conference on Circuit Theory and Design (H. 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