1
Imp o ed Nanopipelined RTD Adde s using Gene alized
Th eshold Ga es
AUTHORS:
Hec o Pe enghi1, Ma ía J. A edillo*1,2, José M. Quin ana1,2
AFFILIATION:
1 Ins i u o de Mic oelec ónica de Se illa. Cen o Nacional de Mic oelec ónica. CSIC
2 Dp o. de Elec ónica y Elec omagne ismo. Uni e sidad de Se illa.
POSTAL ADDRESS FOR CORRESPONDENCE:
A da. Ame ico Vespucio 49
Telephone No. (34) 954 466666 FAX No. (34) 95 4466600
Se illa 41092
SPAIN
ABSTRACT1
Many logic ci cui applica ions o Resonan Tunneling Diodes a e based on he MOnos able-
BIs able Logic Elemen (MOBILE). Th eshold logic is a compu a ional model widely used
in he design o MOBILE ci cui s, i.e. hese ci cui s a e buil om h eshold ga es (TGs).
This pape desc ibes he design o ull adde s (FAs) using TG based ci cui opologies. Bo h
he selec ion o di e en MOBILE TG ne wo ks and he use o ga es ha can be conside ed
ex ensions o he MOBILE TG a e add essed. The FAs a e applied o he design o nan-
opipelined ca y p opaga ions adde s which a e e alua ed and compa ed o a p e iously e-
po ed one, showing ad an ages in e ms o speed, powe and powe delay p oduc .
Keywo ds: Resonan Tunneling Diodes, MOBILE, Th eshold ga e, nanopipelining, adde
*. Co esponding au ho s
2
I. INTRODUCTION
Resonan unneling de ices (RTDs) a e nowadays conside ed he mos ma u e ype o quan-
um-e ec de ices. They a e al eady ope a ing a oom empe a u e and hey exhibi e y a ac-
i e cha ac e is ics as high-speed ope a ion and low powe consump ion. RTDs a e e y as non
linea ci cui elemen s which ha e been in eg a ed wi h ansis o s o c ea e no el quan um de ices
and ci cui s. This inco po a ion o unnel diodes in o ansis o echnologies has shown an imp o ed
ci cui pe o mance: highe ci cui speed, educed componen coun , and/o lowe ed powe con-
sump ion [1], [2], [19], [20]. Mos o he epo ed wo king ci cui s ha e been ab ica ed in III/V
ma e ials while Si-based unnelling diodes compa ible o s anda d CMOS abs a e cu en ly an a ea
o ac i e esea ch [5].
RTDs exhibi a nega i e di e en ial esis ance (NDR) egion in hei cu en - ol age
cha ac e is ics (Figu e 1a) which can be exploi ed o signi ican ly inc ease he unc ion-
ali y implemen ed by a single ga e in compa ison o con en ional MOS and bipola echnolo-
gies, hus educing ci cui complexi y. Figu e 1a depic s he ci cui symbol used o RTDs and
hei ypical I-V cu e showing key pa ame e s o ci cui design: peak cu en and ol age, Ip
and Vp, and alley cu en and ol age, I and V . Many RTD based logic blocks ely on using he
clocked se ies connec ion o a pai o RTDs o Monos able Bis able Logic Elemen (MOBILE) [6]
which ope a es on he basis o he compa ison o peak cu en s (Figu e 1b). In gene al, MOBILE
logic amilies combine he basic pai o se ies-connec ed RTDs wi h di e en h ee e minal de ices
o achie e inpu -ou pu isola ion and unc ionali y (Figu e 1c). Inhe en sel -la ching p ope y o
MOBILE allows he implemen a ion o pipeline a he ga e le el.
The ope a ing p inciple o MOBILE is ex emely well sui ed o implemen he a i h-
me ic ope a ion on which Th eshold Ga es [7] (TGs) a e based [8], [9]. TGs a e a gene -
aliza ion o con en ional Boolean ga es, which a e able o implemen mo e complex
unc ions, wha is a ac i e om he poin o logic design (less ga es and in e connec-
3
ions). TG design s yle is a well ecognized powe ul al e na i e o he s anda d logic
design because o he in insic complexi y o he unc ions pe o med by TGs allowing
ealiza ions ha equi e less h eshold ga es han s anda d h eshold logic. MOBILE TGs
ha e been expe imen ally demons a ed and i has been epo ed he logic a chi ec u e o a
nanopipelined ca y p opaga ion adde using hem [10].
Cu en ly esea ch on ci cui opologies using RTDs and ansis o s is an ac i e a ea. Di e en
gene aliza ions o h eshold ga es, also sui able o be ealized wi h MOBILE RTD s uc-
u es which u he inc ease he unc ionali y o con en ional TGs, a e being in es iga ed [11],
[12], [13], [14]. Compa a i ely, less e o is dedica ed o he e alua ion and compa ison o hese
building blocks wi hin ne wo ks implemen ing logic applica ions. As in con en ional design, di e -
en ga e ne wo ks ealizing same unc ionali y exhibi di e en powe and delay pe o mance, e en
using he same logic s yle o he ga es. Fan-in and an-ou capabili ies o he building blocks a e
c i ical and hei elec ical beha iou can make a logic solu ion be e han o he s. Howe e , li le
a en ion is gi en o his in he li e a u e. This wo k explo es h eshold-ga e based MOBILE logic
s yles wi h his ocus and hei usage in he design o nanopipelined adde s ha signi ican ly
imp o e speed and educe powe -delay p oduc wi h espec o he p e iously epo ed one [10].
The es o he pape is o ganized as ollows. Sec ion II in oduces bo h he elec ical and
he logical backg ound o his wo k. Sec ion III desc ibes he design and cha ac e iza ion
o MOBILE TGs implemen a ions as a mo i a ion o he p oposed ull adde s in o-
duced in Sec ion IV. A chi ec u es o 8-bi adde s using hem a e desc ibed, simula ed
and compa ed in Sec ion V. Finally, Sec ion VI gi es some conclusions.
II. BACKGROUND
4
In his sec ion he ope a ion p inciple o clocked se ies-connec ed RTDs (MOBILE) is sum-
ma ized. Then, he h eshold ga e is o mally de ined and i s MOBILE implemen a ion
desc ibed. Finally, he p e iously epo ed RTD based adde which se es as a e e ence is
in oduced.
A. MOBILE ope a ing p inciple
The MOBILE (Figu e 1b) [6] is a ising edge igge ed cu en con olled ga e which con-
sis s o wo RTDs connec ed in se ies and d i en by a swi ching bias ol age . When
is low, bo h RTDs a e in he on-s a e (o low esis ance s a e) and he ci cui is
monos able. Inc easing o an app op ia e maximum alue ensu es ha only he de ice
wi h he lowes peak cu en swi ches (quenches) om he on-s a e o he o -s a e (o high
esis ance s a e). Ou pu is high i he d i e RTD is he one which swi ches and i is low i he
load swi ches. Assuming equal cu en densi ies o bo h RTDs, peak cu en s a e p opo ional
o RTD a eas, and , o load and d i e espec i ely. Thus, o he load
swi ches ( he ou pu goes o low o “0”) and i o he wise, , he d i e swi ches
( he ou pu goes o high o “1”).
Logic unc ionali y can be achie ed i he peak cu en o one o he RTDs is con olled by
an inpu . In he con igu a ion o an in e e MOBILE shown in Figu e 1c, he peak cu en o
he d i e RTD can be modula ed using he ex e nal inpu signal . Du ing a c i ical pe iod
when ises, he ol age a he ou pu node goes o one o he wo s able s a es (low
o high), co esponding o “0” and “1” in bina y logic. RTD a eas a e selec ed in such a way
ha he alue o he ou pu depends on whe he he ex e nal inpu signal is “1” o “0”.
Cons ain s on ela ionships among RTD a eas o in e e unc ionali y a e depic ed also in
Vbias
()
Vbias
Vbias
λA
λB
λAλB
<
Vou
λBλA
<
Vou
Vin
Vbias
Vou
Vin
5
Figu e 1c. These cons ain s assume ha he ansis o beha es like an ideal swi ch. Tha is, o
high, he ansis o does no limi he RTD cu en and i s peak cu en , which is p opo -
ional o , adds o he one o he d i e in he non unc ional b anch, . Fo high,
he ou pu node main ains i s alue e en i he inpu changes. Tha is, his ci cui s uc u e is
sel -la ching allowing o implemen pipelining a he ga e le el wi hou any a ea o e head
associa ed o he addi ion o he la ches which allows e y high h ough-ou pu . This ci cui
opology can be easily ex ended o sys ema ically implemen TGs which ha e been expe imen-
ally shown [8], [10].
A su icien ly slow Vbias ising is equi ed o MOBILE ope a ion. Tha is, he e is a c i ical
ise ime o he swi ching bias below which he ga e does no ope a e co ec ly and his de e -
mines i s ope a ing equency. Unde ha c i ical ime ise ime, he e is a leas one inpu com-
bina ion o which he ga e does no p oduce he expec ed logic ou pu . I is due o AC cu en s
associa ed o pa asi ics (mo e impo an o as e bias changes) ha somewha “al e ” he ideal
MOBILE ope a ing p inciple based on peak cu en s compa ison. This c i ical alue depends
on bo h ci cui (size o RTDs and ansis o s) and echnological pa ame e s [15], [16].
B. MOBILE TGs
Th eshold logic has been poin ed ou as an e icien compu a ional model o he design o
RTD based ci cui s. Tha is, he basic building blocks o RTD logic ci cui s a e h eshold ga es
ins ead o he con en ional Boolean ga es (AND, OR,...).
A TG o linea sepa able unc ion is de ined as a logic ga e wi h n bina y inpu a iables,
, one bina y ou pu , and o which he e is a se o eal numbe s:
h eshold T and weigh s , such ha i s inpu -ou pu ela ionship is de ined as
Vin
λ1
λB
Vbias
xii1…n,,=(),
y
n1+()
w1w2…wn
,,,

6
i , and o he wise. Sum and p oduc a e he con en ional, a he
han he logical, ope a ions. The se o weigh s and h eshold can be deno ed in a mo e com-
pac ec o no a ion way by .
Figu e 1d shows he implemen a ion o a gene ic TG de ined as y = 1 i
, and 0 o he wise. The RTD a eas de e mine he weigh s wi (i
= 1, …, 4) and he h eshold T. Inpu s ages con olled by ex e nal inpu s a e placed in pa allel
o RTD1 o RTD2 depending on whe he he associa ed weigh is posi i e o nega i e, allowing
he con ol o he peak cu en s o bo h NDRs.
C Re e ence nanopipelined TG-based adde
Figu e 2 shows he logic diag am o he nanopipelined ca y p opaga ion adde p oposed in
[10]. I consis s o a chain o ull adde s (FAs) and memo y elemen s (MOBILE bu e s and
in e e s) o suppo pipeline. Only hose associa ed wi h inpu s a e depic ed. Each FA is ealized
wi h a ne wo k o MOBILE TGs as depic ed in Figu e 3.
The FA akes h ee bina y inpu s and gene a es he ca y ou pu , which is one i wo o mo e
inpu s a e logic ones (majo i y unc ion), and he sum ou pu , ealized by an EXOR logic ope -
a ion. In he p oposed ealiza ion, he ca y ope a ion is implemen ed by a single ga e due o
he ac ha he majo i y unc ion is he h eshold unc ion [1, 1, 1; 2]. When he weigh ed sum
o inpu s is equal o g ea e han 2, he ou pu is logic 1, since all weigh s a e 1, wo o h ee
inpu s a one p oduce a high ou pu . Howe e , he sum ope a ion equi es he implemen a ion
o a h ee-inpu EXOR. This is a non h eshold unc ion and hus equi es a ne wo k o TGs.
The ou ga e ne wo k used and showed in Figu e 3a is based on a gene al echnique o imple-
men symme ic unc ions [7]. I is impo an o ealize ha i con ains he h ee-inpu majo i y
ga e as is shown. Thus, he ca y ou pu can be ex ac ed om he EXOR ne wo k di ec ly.
y1=
wixi
i1=
n
∑T≥
y0=
w1w2…wn;T,,,[]
w1x1w2x2w3x3w4x4
––+ T≥
7
Table in Figu e 3b shows ha he ou pu s o he i s le el TGs codi y he numbe o ones in
he inpu s: n1 is 1 i he e is a leas one inpu a one, n2 is 1 i he e a e a leas wo ones and n3
is one i all he h ee inpu s a e 1. Ou pu o ga e [1, -1, 1; 1] gene a es he 3-EXOR.
Ci cui schema ic is shown in Figu e 3c. Bias signals o ope a e cascaded MOBILE- ype ci -
cui s [10] a e also shown (Figu e 3d). A ou phase (e alua ion, hold, ese and wai ) o e lap-
ping clocking scheme is used. Second s age e alua es ( ising edge o Vbias2) while he i s
s age is in he hold phase (Vbias1 high). Fo a numbe o logic le els g ea e han h ee, ou
bias signals a e equi ed. In one clock pe iod all he ga es a e ac i a ed. Da a can be p ocessed
a a equency gi en by whe e is he minimum ise ime ha
p oduces a co ec beha io in all ga es o a ne wo k. O he wise, he la ency ime, , is gi en
by he numbe o le els o he ne wo k: o a ne wo k o k le els .
III. MOBILE THRESHOLD GATE IMPLEMENTATIONS
This Sec ion desc ibes some expe imen s o cha ac e iza ion o MOBILE TG implemen a-
ions which p o ide suppo o bo h he design me hodology ollowed in he implemen a ion
o he adde s, and o he new concep s on which he p oposed adde s ely on, as i will be cla -
i ied la e . As i was p e iously s a ed, he minimum alue o he ise ime o he bias signal
o which a MOBILE ga e ope a es co ec ly depends on bo h design pa ame e s, like RTD
a eas and ansis o dimensions, and echnological pa ame e s. We ha e ca ied ou ex ensi e
simula ion and analysis o MOBILE ga es in o de o de i e design guidelines o op imize hei
pe o mance and o de e mine which TGs exhibi be e pe o mance.
MOBILE TGs wi h di e en an-in ha e been designed and e alua ed using a non comme -
cial uni e si y InP echnology in which RTD and HFET ansis o s can be co-in eg a ed. Fo his
RTD, Vp is 0.21V, he peak cu en densi y 21KA/cm2, he peak o alley cu en a io is abou 6.25
max 14 c i ()
⋅()⁄=
c i ()
la
la k
⋅=
8
a oom empe a u e and he capaci ance is 4 F/μm2. The ansis o h eshold ol age is o
he deple ion HFET and o he enhancemen one. Minimum ga e-leng h is 0.6μ and
ansconduc ance pa ame e 500
μ
A/V2 (deple ion ype) and 900
μ
A/V2 (enhancemen ype).
Ga e design implies sizing o RTDs and ansis o . As in he simple in e e ga e (Figu e 1c),
a ge logic unc ionali y imposes a se o cons ain s on RTD a ea ela ionships which mus be
ul illed and which can be used o selec RTD sizes. Howe e , he solu ion o his se o ine-
quali ies is no unique. Ci cui pe o mance in e ms o ope a ing equency and powe
depends on he selec ed RTD a eas as i is shown in he ollowing. T ansis o sizing also de e -
mines co ec ope a ion and ci cui pe o mance.
Fi s , he simples TGs, he in e e (Figu e 1c) and he ollowe (inpu b anch in pa allel o
load RTD), ha e been e alua ed h ough HSPICE simula ions using expe imen ally alida ed
models o he RTDs and he ansis o s. Figu e 4 depic s ope a ing equency and PDP (powe /
equency) as a unc ion o ansis o wid h. Minimum ga e-leng h ansis o s ha e been used.
The sizes o he RTDs ha e been selec ed sol ing he design cons ain using as cos unc ion o
minimize he sum o he RTD a eas and echnological cons ain s on minimum sizes. High and
low ol age alues o clocked Vbias and Vin a e 0V and 0.7V espec i ely. Resul s o bo h
deple ion and enhancemen ansis o s a e shown. I can be clea ly obse ed ha he enhance-
men ansis o is be e o he in e e and he deple ion one o he ollowe . In addi ion, an
analysis o he ope a ion equency shows ha a la ge enough ansis o is equi ed o supply
he equi ed cu en o he RTD associa ed wi h each speci ic inpu b anch, bu i exis s an op i-
mal ansis o wid h o e which ope a ing equency s a s o decline. Al hough a la ge an-
sis o in he inpu b anch leads an NDR cha ac e is ic close o an ideal one, which explains he
ini ial inc emen o he equency, i in ol es highe pa asi ic capaci ies ha a e esponsible o
i s educ ion. Simila expe imen s ca ied ou wi h mo e complex TGs also indica e ha o
b anches in pa allel o load (d i e ) RTD deple ion (enhancemen ) HFETs a e p e e able o
0.2V–
0.2 V
9
ope a ing equency and powe -delay p oduc , as well as he exis ence o an op imal ansis o
wid h.
Figu e 5 depic s ope a ing equency and powe o di e en RTD sizings o an in e e .
They ha e been ob ained adding a e m δ o he le hand side o he design inequali ies in Fig-
u e 1c, and sol ing o di e en alues o his pa ame e wi h he cos unc ion p e iously
desc ibed. While inc easing δ, he ope a ing equency imp o es, al hough mo e signi ican ly
o lowe δ alues. Howe e , solu ions wi h la ge δ imply la ge RTD a eas and he powe
consump ion inc eases.
Second, expe imen s inc easing he an-in ha e been ca ied ou . TGs wi h posi i e uni a y
weigh s and TGs wi h nega i e uni a y weigh s wi h iden ical loads ha e been cha ac e ized.
In each case, he h eshold alue esul ing in he slowes implemen a ion has been selec ed.
Table I summa izes equency esul s. I can be clea ly obse ed ha ga es wi h nega i e
weigh s ope a e a highe equencies han hei posi i e coun e pa s. This is due o he ac
ha posi i e weigh s a e implemen ed by inpu b anches in pa allel o uppe RTD, and so hei
ansis o s ha e a ga e o sou ce ol age which is educed while e alua ion akes places (unlike
ansis o s in b anches in pa allel o bo om RTD). When bias signal s a s o ise, MOBILE
s uc u es beha e like a esis i e ol age di iso and he ou pu node ol age inc eases. This
ansla es in ha he ansis o s associa ed wi h uppe b anches a e la ge han hose in bo om
ones. In he case o he non-comme cial InP echnology ha we ha e used, his is ue e en i
deple ion ansis o s a e used o uppe b anches and enhancemen de ices o bo om ones o
compensa e (as we ha e done). La ge ansis o s mean highe in insic pa asi ic capaci ances
and loads o p e ious s ages. The expe imen sugges s ha nega i e weigh s a e p e e able.
This in o ma ion migh be exploi ed a he logic le el o de i e logic ne wo ks wi h be e pe -
o mance. This has been done in he i s p oposed FA in nex Sec ion.
16
he design o 8-bi nanopipelined ca y p opaga ion adde s and compa ed o a p e iously
epo ed one, based on TGs. All o hem ha e been implemen ed wi h he same echnology and
ollowing an iden ical me hodology. The h ee p oposed adde s exhibi be e equency and
less PDP han he p e iously epo ed one. E en i only TGs a e used bene i s a e ob ained
om he al e na i e logic diag am implemen ing he FA. The GTG adde has shown he bes
pe o mance in e ms o speed and powe consump ion in compa ison wi h TG and MTTG
ones. Nanopipelined a chi ec u es o mul iplie s and di iso s ecen ly epo ed [18] can ake
ad an age o hese ad anced p oposed adde s.
Acknowledgemen s
This e o was suppo ed by he Spanish Go e nmen unde p ojec TEC2007-67245 and
Andalusian Go e nmen h ough p ojec EXC/2007/TIC-2961.
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Resonan Tunneling Diodes” Accep ed o publica ion in IEEE T ans. on nano echnology,
al eady a ailable on-line.
[21] Pe enghi, H., A edillo, M.J., Quin ana, J.M., "Single phase clock scheme o mobile logic
ga es". Elec on. Le ., ol. 42, no. 24, pp. 1382-1383, 2006.
[22] Saeid Nooshabadi, Juan A. Mon iel-Nelson, “Fas Feed h ough Logic: A High Pe o -
mance Logic Family o GaAs”, IEEE T ans. on Ci cui s and Sys ems -I, Vol 51, N0. 11,
pp. 2189-2203, No 2004.
CAPTIONS TO THE FIGURES
Figu e 1.- MOBILE ci cui s.
a) RTD I-V cha ac e is ic.
b) Basic MOBILE.
c) MOBILE in e e .
d) MOBILE TG.
Figu e 2.- Logic diag am o pipelined n-bi ca y p opaga ion adde .
Figu e 3.- Re e ence TG FA.
a) Logic diag am.
b) Logic beha iou .
c) Ci cui s uc u e.
d) Bias scheme o MOBILE ci cui s.
Figu e 4.- Ope a ing equency and PDP as a unc ion o ansis o wid h.
a) MOBILE ollowe .
b) MOBILE in e e .
Figu e 5.- Ope a ing equency and powe consump ion as a unc ion o δ o a MOBILE
in e e .
Figu e 6.- P oposed TG FA .
(a) Logic diag am.
(b) Logic beha iou .
(c) Ci cui s uc u e.
Figu e 7.- P oposed MTTG FA.
(a) Logic diag am.
(b) Ci cui s uc u e.
Figu e 8.- Ci cui s uc u e o gene ic n-inpu GTG.
Figu e 9.- P oposed GTG FA.
(a) Logic diag am.
(b) Ci cui s uc u e.
Table I .- Ope a ing F equency o TGs
Table II .- Compa ison among 8-bi adde s
19
Figu e 1.
Load
D i e
Vbias
Vou
(b)
-1 -0.5 0.5 1
-2
-1
1
2
Vin
Vou
NDRA
NDRB
Vbias
(c)
λB
λA
λ1
λB
λA
λBλA
<
λAλBλ1
+<
λ
peak
cu en
cu en
alley
peak
ol age
V
RTD
(V)
I
RTD
(mA)
V
RTD
(V)
+
−
(a)
x4
y
Vbias
λB
λA
λ4
x1
λ1
x3
λ3
x2
λ2
(d)
20
A
0
B
0
A
1
B
1
C
n
-1
C
n
A
n
-1
B
n
-1
S
n
-1
FA
C
1
FA
S
0
Figu e 2.
C
0
FA
S
1
Figu e 3.
Vbias2
S
i
Vbias1
Vbias1
Vbias1
C
i+1
e al. hold ese wai
e al. hold ese
V
bias
1
V
bias
2
wai
[111;2] [1-11;1]
[111;3]
[111;1]
(c)
(d)
[1,1,1;2]
C
i+
1
[1,-1,1;1]
FA
[1,1,1;3]
[1,1,1;1]
S
i
(a)
n2
(Ai + Bi + Ci)n1n2= Ci + 1 n3n1
−
n2 + n3Si
000000
110011
211000
311111
(b)
C
i
A
i
B
i
AiBiCi
AiBiCi
AiBiCi
n1
n3

22
Figu e 4.
(a)
(b)
DEP
ENH
ENH
DEP
ENH
ENH DEP
DEP
23
Figu e 5.
24
Figu e 6.
(a)
[-1,-1,-1;-1]
C’
i
+ 1
[1,- 1, 1;1]
FA
[-1,-1,-1;0]
[-1,-1,-1;-2]
S’
i
C
i
Vbias2
Vbias1
AiBiCi
[-1-1-1;-1]
[1-11;1]
[-1-1-1;0]
[-1-1-1;-2]
(b)
Vbias1
Vbias1
(
−
Ai
−
Bi
−
Ci)n-2 n-1 = C’i + 1n0n-2
−
n-1 + n0S’i
01 111 1
−
11 100 0
−
21 001 1
−
30 000 0
A
i
B
i
AiBiCi
AiBiCi
C’i + 1
S’i
(c)
n-1
n-2
n0
Ai
25
Figu e 7.
Vbias1
Vbias1
Vbias2
[-1-1-1;-1]
(b)
Vbias1
[1 1;1 2] [1 1;1 2]
[-1; 0]
[-1,-1,-1;-1]
C’
i
+ 1
[1, 1;1, 2]
FA
[-1;0]
[1 ,1;1,2]
S’
i
C
i
A
i
B
i
AiBi
AiBiCi
AiBi
Ci
C’i
+ 1
S’i
(a)