Improved nanopipelined RTD adder using generalized threshold gates

1 Improved Nanopipelined RTD Adders using Generalized Threshold Gates AUTHORS: Hector Pettenghi1, María J. Avedillo*1,2, José M. Quintana1,2 AFFILIATION: 1 Instituto de Microelectrónica de Sevilla. Centro Nacional de Microelectrónica. CSIC 2 Dpto. de Electrónica y Electromagnetismo. Universidad de Sevilla. POSTAL ADDRESS FOR CORRESPONDENCE: Avda. Americo Vespucio 49 Telephone No. (34) 954 466666 FAX No. (34) 95 4466600 Sevilla 41092 SPAIN ABSTRACT1 Many logic circuit applications of Resonant Tunneling Diodes are based on the MOnostable- BIstable Logic Element (MOBILE). Threshold logic is a computational model widely used in the design of MOBILE circuits, i.e. these circuits are built from threshold gates (TGs). This paper describes the design of full adders (FAs) using TG based circuit topologies. Both the selection of different MOBILE TG networks and the use of gates that can be considered extensions of the MOBILE TG are addressed. The FAs are applied to the design of nanopipelined carry propagations adders which are evaluated and compared to a previously reported one, showing advantages in terms of speed, power and power delay product. Keywords: Resonant Tunneling Diodes, MOBILE, Threshold gate, nanopipelining, adder *. Corresponding authors 2 I. INTRODUCTION Resonant tunneling devices (RTDs) are nowadays considered the most mature type of quantum-effect devices. They are already operating at room temperature and they exhibit very attractive characteristics as high-speed operation and low power consumption. RTDs are very fast non linear circuit elements which have been integrated with transistors to create novel quantum devices and circuits. This incorporation of tunnel diodes into transistor technologies has shown an improved circuit performance: higher circuit speed, reduced component count, and/or lowered power consumption [1], [2], [19], [20]. Most of the reported working circuits have been fabricated in III/V materials while Si-based tunnelling diodes compatible to standard CMOS fabs are currently an area of active research [5]. RTDs exhibit a negative differential resistance (NDR) region in their current-voltage characteristics (Figure 1a) which can be exploited to significantly increase the functionality implemented by a single gate in comparison to conventional MOS and bipolar technologies, thus reducing circuit complexity. Figure 1a depicts the circuit symbol used for RTDs and their typical I-V curve showing key parameters for circuit design: peak current and voltage, Ip and Vp, and valley current and voltage, Iv and Vv. Many RTD based logic blocks rely on using the clocked series connection of a pair of RTDs or Monostable Bistable Logic Element (MOBILE) [6] which operates on the basis of the comparison of peak currents (Figure 1b). In general, MOBILE logic families combine the basic pair of series-connected RTDs with different three terminal devices to achieve input-output isolation and functionality (Figure 1c). Inherent self-latching property of MOBILE allows the implementation of pipeline at the gate level. The operating principle of MOBILE is extremely well suited to implement the arithmetic operation on which Threshold Gates [7] (TGs) are based [8], [9]. TGs are a generalization of conventional Boolean gates, which are able to implement more complex functions, what is attractive from the point of logic design (less gates and interconnec- 3 tions). TG design style is a well recognized powerful alternative to the standard logic design because of the intrinsic complexity of the functions performed by TGs allowing realizations that require less threshold gates than standard threshold logic. MOBILE TGs have been experimentally demonstrated and it has been reported the logic architecture of a nanopipelined carry propagation adder using them [10]. Currently research on circuit topologies using RTDs and transistors is an active area. Different generalizations of threshold gates, also suitable to be realized with MOBILE RTD structures which further increase the functionality of conventional TGs, are being investigated [11], [12], [13], [14]. Comparatively, less effort is dedicated to the evaluation and comparison of these building blocks within networks implementing logic applications. As in conventional design, different gate networks realizing same functionality exhibit different power and delay performance, even using the same logic style for the gates. Fan-in and fan-out capabilities of the building blocks are critical and their electrical behaviour can make a logic solution better than others. However, little attention is given to this in the literature. This work explores threshold-gate based MOBILE logic styles with this focus and their usage in the design of nanopipelined adders that significantly improve speed and reduce power-delay product with respect to the previously reported one [10]. The rest of the paper is organized as follows. Section II introduces both the electrical and the logical background of this work. Section III describes the design and characterization of MOBILE TGs implementations as a motivation for the proposed full adders introduced in Section IV. Architectures of 8-bit adders using them are described, simulated and compared in Section V. Finally, Section VI gives some conclusions. II. BACKGROUND 4 In this section the operation principle of clocked series-connected RTDs (MOBILE) is summarized. Then, the threshold gate is formally defined and its MOBILE implementation described. Finally, the previously reported RTD based adder which serves as a reference is introduced. A. MOBILE operating principle The MOBILE (Figure 1b) [6] is a rising edge triggered current controlled gate which consists of two RTDs connected in series and driven by a switching bias voltage . When is low, both RTDs are in the on-state (or low resistance state) and the circuit is monostable. Increasing to an appropriate maximum value ensures that only the device with the lowest peak current switches (quenches) from the on-state to the off-state (or high resistance state). Output is high if the driver RTD is the one which switches and it is low if the load switches. Assuming equal current densities for both RTDs, peak currents are proportional to RTD areas, and , for load and driver respectively. Thus, for the load switches (the output goes to low or “0”) and if otherwise, , the driver switches (the output goes to high or “1”). Logic functionality can be achieved if the peak current of one of the RTDs is controlled by an input. In the configuration for an inverter MOBILE shown in Figure 1c, the peak current of the driver RTD can be modulated using the external input signal . During a critical period when rises, the voltage at the output node goes to one of the two stable states (low or high), corresponding to “0” and “1” in binary logic. RTD areas are selected in such a way that the value of the output depends on whether the external input signal is “1” or “0”. Constraints on relationships among RTD areas for inverter functionality are depicted also in Vbias () Vbias Vbias λA λB λAλB < Vout λBλA < Vout Vin Vbias Vout Vin 5 Figure 1c. These constraints assume that the transistor behaves like an ideal switch. That is, for high, the transistor does not limit the RTD current and its peak current, which is proportional to , adds to the one of the driver in the non functional branch, . For high, the output node maintains its value even if the input changes. That is, this circuit structure is self-latching allowing to implement pipelining at the gate level without any area overhead associated to the addition of the latches which allows very high through-output. This circuit topology can be easily extended to systematically implement TGs which have been experimentally shown [8], [10]. A sufficiently slow Vbias rising is required for MOBILE operation. That is, there is a critical rise time for the switching bias below which the gate does not operate correctly and this determines its operating frequency. Under that critical time rise time, there is at least one input combination for which the gate does not produce the expected logic output. It is due to AC currents associated to parasitics (more important for faster bias changes) that somewhat “alter” the ideal MOBILE operating principle based on peak currents comparison. This critical value depends on both circuit (size of RTDs and transistors) and technological parameters [15], [16]. B. MOBILE TGs Threshold logic has been pointed out as an efficient computational model for the design of RTD based circuits. That is, the basic building blocks for RTD logic circuits are threshold gates instead of the conventional Boolean gates (AND, OR,...). A TG or linear separable function is defined as a logic gate with n binary input variables, , one binary output , and for which there is a set of real numbers: threshold T and weights , such that its input-output relationship is defined as Vin λ1 λB Vbias xii1…n,,=(), y n1+() w1w2…wn ,,, 6 iff , and otherwise. Sum and product are the conventional, rather than the logical, operations. The set of weights and threshold can be denoted in a more compact vector notation way by . Figure 1d shows the implementation of a generic TG defined as y = 1 iff , and 0 otherwise. The RTD areas determine the weights wi (i = 1, …, 4) and the threshold T. Input stages controlled by external inputs are placed in parallel to RTD1 or RTD2 depending on whether the associated weight is positive or negative, allowing the control of the peak currents of both NDRs. C Reference nanopipelined TG-based adder Figure 2 shows the logic diagram of the nanopipelined carry propagation adder proposed in [10]. It consists of a chain of full adders (FAs) and memory elements (MOBILE buffers and inverters) to support pipeline. Only those associated with inputs are depicted. Each FA is realized with a network of MOBILE TGs as depicted in Figure 3. The FA takes three binary inputs and generates the carry output, which is one if two or more inputs are logic ones (majority function), and the sum output, realized by an EXOR logic operation. In the proposed realization, the carry operation is implemented by a single gate due to the fact that the majority function is the threshold function [1, 1, 1; 2]. When the weighted sum of inputs is equal or greater than 2, the output is logic 1, since all weights are 1, two or three inputs at one produce a high output. However, the sum operation requires the implementation of a three-input EXOR. This is a non threshold function and thus requires a network of TGs. The four gate network used and showed in Figure 3a is based on a general technique to implement symmetric functions [7]. It is important to realize that it contains the three-input majority gate as is shown. Thus, the carry output can be extracted from the EXOR network directly. y1= wixi i1= n ∑T≥ y0= w1w2…wn;T,,,[] w1x1w2x2w3x3w4x4 ––+ T≥ 7 Table in Figure 3b shows that the outputs of the first level TGs codify the number of ones in the inputs: n1 is 1 if there is at least one input at one, n2 is 1 if there are at least two ones and n3 is one if all the three inputs are 1. Output of gate [1, -1, 1; 1] generates the 3-EXOR. Circuit schematic is shown in Figure 3c. Bias signals to operate cascaded MOBILE-type circuits [10] are also shown (Figure 3d). A four phase (evaluation, hold, reset and wait) overlapping clocking scheme is used. Second stage evaluates (rising edge of Vbias2) while the first stage is in the hold phase (Vbias1 high). For a number of logic levels greater than three, four bias signals are required. In one clock period all the gates are activated. Data can be processed at a frequency given by where is the minimum rise time that produces a correct behavior in all gates of a network. Otherwise, the latency time, , is given by the number of levels of the network: for a network of k levels . III. MOBILE THRESHOLD GATE IMPLEMENTATIONS This Section describes some experiments of characterization of MOBILE TG implementations which provide support for both the design methodology followed in the implementation of the adders, and for the new concepts on which the proposed adders rely on, as it will be clarified later. As it was previously stated, the minimum value for the rise time of the bias signal for which a MOBILE gate operates correctly depends on both design parameters, like RTD areas and transistor dimensions, and technological parameters. We have carried out extensive simulation and analysis of MOBILE gates in order to derive design guidelines to optimize their performance and to determine which TGs exhibit better performance. MOBILE TGs with different fan-in have been designed and evaluated using a non commercial university InP technology in which RTD and HFET transistors can be co-integrated. For this RTD, Vp is 0.21V, the peak current density 21KA/cm2, the peak to valley current ratio is about 6.25 fmax 14trcrit() ⋅()⁄= trcrit() tlat tlat kt r ⋅= 8 at room temperature and the capacitance is 4fF/μm2. The transistor threshold voltage is for the depletion HFET and for the enhancement one. Minimum gate-length is 0.6μ and transconductance parameter 500 μ A/V2 (depletion type) and 900 μ A/V2 (enhancement type). Gate design implies sizing of RTDs and transistor. As in the simple inverter gate (Figure 1c), target logic functionality imposes a set of constraints on RTD area relationships which must be fulfilled and which can be used to select RTD sizes. However, the solution to this set of inequalities is not unique. Circuit performance in terms of operating frequency and power depends on the selected RTD areas as it is shown in the following. Transistor sizing also determines correct operation and circuit performance. First, the simplest TGs, the inverter (Figure 1c) and the follower (input branch in parallel to load RTD), have been evaluated through HSPICE simulations using experimentally validated models for the RTDs and the transistors. Figure 4 depicts operating frequency and PDP (power/ frequency) as a function of transistor width. Minimum gate-length transistors have been used. The sizes of the RTDs have been selected solving the design constraint using as cost function to minimize the sum of the RTD areas and technological constraints on minimum sizes. High and low voltage values for clocked Vbias and Vin are 0V and 0.7V respectively. Results for both depletion and enhancement transistors are shown. It can be clearly observed that the enhancement transistor is better for the inverter and the depletion one for the follower. In addition, an analysis of the operation frequency shows that a large enough transistor is required to supply the required current of the RTD associated with each specific input branch, but it exists an optimal transistor width over which operating frequency starts to decline. Although a larger transistor in the input branch leads an NDR characteristic closer to an ideal one, which explains the initial increment of the frequency, it involves higher parasitic capacities that are responsible for its reduction. Similar experiments carried out with more complex TGs also indicate that for branches in parallel to load (driver) RTD depletion (enhancement) HFETs are preferable for 0.2V– 0.2 V 9 operating frequency and power-delay product, as well as the existence of an optimal transistor width. Figure 5 depicts operating frequency and power for different RTD sizings of an inverter. They have been obtained adding a term δ to the left hand side of the design inequalities in Figure 1c, and solving for different values of this parameter with the cost function previously described. While increasing δ, the operating frequency improves, although more significantly for lower δ values. However, solutions with larger δ imply larger RTD areas and the power consumption increases. Second, experiments increasing the fan-in have been carried out. TGs with positive unitary weights and TGs with negative unitary weights with identical loads have been characterized. In each case, the threshold value resulting in the slowest implementation has been selected. Table I summarizes frequency results. It can be clearly observed that gates with negative weights operate at higher frequencies than their positive counterparts. This is due to the fact that positive weights are implemented by input branches in parallel to upper RTD, and so their transistors have a gate to source voltage which is reduced while evaluation takes places (unlike transistors in branches in parallel to bottom RTD). When bias signal starts to rise, MOBILE structures behave like a resistive voltage divisor and the output node voltage increases. This translates in that the transistors associated with upper branches are larger than those in bottom ones. In the case of the non-commercial InP technology that we have used, this is true even if depletion transistors are used for upper branches and enhancement devices for bottom ones to compensate (as we have done). Larger transistors mean higher intrinsic parasitic capacitances and loads for previous stages. The experiment suggests that negative weights are preferable. This information might be exploited at the logic level to derive logic networks with better performance. This has been done in the first proposed FA in next Section. 16 the design of 8-bit nanopipelined carry propagation adders and compared to a previously reported one, based on TGs. All of them have been implemented with the same technology and following an identical methodology. The three proposed adders exhibit better frequency and less PDP than the previously reported one. Even if only TGs are used benefits are obtained from the alternative logic diagram implementing the FA. The GTG adder has shown the best performance in terms of speed and power consumption in comparison with TG and MTTG ones. Nanopipelined architectures for multipliers and divisors recently reported [18] can take advantage of these advanced proposed adders. Acknowledgements This effort was supported by the Spanish Government under project TEC2007-67245 and Andalusian Government through project EXC/2007/TIC-2961. REFERENCES [1] Chen, K.J., K. Maezawa, K., Waho, T., and Yamamoto, M., "Device technology for monolithic integration of InP-based resonant tunneling diodes and HEMT’s". IEICE Trans. on Electron., vol. 79-C, no.11, pp. 1515-1524, 1996. [2] Mazumder, P., Kulkarni, S., Bhattacharya, M., Jian Ping S., Haddad, G.I.,"Digital circuit applications of resonant tunneling devices". Proc. of the IEEE, vol. 86, no. 4, pp. 664-686, 1998. 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CAPTIONS TO THE FIGURES Figure 1.- MOBILE circuits. a) RTD I-V characteristic. b) Basic MOBILE. c) MOBILE inverter. d) MOBILE TG. Figure 2.- Logic diagram of pipelined n-bit carry propagation adder. Figure 3.- Reference TG FA. a) Logic diagram. b) Logic behaviour. c) Circuit structure. d) Bias scheme for MOBILE circuits. Figure 4.- Operating frequency and PDP as a function of transistor width. a) MOBILE follower. b) MOBILE inverter. Figure 5.- Operating frequency and power consumption as a function of δ for a MOBILE inverter. Figure 6.- Proposed TG FA . (a) Logic diagram. (b) Logic behaviour. (c) Circuit structure. Figure 7.- Proposed MTTG FA. (a) Logic diagram. (b) Circuit structure. Figure 8.- Circuit structure for generic n-input GTG. Figure 9.- Proposed GTG FA. (a) Logic diagram. (b) Circuit structure. Table I .- Operating Frequency of TGs Table II .- Comparison among 8-bit adders 19 Figure 1. Load Driver Vbias Vout (b) -1 -0.5 0.5 1 -2 -1 1 2 Vin Vout NDRA NDRB Vbias (c) λB λA λ1 λB λA λBλA < λAλBλ1 +< λ peak current current valley peak voltage V RTD (V) I RTD (mA) V RTD (V) + − (a) x4 y Vbias λB λA λ4 x1 λ1 x3 λ3 x2 λ2 (d) 20 A 0 B 0 A 1 B 1 C n -1 C n A n -1 B n -1 S n -1 FA C 1 FA S 0 Figure 2. C 0 FA S 1 Figure 3. Vbias2 S i Vbias1 Vbias1 Vbias1 C i+1 eval. hold reset wait eval. hold reset V bias 1 V bias 2 wait [111;2] [1-11;1] [111;3] [111;1] (c) (d) [1,1,1;2] C i+ 1 [1,-1,1;1] FA [1,1,1;3] [1,1,1;1] S i (a) n2 (Ai + Bi + Ci)n1n2= Ci + 1 n3n1 − n2 + n3Si 000000 110011 211000 311111 (b) C i A i B i AiBiCi AiBiCi AiBiCi n1 n3 22 Figure 4. (a) (b) DEP ENH ENH DEP ENH ENH DEP DEP 23 Figure 5. 24 Figure 6. (a) [-1,-1,-1;-1] C’ i + 1 [1,- 1, 1;1] FA [-1,-1,-1;0] [-1,-1,-1;-2] S’ i C i Vbias2 Vbias1 AiBiCi [-1-1-1;-1] [1-11;1] [-1-1-1;0] [-1-1-1;-2] (b) Vbias1 Vbias1 ( − Ai − Bi − Ci)n-2 n-1 = C’i + 1n0n-2 − n-1 + n0S’i 01 111 1 − 11 100 0 − 21 001 1 − 30 000 0 A i B i AiBiCi AiBiCi C’i + 1 S’i (c) n-1 n-2 n0 Ai 25 Figure 7. Vbias1 Vbias1 Vbias2 [-1-1-1;-1] (b) Vbias1 [1 1;1 2] [1 1;1 2] [-1; 0] [-1,-1,-1;-1] C’ i + 1 [1, 1;1, 2] FA [-1;0] [1 ,1;1,2] S’ i C i A i B i AiBi AiBiCi AiBi Ci C’i + 1 S’i (a)