Global Design o Analog Cells using S a is ical Op imiza ion Techniques 2
Global Design o Analog Cells using S a is ical Op imiza-
ion Techniques
F. Medei o, R. Rod íguez-Macías, F.V. Fe nández, R. Domínguez-Cas o, J.L. Hue as
and A. Rod íguez-Vázquez
Dep . o Analog Ci cui Design,
Cen o Nacional de Mic oelec ónica,
Edi icio CNM, A da. Reina Me cedes sn.
41012-Se illa, SPAIN
FAX #34 5 4624506, Phone #34 5 4239923
email [email p o ec ed]
Abs ac
We p esen a me hodology o au oma ed sizing o analog cells using s a is ical op imi-
za ion in a simula ion based app oach. This me hodology enables o design complex analog
cells om sc a ch wi hin easonable CPU ime. Th ee di e en speci ica ion ypes a e co e ed:
s ong cons ain s on he elec ical pe o mance o he cells, weak cons ain s on his pe o -
mance, and design objec i es. A ma hema ical cos unc ion is p oposed and a bunch o heu is-
ics is gi en o inc ease accu acy and educe CPU ime o minimize he cos unc ion. A
echnique is also p esen ed o yield designs wi h educed a iabili y in he pe o mance pa am-
e e s, unde andom a ia ions o he ansis o echnological pa ame e s. Se e al CMOS ana-
log cells wi h complexi y le els up o 48 ansis o s a e designed o illus a ion. Measu emen s
om ab ica ed p o o ypes demons a e he sui abili y o he p oposed me hodology.
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 3
Global Design o Analog Cells using S a is ical Op imiza-
ion Techniques
F. Medei o, R. Rod íguez-Macías, F.V. Fe nández, R. Domínguez-Cas o, J.L. Hue as
and A. Rod íguez-Vázquez
Dep . o Analog Ci cui Design,
Cen o Nacional de Mic oelec ónica,
Edi icio CNM, A da. Reina Me cedes sn.
41012-Se illa, SPAIN
FAX #34 5 4624506, Phone #34 5 4239923
email [email p o ec ed]
1. In oduc ion
The design o analog VLSI building blocks, and in gene al he design o any in eg a ed
ci cui , comp ises h ee majo s eps. Fi s , a sui able schema ic mus be selec ed. Then his
schema ic mus be sized o comply equi ed pe o mance speci ica ions on gain, bandwid h,
slew- a e, e c., as well as o mee design objec i es ega ding a ea, powe consump ion, e c.
Finally, a layou mus be gene a ed o he sized schema ics. O hese h ee majo s eps, his
pape ocuses on he p oblem o analog sizing.
Analog sizing is a e y complica ed, ime-consuming ask whose au oma ion has d awn
s ong a en ion in ecen yea s, whe e se e al ools and me hodologies ha e e ol ed [1]-[8].
Two basic easons lie behind hese de elopmen s: a) ma ke p essu e o educe he design cos
o he analog componen s o mode n analog-digi al ASICs and b) he need o cus om analog
design o be a ailable o ASIC sys em designe s.
Mos p e iously epo ed app oaches o au oma ed analog cell design a e closed sys ems
co e ing only a limi ed numbe ( hough no necessa ily small, see o ins ance [1]) o schema -
ics. Some ools wo k on a la schema ic lib a y whe e opologies a e de ined a he de ice-le el
[1], [6], [8], [9]. In o he s [3], [5], [7], [10] a chi ec u es a e de ined a he concep ual le el as
a connec ion o sub-blocks (di e en ial pai s, cu en mi o s, e c.), each o which can be
expanded hie a chically down o he de ice-le el. Tools also di e among hemsel es depend-
ing on he sizing s a egy used. In some app oaches, he sizing p ocess is educed o a con-
s ained op imiza ion p oblem [6],[8]; in o he s, sizing is pe o med by ollowing speci ic
design plans o each opology, p e iously de eloped by expe designe s and s o ed in he ool
da abase [1], [3], [5], [7], [10].
Closed sizing sys ems a e all equa ion-based; ha is, he knowledge abou he a ailable
opologies is p o ided as analy ical design equa ions. The associa ed design equa ions o new
opologies mus be gene a ed -- a ask o only eal analog design expe s o ackle. Ano he
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 4
d awback ela ing o closed sys ems is ha hey do no allow he explo a ion o opology
enhancemen s as concei ed by designe s wi h some expe ise.
Some o he d awbacks o closed sys ems a e o e come by he app oaches in [9],[11],
which a e also equa ion based. The dis inc i e ea u e is ha some o he design equa ions o
new opologies a e au oma ically gene a ed ia auxilia y symbolic analysis ools [9],[12].
Expe concou se is no u he equi ed o ha end. Un o una ely, symbolic analysis ools p o-
ide equa ions o nei he DC no la ge signal ansien cha ac e is ics, whose associa ed
design equa ions mus s ill be manually p o ided. Hence, he me hodology is only pa ially
open. Fu he mo e, he le el o complexi y o AC au oma ic modeling is limi ed by he capa-
bili ies o symbolic analysis ools (cu en ly, abou 15 MOS ansis o s using high- equency
MOST models and wo ks a ion s anda d con igu a ions). Consequen ly, his app oach is no
he mos sui able o he au oma ed sizing o complex analog building blocks ( o ins ance,
ully-di e en ial opamps), o o applica ions whe e la ge signal speci ica ions play a majo
ole, o ins ance, o e sampled modula o s o high esolu ion A/D con e e s [13].
Whe he closed o open, equa ion-based sys ems ha e a common d awback in ha sizing
is ca ied ou using simpli ied analy ical desc ip ions o he blocks. Hence, manual ine- uning
using an elec ical simula o and de ailed MOS ansis o models may be necessa y once ough
au oma ed sizing is comple ed. This d awback is o e come in he so-called simula ion-based
sys ems [14], which also educe sizing o a cons ained op imiza ion p oblem, and aim o sol e
i by ollowing an i e a i e p ocedu e buil a ound an elec ical simula o . No design equa ions
a e equi ed in hese app oaches; he design pa ame e s a e upda ed a each i e a ion based on
he esul s p o ided by simula ions wi h de ailed ansis o models. Thus, hey a e in insically
open. A ep esen a i e example o his me hodology is DELIGHT.SPICE [14] whe e
DELIGHT (a gene al algo i hmic op imiza ion ool) and SPICE a e combined. Also, ad anced
elec ical simula o s, like HSPICE [15], inco po a e op imiza ion ou ines. Howe e , he op i-
miza ion ou ines in bo h ools sea ch o a local solu ion, and consequen ly a e ypically used
o edesign cells whose pe o mance speci ica ions a e close o he design goals ( o ins ance,
echnology upda ing o a cell lib a y), bu a e inapp op ia e o size analog cells om sc a ch.
This is a eal challenge in analog design au oma ion and equi es he de elopmen o o he ech-
niques.
This pape p esen s a simula ion based app oach o global sizing o a bi a y opology
analog cells using s a is ical op imiza ion. We demons a e ha by combining p ope cos unc-
ion o mula ion and inno a i e op imiza ion heu is ics complex cells a e designed s a ing
om a bi a y ini ial poin s, wi hin easonable CPU imes and wi h no designe in e ac ion
equi ed -- a e y appealing ea u e o ASIC applica ions. We p esen esul s ob ained o wo
ully-di e en ial CMOS opamps, a compa a o and an analog ou pu bu e , which we e sized
using he p oposed me hodology, ab ica ed in di e en CMOS echnologies, and whose pe -
o mance was co obo a ed om ac ual silicon p o o ypes. The p oposed echnique is also
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 5
ex ended o design o low a iabili y inco po a ing misma ching in o ma ion in he design
p ocedu e. This is illus a ed in he design o a CMOS olded-cascode ope a ional ampli ie .
2. Some Gene ali ies on Op imiza ion-Based Sizing
Analog sizing is a cons uc i e p ocedu e o map cell speci ica ions in o design pa ame-
e alues. Design speci ica ions a e gi en a b oad meaning he e which includes cons ain s on
he elec ical pe o mance pa ame e s o he cell as well as design objec i es. Le us conside
o illus a ion pu poses he ou pu bu e o Fig.1, one o he examples co e ed in his pape .
A possible speci ica ion se o his ci cui could include cons ain s on i s DC gain (Ao > a -
ge ), inpu capaci ance (Cin < a ge ), 3-dB equency ( 3dB > a ge ), and ou pu ol age ange
( a ge < OS < a ge ), in addi ion o he design objec i e o minimum possible powe consump-
ion. Wi h ega ds o he design pa ame e s, hese include ansis o dimensions and passi e
componen alues.
In a gene ic ci cui , he design pa ame e s can be iewed as componen s o a ec o xT =
{x1, x2, . . . xN} de ining a mul idimensional design space. Thus, pe o mance pa ame e s and
he ea u es in ol ed in design objec i es a e gi en as unc ions o x; e e ing again o he
example o Fig.1: Ao(x), Cin(x), 3dB(x), OS(x),and Powe (x). Then he p oblem o sizing is o -
mula ed as a cons ained op imiza ion p oblem; in pa icula , o he case o he bu e o Fig.1,
(1)
Un o una ely, e en o elemen a y analog cells like ha shown in Fig.1, he analy ical solu ion
in
o
M1M2
M3M4
M5
M6M7
M8
Figu e 1: A CMOS ou pu bu e .
Cc
IB
subjec ed o
minimize Powe x()
Aox() a ge >
Cin x() a ge <
3dB x() a ge >
a ge OS x() a ge <<
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 6
o he sizing p oblem is no possible due, among o he ac o s, o he ollowing:
•Design equa ions, i.e., unc ional ela ionships among pe o mance pa ame e s and
design objec i es on one hand, and design pa ame e s on he o he , a e e y di icul
o ob ain accu a ely.
•These ela ionships a e ypically highly nonlinea and, consequen ly, unsol able ana-
ly ically. A u he complica ion a ises due o he la ge dimensions o he design and
he speci ica ion spaces.
•The need o minimize some unc ions o ces he calcula ion o i s and second de i -
a i es and hence, in oduces addi ional complica ions o he analy ical solu ion p o-
cess.
Due o hese di icul ies, analog ci cui s a e mos con enien ly sized by using ani e a i e,
dynamic p ocess. This concep is illus a ed in Fig.2: s a ing om an ini ial design pa ame e
es ima e, x0, a disc e e sequence o mo emen s ( ep esen ed gene ically as ∆xn) is pe o med
Figu e 2: I e a i e analog cell sizing: (a) Gene al concep . (b) Manual and au oma ed
design upda ing managemen .
UNSIZED
SPECIFICATIONS
ELECTRICAL SIMULATION
PERFORMANCE
EVALUATION
GOALS UPDATE
PARAMETERS
NEW MOV. ∆xn
SCHEMATIC
INITIAL DESIGN
PARAMETER ESTIMATE x0
ACHIEVED?
YES NO
Design P ocess Managemen
END
xnxn1– ∆xn1–
+=
COST FUNCTION
EVALUATION Φ(x)
FIGURES OF MERIT
EVALUATION
ELECTRICAL SIMULATION
PARAMETER UPDATING
manual managemen au oma ed managemen
(a)
(b)

Global Design o Analog Cells using S a is ical Op imiza ion Techniques 7
h ough he design pa ame e space un il an equilib ium solu ion poin x*is ound.
A key componen o his i e a i e loop is p ocess managemen : he calcula ion o he
di ec ion and magni ude o he mo emen ∆xn o be made a each i e a ion. In manual design,
∆xn is chosen by he designe based on his/he knowledge o he ci cui s uc u e being sized -
- a di icul and ime-consuming ask e en o expe ienced analog designe s. In au oma ed
design, he selec ion o ∆xn mus be pe o med by he compu e based on he e alua ion o
some c i ical ci cui pe o mance indica o s. A con enien app oach o do his is o ecas he
p oblem o mula ion as a cos unc ion Φ(x) which quan i ies he deg ee o achie emen o he
design goals and hei ela ion o he design pa ame e s. Thus, he pa ame e upda ing o be
done o he subsequen i e a ion ∆xn is selec ed a each i e a ion using unc ional analysis da a
o Φ(x). This app oach also p o ides simple and accu a e c i e ia o inish he sizing p ocess a
poin s whe e he cos unc ion is ei he maximized o minimized.
In he simples case, ∆xn is calcula ed by using pieces o in o ma ion calcula ed only a
xn. Howe e , as demons a ed in his pape , he use o addi ional in o ma ion om p e ious
poin s, a ime ins ances n−1, n−2, e c., may p oduce mo e obus solu ions o he sizing p ob-
lem, in he sense o yielding cells whose speci ica ions ha e lowe a iabili y when s a is ical
a ia ions o he echnological pa ame e s a e aken in o accoun . In his mo e gene al case, he
upda ing p ocess is desc ibed as a high-o de nonlinea disc e e- ime sys em,
(2)
As s a ed in he in oduc ion, we will assume ha pe o mance e alua ions in Fig.2
(equi alen ly, he calcula ion o pe o mance speci ica ion alues and he alues o he ea u es
in ol ed in he design equa ions as unc ions o x) a e made using elec ical simula ion and
de ailed ansis o models o gua an ee accu acy o he sizing p ocess. Many di e en al e na-
i e implemen a ions o Fig.2 a e possible depending on: a) o mula ion o he cos unc ion
i sel , b) he upda ing p ocedu e. Two majo al e na i es can be oughly iden i ied, depending
o he unc ional s uc u e o S[•] in (2):
•De e minis ic, inc emen al echniques whe e ∆xncalcula ion uses in o ma ion abou
he de i a i es o he cos unc ion. This is an impo an d awback since analy ical
exp essions o he cos unc ion and i s de i a i es as unc ions o he design pa am-
e e s a e no commonly a ailable, so ha he de i a i es mus be calcula ed by nume -
ical in e pola ion. Ano he majo d awback is ha only ∆xn alues which lowe he
cos unc ion a e conside ed. Hence, he op imiza ion p ocess is easily apped in local
minima, ende ing i e y sui able only o ine adjus men o he design.
•S a is ical echniques, whe e ∆xnis calcula ed a andom and hence, equi es no in o -
ma ion abou he cos unc ion de i a i es.
Pa ame e upda ing in de e minis ic echniques is done only in he di ec ion which lowe s
∆xnSΦx()xnxn1– xn2– …xnM–
,, , ,,[]=
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 8
he cos unc ion. This makes hem e y sensi i e o he s a ing poin and hence, inadequa e
o global ci cui sizing. This is o e come using s a is ical op imiza ion echniques whe e
mo emen s in he design space a e done heu is ically, ollowing s a is ical op imiza ion p inci-
ples [16]. The p ice o pay o an independen ini ial poin is a la ge numbe o i e a ions and
hence, longe CPU imes. Howe e , as shown he e, p ope o mula ion o he cos unc ion, he
mo emen gene a o , and he cooling schedule, adap ed o he na u e o analog syn hesis, pal-
lia es he high compu a ional cos and hus p o ides a con enien me hodology o global
design o analog cells.
3. Cos Func ion Fo mula ion
A i s s ep owa ds de ising a ool o au oma ed sizing o analog cells using s a is ical
op imiza ion is o o malize he se ing o pe o mance speci ica ions. In a mo e gene al case,
h ee di e en speci ica ion classes mus be conside ed:
•S ong es ic ions: These a e speci ica ions whose ul illmen is conside ed essen ial
by he designe ; o ins ance, he phase ma gin o an opamp mus be la ge han 0 (PM
> 0) o s abili y [17]. No elaxa ion o he speci ied alue is allowed. Hence, i any
se ing o he design pa ame e s (equi alen ly, any poin o he design pa ame e
space) does no sa is y one s ong es ic ion, i mus be ejec ed immedia ely.
•Weak es ic ions: These a e he ypical pe o mance speci ica ions equi ed o ana-
log building blocks, i.e. Ao > 80dB. Unlike s ong es ic ions, weak es ic ions allow
some elaxa ion o he a ge pa ame e s, making such ci cui sizings which do no
mee such speci ica ions accep able.
•Design objec i es: S a ed as he minimiza ion (maximiza ion educes o his case by
ei he changing he sign o using he in e se o he unc ion o maximize) o some pe -
o mance ea u es,
(3)
o ins ance, minimize −GB o an opamp (equi alen ly, maximize GB), whe e GB
deno es he gain-bandwid h p oduc ; o minimize he occupied a ea o he ci cui .
Ma hema ically, he ul illmen o hese speci ica ions can be o mula ed as a mul i-
objec i e cons ained op imiza ion p oblem,
(4)
whe e yΨi deno es he alue o he i- h design objec i e; ysj and ywk deno e alues o he ci cui
m
inimize yΨix() 1i
P
≤≤
m
i
n
i
m
i
ze yΨix
() 1iP≤≤
,
subjec ed o ysj x() Ysj o ysj x() Ysj
≤1jQ≤≤,≥
ywk x() Ywk o ywk x() Ywk
≤1,kR≤≤≥



Global Design o Analog Cells using S a is ical Op imiza ion Techniques 9
speci ica ions (subsc ip s s and w deno e s ong and weak speci ica ions espec i ely); and Ysj
and Ywk a e he co esponding a ge s ( o ins ance, Ao ≥ 80dB, se ling ime ≤ 0.1µs).
The cos unc ion is de ined in he minimax sense as ollows,
(5)
whe e he pa ial cos unc ions FΨ(•), Fsj(•), and Fwk(•) a e de ined as,
(6)
whe e wi (called weigh pa ame e s o he design objec i es) is a posi i e (al e na i ely nega-
i e) eal numbe i yΨi is posi i e (al e na i ely nega i e), and o Ksj(•) and Kwk(•) we ha e,
(7)
whe e kk (weigh pa ame e s assigned o weak es ic ions) is a posi i e (al e na i ely nega i e)
eal numbe i he weak speci ica ion is o ≥ (al e na i ely ≤) ype. Weigh pa ame e s a e used
o gi e p io i y o he associa ed design objec i es and weak speci ica ions. As shown in he
cos unc ion o mula ion, only ela i e magni ude o he weigh pa ame e s o he same ype
makes sense. In (7) weak speci ica ions a e assumed posi i e. Sign c i e ia is e e sed o neg-
a i e speci ica ions.
S ong es ic ions a e checked i s a each i e a ion. I any o hem a e no me , he co -
esponding mo emen mus be ejec ed. O he wise, weak es ic ions a e examined. Weak
es ic ions ha e p io i y o e design objec i es. I some weak es ic ion is no ul illed, he
cos unc ion is buil only wi h hei con ibu ion. Hence, i no ci cui sizing is able o co e all
weak speci ica ions, he op imiza ion p ocess will p o ide esul s as close as possible. Once all
o hem a e me , he design objec i es a e e alua ed and hei in luence in he cos unc ion
guides hei maximiza ion o minimiza ion.
4. Pa ame e Upda ing and P ocess Managemen
Fig.3 shows a block diag am illus a ing he ope a ion low in he p oposed me hodology.
The upda ing ec o , ∆xn, is andomly gene a ed a each i e a ion. The alue o he cos unc ion
is calcula ed a he new pa ame e space poin and compa ed o he p e ious one. The new poin
is accep ed i he cos unc ion has a lowe alue. Unlike de e minis ic echniques, i may also
be accep ed i he cos unc ion inc eases, acco ding o a p obabili y unc ion,
minimize Φx() max FΨyΨi
()Fsj ysj
()Fwk ywk
(),,{}=
FΨyΨi
() wiyΨi
()log
i
∑
–= Fsj ysj
()Ksj ysj Ysj
,()=,
Fwk ywk
() Kwk ywk Ywk
,()
ywk
Ywk
---------


log–=
Ksj ysj Ysj
,()
∞–
i
s ong es
i
c
i
on
h
o
ld
s,
∞o he wise,



=
Kwk ywk Ywk
,()
∞kk
()sgn i weak es ic ion holds,
k
k
o he wise,



=
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 10
(8)
depending on a con ol pa ame e , T. The andom cha ac e o mo emen s and he s a is ical
accep ance o hose which inc ease he cos unc ion enable escaping om local minima and
hence, wide explo a ion o he design space. This p obabili y o accep ance changes du ing he
op imiza ion p ocess, being high a he beginning ( o la ge T) and dec easing as he sys em
cools (dec easing T). This is he gene al concep lying behind simula ed annealing op imiza-
ion echniques -- a p ocess whose name is jus i ied by i s analogies o he physical annealing
in solids [16]. The ool p oposed he ein inco po a es new heu is ics ela ing o bo h pa ame e
upda ing and he cooling schedule i sel , as explained below.
4.1. Cooling Schedule
Cooling schedule e e s o he s a egy used o modi y he empe a u e while he p ocess
e ol es. Unlike classical simula ed annealing algo i hms [16], whe e T in (8) dec eases mono-
PP
oe
Φ∆
T
--------–
=
Figu e 3: Ope a ion low in he p oposed me hodology.
MOVEMENT
NEW
MOVEMENT
∆xn
INITIAL DESIGN
PARAMETER ESTIMATE x0
ACCEPTED?
YES NO
END
xnxn1– ∆xn1–
+=
COST FUNCTION
EVALUATION Φ(x)
(ELECTRICAL SIMULATION)
UPDATE TEMPERATURE SCALE
UPDATE MOVEMENT AMPLITUDE
xnxn1–
=
ACCEPT
MOVEMENT
STATISTICAL
ACCEPTANCE
P=P(∆Φ,T)
END
PROCESS?
∆Φ(x)?
NO
YES
> 0
< 0
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 17
cos ly in CPU ime and, consequen ly, no well sui ed o be used in o an i e a i e op imiza ion
loop. Since dispe sion o he ansis o pa ame e alues is in e sely p opo ional o he
de ice’s a ea, and o he dis ance among nominally iden ical de ices [21], a s a egy o educe
a iabili y o he cells is o pu addi ional cons ain s on he design a iables. Howe e , his
s a egy d as ically educes he sea ch space, limi ing he achie emen o demanding pe o -
mances. The heu is ics desc ibed below p o ides a mo e con enien app oach ha ake ad an-
age o he la ge amoun o da a gene a ed du ing he s a is ical op imiza ion p ocess. I
encompasses a modi ica ion o he cos unc ion s uc u e and a new compa ison me hodology,
in combina ion o he nonmono onic cooling schedule.
Fi s o all, design speci ica ions, and, hence, he cos unc ion is made o depend no only
on he ec o o design pa ame e s x, bu also on a ec o o ansis o model pa ame e s e.
These model pa ame e s change du ing he op imiza ion p ocess as a consequence o he
dependance o hei s a is ical a iabili y wi h de ice a ea and dis ances be ween de ices [21].
A each i e a ion, design pa ame e s a e upda ed acco ding o he heu is ics in Sec ion 4.2 and
de ice model pa ame e s a e changed acco ding o he s a is ical dis ibu ion o he echnolog-
ical independen pa ame e s [20]. In addi ion o enla ging he numbe o pa ame e s, a new
addend is inco po a ed o he cos unc ion o e alua e he sensi i i y o pe o mance speci ica-
ions o de ice model pa ame e a ia ions. Such addend is:
(15)
which inco po a es in o ma ion om he las M i e a ions, whe e M co esponds ypically o
he numbe o i e a ions pe o med in one cooling. Each addend in (15) con ains he a io o
he ela i e inc ease in he speci ica ions (ei he weak speci ica ions o design objec i es) o he
inc ease in he L de ice model pa ame e s wi h espec o p e ious i e a ion. The nume a o
e alua es ela i e a ia ions o he P pe o mance speci ica ions wi h espec o p e ious i e a-
ion due o a ia ions in he design pa ame e s x, and he de ice model pa ame e s e.
The ampli ude o design pa ame e a ia ions dec eases along each cooling. The e o e,
he a iabili y o pe o mance speci ica ions is e alua ed wi h highe p ecision as he op imi-
za ion p ocess e ol es. This ac is e lec ed in (15) by he weigh pa ame e w1, which is gi en
by:
(16)
whe e in an heu is ic pa ame e la ge han 1. Hence, w1 inc eases along a cooling, gi ing
mo e impo ance in (15) o he addends co esponding o he las i e a ions wi hin each cooling.
A simila weigh ing be ween di e en coolings is done wi h pa ame e w2, which is gi en
1
M
-----
yspecixnen
,()yspecixn1– en1–
,()–
yspecixnen
,()
---------------------------------------------------------------------------------
i1=
P
∑
ejn,ejn 1–,
–
j
1=
L
∑
-----------------------------------------------------------------------------------------------w1w2
⋅⋅







n1=
M
∑
w1 n
1
–
=

Global Design o Analog Cells using S a is ical Op imiza ion Techniques 18
by
(17)
whe e ’ is a heu is ically chosen cons an pa ame e which mus be smalle han 1 and l is he
o dinal o he cu en e-hea ing wi hin he cooling schedule.
The cos unc ion a some gi en i e a ion mus be compa ed wi h some p e ious i e a ion
in o de o accep o ejec he cu en design pa ame e mo emen . A new compa ison me h-
odology is in oduced adap ed o he new cos unc ion o mula ion. Each i e a ion in a gi en
cooling is compa ed wi h he i e a ion o equal o dinal om he bes o p e ious coolings, o
accep ance o ejec ion, ollowing he s a is ical op imiza ion p inciples o Sec ion 2. I
ejec ed, he design poin o he bes cooling is adop ed as new poin in he cu en i e a ion and
he op imiza ion p ocess con inues. Since (15) is added o he cos unc ion, he op imiza ion
p ocess ends o minimize i . Tha implies small speci ica ion inc eases in he las M i e a ions
and, hence, educed pe o mance s a is ical de ia ions.
A ma hema ical es unc ion has also been used he e, o p o e he me hod’s capabili y
and as a benchma k o heu is ics e inemen s. I s analy ical s u u e o a N-dimensional case
is,
(18)
The i s addend in (18), se s he mean alue o (•) and he second one c ea es a ia ions a ound
ha mean alue. S a is ical de ia ions a e simula ed a he hi d addend by means o a andom
a iable, h. The global minimum o dispe sion is loca ed in xmin. Sinusoidal a ia ions se local
dispe sion minima. A me hod o educe a iance will be accep able, i he inal solu ion is close
o xmin.
Fo a es example wi h eigh independen a iables comp ised in he in e al
xn∈[−0.7,0.7], a mean alue K=100 and sinusoidal a ia ions wi h an ampli ude K´=10, he
new heu is ics p o ides a solu ion o a dis ance o 1.75 om he global minimum, whe e s an-
da d de ia ion is σ= 0.25. A con en ional s a is ical op imiza ion echnique ends in dis ances
a ound 12 om xmin, whe e s anda d de ia ion is σ= 12.
6. P ac ical Resul s
P oposed echniques ha e been applied o a wide a ie y o analog building blocks.
Resul s a e shown o he design o wo ully-di e en ial opamps, a compa a o and an ou pu
bu e . Simula ed esul s and measu emen o silicon p o o ypes o he ci cui s demons a e he
easibili y o he app oach.
w2 'l1–
=
x() KK'2πxk
3
----------


sin h dis 2xx
min
,() 2πxk
6
----------


sin
k1=
N
∑
+



+
k1=
n
∑
+=
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 19
6.1. Fully Di e en ial Class-AB Opamp wi h Dynamic Biasing
Le us i s conside he ully di e en ial opamp o Fig.7 [22], in ended o a
16bi @16KHz second o de ∑∆ modula o . This class-AB opamp includes dynamic biasing o
he ou pu b anches o ob ain la ge ou pu swing and high slew- a e, and uses a dynamic com-
mon-mode eedback ne wo k. These ad anced ci cui s a egies, and he complexi y o he ci -
cui i sel (i con ains 48 ansis o s) ende s i s sizing a di icul ask, ha d o handle o sys em
le el designe s. Howe e , he he ein p oposed me hodology was able o au oma ically size he
ci cui o he in ended applica ion a e 1hou CPU ime on a 100mips spa cs a ion, s a ing
om sc a ch and wi h no designe in e ac ion equi ed. Table 2 shows he sizing ob ained.
The i s column in Table 1 con ains he design goals, which includes a design objec i e
on he powe consump ion and weak es ic ions on he gain-bandwid h p oduc (GBW), phase
ma gin (PM), inpu whi e noise and ou pu swing (OS). Fig.7 shows he e olu ion o he cos
unc ion du ing he op imiza ion p ocess. No e ha he e ical axis con ains wo egions, sep-
a a ed by a dashed line. The weak egion co esponds o he case whe e any o he weak es ic-
Table 1. Simula ed and measu ed esul s o he class-AB opamp.
Speci ica ions Simula ed Measu ed Uni s
A0≥ 70 74.9 74.6 dB
GBW ≥ 20 19.7 19.4 MHz
PM ≥ 60 63.3 65 o
Inpu whi e noise ≤ 50 44.7 - nV/√Hz
OS ≥7 8.0 8.2 V
O se - − 3.35 mV
Powe minimize 4.3 4.3 mW
M1M2
M3M4
M8
M6
M10
M9
M22 M26 M18
M30
M14
M20
M28
Mbias
Mbias
Mbias
M7
M5
Ibias
M21
M25
M17
M13
M29
M19
M23
M15
M31
M33
M35
M41
M43
M45
M47 M39
M37
C1C2
M42
M44
M34
M36
M38
M40 M48
M46
C1
C2
M16
M32
M24
M12
M11
M27
Vcm+
Vcm-
Vo+Vo-
V-V+
Figu e 7: Fully-di e en ial opamp.
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 20
ions is iola ed, while he objec i e egion co esponds o he case whe e all weak es ic ions
a e ul illed; inside his egion he op imiza ion p ocess ocuses on he design objec i es. No e
ha a good design (meaning one ha ul ills all he weak es ic ions) is ob ained a e 750 i e -
a ions. Simula ed esul s co esponding o he ob ained sizing a e shown in he second column
o Table 1.
Fig.9 is a mic opho og aph o a CMOS 1.2µm double poly n-well p o o ype o he ully
di e en ial opamp. Measu ed esul s om he silicon p o o ype a e also shown in Table 1. The
Table 2. Sizing o he opamp o Fig.7
M1,2 149.2 / 2.2 µmM
21,22 48.2 / 2.2 µm
M3,4 22.0 / 2.2 “ M23,24 42.8 / 2.2 “
M5,6 80.4 / 2.2 “ M25,26 6.2 / 2.2 “
M7,8 11.8 / 2.2 “ M27,28 5.4 / 2.2 “
M9,10 149.8 / 2.2 “ M29,30 78.8 / 2.2 “
M11,12 65 / 2.2 “ M31,32 34.2 / 2.2 “
M13,14 78.8 / 2.2 “ M33-48 5.0 / 1.2 “
M15,16 34.2 / 2.2 “ Mbias 378.0/ 5 “
M17,18 121.8 / 2.2 “ C1-4 0.4 pF
M19,20 142.8 / 2.2 “ Ibias 74 µA
0500 1000
# i e a ions
-0.5
0.5
1.5
2.5
3.5
Cos Func ion
Figu e 8: Cos unc ion e olu ion o he op imiza ion o Fig.7.
Weak Region
Objec i e
Region
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 21
Σ∆ modula o CMOS p o o ype, which was buil using his opamp, displayed a measu ed es-
olu ion o 15.7bi @16Khz.
6.2. Fully-Di e en ial Folded-Cascode Opamp
As a second example, le us conside he olded-cascode ully-di e en ial opamp o
Fig.10, which displays he sizes p o ided by he ool. These sizes we e ob ained o he speci-
ica ions needed in a 17bi @40KHz ou h o de ∑∆ modula o . The speci ica ions a e gi en in
he i s column o Table 3. Once again only he powe consump ion was a design objec i e.
The op imiza ion p ocess s a ed om sc a ch on a 10-dimension design space and equi ed
abou 45mins. o CPU ime on a 100mips spa cs a ion. Simula ion esul s o he sized ci cui
a e shown in he second column o Table 3. The opamp has been in eg a ed in a CMOS 1.2µm
double poly n-well echnology. Expe imen al esul s a e gi en in hi d column o Table 3. The
inal Σ∆ modula o p o o ype displayed 16.8bi @40Khz [23].
Table 3. Simula ed and measu ed esul s o he olded-cascode opamp.
Speci ica ions Simula ed Measu ed Uni s
A0≥ 70 78.52 76.01 dB
GBW (1pF) ≥ 30 34.88 - MHz
GBW(12pF,1MΩ) 4.17 4.21 MHz
PM(1pF) ≥ 60 66.28 - o
PM(12pF, 1ΜΩ) 87.2 86.8 o
Inpu whi e noise ≤ 12 13.53 - nV/√Hz
SR ≥ 70 74.81 70.5 V/µs
OS ≥±3±3.2 ±3.0 V
O se - − 3.35 mV
Powe minimize 1.95 1.93 mW
Figu e 9: Mic opho og aph o he ully-di e en ial opamp o Fig.7.
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 22
6.3. Regene a i e Compa a o
The compa a o used in he same 17bi ∑∆ modula o was designed using he high- e-
quency egene a i e la ch o Fig.11 o mee he speci ica ions o Table 4. The simula ed and
measu ed esul s o he sized schema ics p o ided by he design ool a e also shown in Table
4. As o he p e ious opamp, measu emen s co espond o a p o o ype buil in a CMOS 1.2µm
double poly n-well echnology. We ha e analyzed he o igin o he sligh de ia ions obse ed
in he measu ed esolu ion ime and ha e ound ha hey can be ully explained by aking in o
accoun he dynamics o he measu emen se -up.
6.4. High-F equency Analog Bu e
The analog bu e o Fig.1 was designed o e y low inpu capaci ance. The sizing
ob ained a e 30mins CPU ime is shown in Table 5. Table 6 shows he speci ica ions, whe e
he DC gain (A0), ou pu ange (OS), and powe consump ion a e design objec i es; he 3-dB
equency is a weak es ic ions, and he inpu capaci ance is included as a cons ained design
objec i e. As shown in he hi d column o Table 6 he ool was able o ob ain a solu ion wi h
inpu capaci ance as low as 0.07pF and 3dB o 34.35Mhz.
Table 4. Simula ed and measu ed esul s o he compa a o .
Speci ica ions Simula ed Measu ed Uni s
TPHL < 20 8.0 12.0 ns
TPLH < 20 10.0 14.0 ns
Resolu ion < 60 40 36.4 mV
O se - 77 22.5 mV
183.6/9.4
61.8/3
63.8/3 29/3
274.4/3
166.2/36
19.4/5
21.2/5
20/5
50/5
20/5
48/5
10/5
6.8/5 6.8/5
40µA
− +
o+o−
Figu e 10: Fully-di e en ial olded-cascode opamp.
61.8/3
183.6/9.4
166.2/36
20/5
50/5
48/5
10/5
20/5 20/5
21.2/5

Global Design o Analog Cells using S a is ical Op imiza ion Techniques 23
6.5. An Example o Low Va iabili y Sizing
The educed a iabili y echnique has been applied o p ac ical opologies wi h good
esul s. Table 7 gi es he esul s o he applica ion o he olded-cascode opamp o Fig.10. Elec-
ical pa ame e s we e co ela ed acco ding o [16], and hei a ia ions a e p opo ional o an-
sis o a ea and he dis ances be ween hem [21]. Compa a i e Mon e Ca lo analyses a e shown
o he design ob ained wi h he s a is ical op imiza ion echnique desc ibed in Sec ion 3 and 4,
and ha desc ibed in his Sec ion. In pa icula , we ha e ocused on hose speci ica ions which
a e mo e sensi i e o echnological a ia ions: o se , DC gain, common-mode ejec ion a io,
and powe supply ejec ion a io. P obabili y dis ibu ions esul ing om Mon e Ca lo analysis
o he la e wo a e e y asymme ic. Hence, i is mo e in e es ing o show hei possible min-
imum alue in said p obabili y dis ibu ion.
Expe imen al esul s wi h he memo y-less echnique o Sec ion 3 and 4 a e seen o di e
wi h he esul s shown in Table 3 o he same example. This is a due o he change in echno-
Table 5. T ansis o sizes o he analog bu e o Fig.1.
M1,2 48/2.2 M5,6 20.8/2.2 M8403.2/2.2 µm
M3,4 167.2/2.2 M7148.8/3 Cc4.7 pF
Table 6. Simula ed esul s o he analog bu e (Ou pu load 10pF@1MΩ).
Speci ica ions Simula ed Uni s
-3dB > 30Mhz 34.35 MHz
minimize Cin, wi h Cin < 0.1pF 0.07 pF
maximize A0−0.169 dB
maximize OS 0.6 <-> −2.2 V
minimize Powe 3.726 mW
2/1.8
11/1.8
12.2/1.8
12.2/1.8
2.4/1.8
10.4/1.8
2/1.8
in+ in−
φ
φφ
SR
Figu e 11: Regene a i e la ch.
2/1.8
11/1.8
2/1.8
2/1.8
2/1.8
2.4/1.8
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 24
logical pa ame e s. A echnology wi h a ailable da a abou elec ical pa ame e co ela ions
was necessa y o apply he educed a iance echnique. Hence, i was easonable o compa e
he esul s wi h he memo y-less echnique using he same echnological pa ame e s.
6.6. Discussion o Resul s
Summa izing, p e ious esul s demons a e he possibili y o size complex analog cells in
ully au oma ic way, s a ing om sc a ch and wi hou designe i e ac ion equi ed -- ea u es
ha ende he p oposed me hodology e y appealing o sys em designe s. As a ma e o ac ,
eso ing o he concou se o his me hodology, and using i also a he unc ional and sys em
le els has enabled o design ull-cus om Σ∆ modula o s wi h educed manpowe in sho ime
cycles [23].
7. Re e ences
[1] M.G.R. Deg auwe e al. “IDAC: An In e ac i e Design Tool o Analog CMOS Ci cui s”. IEEE Jou nal o
Solid-S a e Ci cui s, Vol. 22, pp. 1106-1114, Decembe 1987.
[2] C. Meixenbe ge , R. Hende son, L. As ie and M. Deg auwe: “Tools o Analog Design”, P oc. Wo kshop on
Ad ances in Analog Ci cui Design, pp. 357-368, Sche eningen, The Ne he lands, 1992.
[3] F. El-Tu ky and E.E. Pe y: “BLADES: An A i icial In elligence App oach o Analog Ci cui s Design”.
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[4] G. Gielen and W. Sansen: “Symbolic Analysis o Au oma ed Design o Analog In eg a ed Ci cui s”. Kluwe ,
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[5] R. Ha jani, R. Ru enba and L.R. Ca ley: “OASYS: A F amewo k o Analog Ci cui s Syn hesis”. IEEE
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[6] H. Onode a e al.: “Ope a ional-Ampli ie Compila ion wi h Pe o mance Op imiza ion”. IEEE Jou nal o
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Design”. IEE P oceedings, Vol. 137, P . G, pp. 266-274, Augus 1990.
[8] H. Young Koh, C.H. Sequin and P.R. G ay: “OPASYN: A Compile o CMOS Ope a ional Ampli ie ”. IEEE
T ans. on Compu e Aided Design, Vol. 9, pp. 113-125, Feb. 1990.
Table 7. Simula ion esul s o he olded-cascode opamp.
Memo y-less echnique Reduced a iance echnique
Specs nominal mean a iance min.
alue mean a iance min.
alue Uni s
SR > 70 80.8 109.8 V/µs
o se - 2.0 1.7 1.5 1.0 mV
powe 1.73 1.1 mW
DC gain > 70 80.9 71.4 13.5 72 7 dB
GB > 30 35 31 MHz
PM > 60 65 62.9 o
noise < 12 13.4 11 n
OS > 3 3.89 4.1 V
CMRR 75.12 - 45.3 82.5 - 49 dB
PSRR 150.0 - 94.4 165.0 - 105.5 dB
Global Design o Analog Cells using S a is ical Op imiza ion Techniques 25
[9] G.E. Gielen, H. Walsha s and W. Sansen: “Analog Ci cui s Design Op imiza ion Based on Symbolic Simu-
la ion and Simula ed Annealing”. IEEE Jou nal o Solid-S a e Ci cui s, Vol. 25, pp. 707-713, June 1990.
[10] C. Mak is and C. Toumazou: “ISAID: Quali a i e Reasoning and T ade-o Analysis in Analog IC Design
Au oma ion”, P oc. IEEE In . Symp. on Ci cui s and Sys ems, pp. 2364-2367, 1992.
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[12] F. V. Fe nández, A. Rod íguez-Vázquez and J. L. Hue as: “In e ac i e AC Modeling and Cha ac e iza ion
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[13] B. E. Bose and B. A. Wooley: “The Design o Sigma-Del a Modula ion Analog- o-Digi al Con e e s”.
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[15] “HSPICE Use Manual”. Me a So wa e Inc. 1988.
[16] P.J.M. an Laa ho en and E.H.L. Aa s: “Simula ed Annealing: Theo y and Applica ions”, Kluwe Acade-
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[17] J.K. Robe ge: “Ope a ional Ampli ie s: Theo y and P ac ice”. John Wiley & Sons Inc., 1975.
[18] R. A. Ru enba : “Simula ed Annealing Algo i hms: An O e iew”. IEEE Ci cui s and De ices Magazine,
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[20] C. Michael and M. Ismail: “S a is ical Modeling o De ice Misma ch o Analog MOS In eg a ed Ci cui s”,
IEEE Jou nal o Solid-S a e Ci cui s, Vol. 27, No. 2, pp. 154-166, Feb. 1992.
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Solid-S a e Ci cui s, Vol. 24, No. 5, pp. 1433-1440, Oc . 1989.
[22] C. Wang, R. Cas ello and P.R G ay: “A Scalable High-Pe o mance Swi ched-Capaci o Fil e ”. IEEE Jou -
nal o Solid-S a e Ci cui s, Vol. 21, pp. 57-64, Feb ua y 1986.
[23] F. Medei o, B. Pé ez Ve dú, A. Rod íguez Vázquez y J. L. Hue as: "A Tool o Au oma ed Design o Sigma-
Del a Modula o s using S a is ical Op imiza ion". P oc. o ISCAS’93,, pp. 1373-1376. Chicago, May, 1993.