Global design of analog cells using statistical optimization techniques

Global Design of Analog Cells using Statistical Optimization Techniques 2 Global Design of Analog Cells using Statistical Optimization Techniques F. Medeiro, R. Rodríguez-Macías, F.V. Fernández, R. Domínguez-Castro, J.L. Huertas and A. Rodríguez-Vázquez Dept. of Analog Circuit Design, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes sn. 41012-Sevilla, SPAIN FAX #34 5 4624506, Phone #34 5 4239923 email [email protected] Abstract We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology. Global Design of Analog Cells using Statistical Optimization Techniques 3 Global Design of Analog Cells using Statistical Optimization Techniques F. Medeiro, R. Rodríguez-Macías, F.V. Fernández, R. Domínguez-Castro, J.L. Huertas and A. Rodríguez-Vázquez Dept. of Analog Circuit Design, Centro Nacional de Microelectrónica, Edificio CNM, Avda. Reina Mercedes sn. 41012-Sevilla, SPAIN FAX #34 5 4624506, Phone #34 5 4239923 email [email protected] 1. Introduction The design of analog VLSI building blocks, and in general the design of any integrated circuit, comprises three major steps. First, a suitable schematic must be selected. Then this schematic must be sized to comply required performance specifications on gain, bandwidth, slew-rate, etc., as well as to meet design objectives regarding area, power consumption, etc. Finally, a layout must be generated for the sized schematics. Of these three major steps, this paper focuses on the problem of analog sizing. Analog sizing is a very complicated, time-consuming task whose automation has drawn strong attention in recent years, where several tools and methodologies have evolved [1]-[8]. Two basic reasons lie behind these developments: a) market pressure to reduce the design cost of the analog components of modern analog-digital ASICs and b) the need for custom analog design to be available to ASIC system designers. Most previously reported approaches for automated analog cell design are closed systems covering only a limited number (though not necessarily small, see for instance [1]) of schematics. Some tools work on a flat schematic library where topologies are defined at the device-level [1], [6], [8], [9]. In others [3], [5], [7], [10] architectures are defined at the conceptual level as a connection of sub-blocks (differential pairs, current mirrors, etc.), each of which can be expanded hierarchically down to the device-level. Tools also differ among themselves depending on the sizing strategy used. In some approaches, the sizing process is reduced to a constrained optimization problem [6],[8]; in others, sizing is performed by following specific design plans for each topology, previously developed by expert designers and stored in the tool database [1], [3], [5], [7], [10]. Closed sizing systems are all equation-based; that is, the knowledge about the available topologies is provided as analytical design equations. The associated design equations for new topologies must be generated -- a task for only real analog design experts to tackle. Another Global Design of Analog Cells using Statistical Optimization Techniques 4 drawback relating to closed systems is that they do not allow the exploration of topology enhancements as conceived by designers with some expertise. Some of the drawbacks of closed systems are overcome by the approaches in [9],[11], which are also equation based. The distinctive feature is that some of the design equations for new topologies are automatically generated via auxiliary symbolic analysis tools [9],[12]. Expert concourse is not further required to that end. Unfortunately, symbolic analysis tools provide equations for neither DC nor large signal transient characteristics, whose associated design equations must still be manually provided. Hence, the methodology is only partially open. Furthermore, the level of complexity for AC automatic modeling is limited by the capabilities of symbolic analysis tools (currently, about 15 MOS transistors using high-frequency MOST models and workstation standard configurations). Consequently, this approach is not the most suitable for the automated sizing of complex analog building blocks (for instance, fully-differential opamps), or for applications where large signal specifications play a major role, for instance, oversampled modulators for high resolution A/D converters [13]. Whether closed or open, equation-based systems have a common drawback in that sizing is carried out using simplified analytical descriptions of the blocks. Hence, manual fine-tuning using an electrical simulator and detailed MOS transistor models may be necessary once rough automated sizing is completed. This drawback is overcome in the so-called simulation-based systems [14], which also reduce sizing to a constrained optimization problem, and aim to solve it by following an iterative procedure built around an electrical simulator. No design equations are required in these approaches; the design parameters are updated at each iteration based on the results provided by simulations with detailed transistor models. Thus, they are intrinsically open. A representative example of this methodology is DELIGHT.SPICE [14] where DELIGHT (a general algorithmic optimization tool) and SPICE are combined. Also, advanced electrical simulators, like HSPICE [15], incorporate optimization routines. However, the optimization routines in both tools search for a local solution, and consequently are typically used to redesign cells whose performance specifications are close to the design goals (for instance, technology updating of a cell library), but are inappropriate to size analog cells from scratch. This is a real challenge in analog design automation and requires the development of other techniques. This paper presents a simulation based approach for global sizing of arbitrary topology analog cells using statistical optimization. We demonstrate that by combining proper cost function formulation and innovative optimization heuristics complex cells are designed starting from arbitrary initial points, within reasonable CPU times and with no designer interaction required -- a very appealing feature for ASIC applications. We present results obtained for two fully-differential CMOS opamps, a comparator and an analog output buffer, which were sized using the proposed methodology, fabricated in different CMOS technologies, and whose performance was corroborated from actual silicon prototypes. The proposed technique is also Global Design of Analog Cells using Statistical Optimization Techniques 5 extended to design for low variability incorporating mismatching information in the design procedure. This is illustrated in the design of a CMOS folded-cascode operational amplifier. 2. Some Generalities on Optimization-Based Sizing Analog sizing is a constructive procedure to map cell specifications into design parameter values. Design specifications are given a broad meaning here which includes constraints on the electrical performance parameters of the cell as well as design objectives. Let us consider for illustration purposes the output buffer of Fig.1, one of the examples covered in this paper. A possible specification set for this circuit could include constraints on its DC gain (Ao > target), input capacitance (Cin < target), 3-dB frequency (f3dB > target), and output voltage range (target < OS < target), in addition to the design objective of minimum possible power consumption. With regards to the design parameters, these include transistor dimensions and passive component values. In a generic circuit, the design parameters can be viewed as components of a vector xT = {x1, x2, . . . xN} defining a multidimensional design space. Thus, performance parameters and the features involved in design objectives are given as functions of x; referring again to the example of Fig.1: Ao(x), Cin(x), f3dB(x), OS(x),and Power(x). Then the problem of sizing is formulated as a constrained optimization problem; in particular, for the case of the buffer of Fig.1, (1) Unfortunately, even for elementary analog cells like that shown in Fig.1, the analytical solution vin vo M1M2 M3M4 M5 M6M7 M8 Figure 1: A CMOS output buffer. Cc IB subjected to minimize Power x() Aox() target> Cin x() target< f3dB x() target> target OS x() target<< Global Design of Analog Cells using Statistical Optimization Techniques 6 to the sizing problem is not possible due, among other factors, to the following: •Design equations, i.e., functional relationships among performance parameters and design objectives on one hand, and design parameters on the other, are very difficult to obtain accurately. •These relationships are typically highly nonlinear and, consequently, unsolvable analytically. A further complication arises due to the large dimensions of the design and the specification spaces. •The need to minimize some functions forces the calculation of first and second derivatives and hence, introduces additional complications to the analytical solution process. Due to these difficulties, analog circuits are most conveniently sized by using aniterative, dynamic process. This concept is illustrated in Fig.2: starting from an initial design parameter estimate, x0, a discrete sequence of movements (represented generically as ∆xn) is performed Figure 2: Iterative analog cell sizing: (a) General concept. (b) Manual and automated design updating management. UNSIZED SPECIFICATIONS ELECTRICAL SIMULATION PERFORMANCE EVALUATION GOALS UPDATE PARAMETERS NEW MOV. ∆xn SCHEMATIC INITIAL DESIGN PARAMETER ESTIMATE x0 ACHIEVED? YES NO Design Process Management END xnxn1– ∆xn1– += COST FUNCTION EVALUATION Φ(x) FIGURES OF MERIT EVALUATION ELECTRICAL SIMULATION PARAMETER UPDATING manual management automated management (a) (b) Global Design of Analog Cells using Statistical Optimization Techniques 7 through the design parameter space until an equilibrium solution point x*is found. A key component of this iterative loop is process management: the calculation of the direction and magnitude of the movement ∆xnto be made at each iteration. In manual design, ∆xn is chosen by the designer based on his/her knowledge of the circuit structure being sized - - a difficult and time-consuming task even for experienced analog designers. In automated design, the selection of ∆xn must be performed by the computer based on the evaluation of some critical circuit performance indicators. A convenient approach to do this is to recast the problem formulation as a cost function Φ(x) which quantifies the degree of achievement of the design goals and their relation to the design parameters. Thus, the parameter updating to be done for the subsequent iteration ∆xn is selected at each iteration using functional analysis data of Φ(x). This approach also provides simple and accurate criteria to finish the sizing process at points where the cost function is either maximized or minimized. In the simplest case, ∆xn is calculated by using pieces of information calculated only at xn. However, as demonstrated in this paper, the use of additional information from previous points, at time instances n−1, n−2, etc., may produce more robust solutions of the sizing problem, in the sense of yielding cells whose specifications have lower variability when statistical variations of the technological parameters are taken into account. In this more general case, the updating process is described as a high-order nonlinear discrete-time system, (2) As stated in the introduction, we will assume that performance evaluations in Fig.2 (equivalently, the calculation of performance specification values and the values of the features involved in the design equations as functions of x) are made using electrical simulation and detailed transistor models to guarantee accuracy of the sizing process. Many different alternative implementations of Fig.2 are possible depending on: a) formulation of the cost function itself, b) the updating procedure. Two major alternatives can be roughly identified, depending of the functional structure of S[•] in (2): •Deterministic, incremental techniques where ∆xncalculation uses information about the derivatives of the cost function. This is an important drawback since analytical expressions for the cost function and its derivatives as functions of the design parameters are not commonly available, so that the derivatives must be calculated by numerical interpolation. Another major drawback is that only ∆xn values which lower the cost function are considered. Hence, the optimization process is easily trapped in local minima, rendering it very suitable only for fine adjustment of the design. •Statistical techniques, where ∆xnis calculated at random and hence, requires no information about the cost function derivatives. Parameter updating in deterministic techniques is done only in the direction which lowers ∆xnSΦx()xnxn1– xn2– …xnM– ,, , ,,[]= Global Design of Analog Cells using Statistical Optimization Techniques 8 the cost function. This makes them very sensitive to the starting point and hence, inadequate for global circuit sizing. This is overcome using statistical optimization techniques where movements in the design space are done heuristically, following statistical optimization principles [16]. The price to pay for an independent initial point is a larger number of iterations and hence, longer CPU times. However, as shown here, proper formulation of the cost function, the movement generator, and the cooling schedule, adapted to the nature of analog synthesis, palliates the high computational cost and thus provides a convenient methodology for global design of analog cells. 3. Cost Function Formulation A first step towards devising a tool for automated sizing of analog cells using statistical optimization is to formalize the setting of performance specifications. In a more general case, three different specification classes must be considered: •Strong restrictions: These are specifications whose fulfillment is considered essential by the designer; for instance, the phase margin of an opamp must be larger than 0 (PM > 0) for stability [17]. No relaxation of the specified value is allowed. Hence, if any setting of the design parameters (equivalently, any point of the design parameter space) does not satisfy one strong restriction, it must be rejected immediately. •Weak restrictions: These are the typical performance specifications required of analog building blocks, i.e. Ao > 80dB. Unlike strong restrictions, weak restrictions allow some relaxation of the target parameters, making such circuit sizings which do not meet such specifications acceptable. •Design objectives: Stated as the minimization (maximization reduces to this case by either changing the sign or using the inverse of the function to maximize) of some performance features, (3) for instance, minimize −GB of an opamp (equivalently, maximize GB), where GB denotes the gain-bandwidth product; or minimize the occupied area of the circuit. Mathematically, the fulfillment of these specifications can be formulated as a multiobjective constrained optimization problem, (4) where yΨi denotes the value of the i-th design objective; ysj and ywk denote values of the circuit m inimize yΨix() 1i P ≤≤ m i n i m i ze yΨix () 1iP≤≤ , subjected to ysj x() Ysj or ysj x() Ysj ≤1jQ≤≤,≥ ywk x() Ywk or ywk x() Ywk ≤1,kR≤≤≥    Global Design of Analog Cells using Statistical Optimization Techniques 9 specifications (subscripts s and w denote strong and weak specifications respectively); and Ysj and Ywk are the corresponding targets (for instance, Ao ≥ 80dB, settling time ≤ 0.1µs). The cost function is defined in the minimax sense as follows, (5) where the partial cost functions FΨ(•), Fsj(•), and Fwk(•) are defined as, (6) where wi (called weight parameters for the design objectives) is a positive (alternatively negative) real number if yΨi is positive (alternatively negative), and for Ksj(•) and Kwk(•) we have, (7) where kk (weight parameters assigned to weak restrictions) is a positive (alternatively negative) real number if the weak specification is of ≥ (alternatively ≤) type. Weight parameters are used to give priority to the associated design objectives and weak specifications. As shown in the cost function formulation, only relative magnitude of the weight parameters of the same type makes sense. In (7) weak specifications are assumed positive. Sign criteria is reversed for negative specifications. Strong restrictions are checked first at each iteration. If any of them are not met, the corresponding movement must be rejected. Otherwise, weak restrictions are examined. Weak restrictions have priority over design objectives. If some weak restriction is not fulfilled, the cost function is built only with their contribution. Hence, if no circuit sizing is able to cover all weak specifications, the optimization process will provide results as close as possible. Once all of them are met, the design objectives are evaluated and their influence in the cost function guides their maximization or minimization. 4. Parameter Updating and Process Management Fig.3 shows a block diagram illustrating the operation flow in the proposed methodology. The updating vector, ∆xn, is randomly generated at each iteration. The value of the cost function is calculated at the new parameter space point and compared to the previous one. The new point is accepted if the cost function has a lower value. Unlike deterministic techniques, it may also be accepted if the cost function increases, according to a probability function, minimize Φx() max FΨyΨi ()Fsj ysj ()Fwk ywk (),,{}= FΨyΨi () wiyΨi ()log i ∑ –= Fsj ysj ()Ksj ysj Ysj ,()=, Fwk ywk () Kwk ywk Ywk ,() ywk Ywk ---------   log–= Ksj ysj Ysj ,() ∞– if strong restr i ct i on h o ld s, ∞otherwise,    = Kwk ywk Ywk ,() ∞kk ()sgn if weak restriction holds, k k otherwise,    = Global Design of Analog Cells using Statistical Optimization Techniques 10 (8) depending on a control parameter, T. The random character of movements and the statistical acceptance of those which increase the cost function enable escaping from local minima and hence, wide exploration of the design space. This probability of acceptance changes during the optimization process, being high at the beginning (for large T) and decreasing as the system cools (decreasing T). This is the general concept lying behind simulated annealing optimization techniques -- a process whose name is justified by its analogies to the physical annealing in solids [16]. The tool proposed herein incorporates new heuristics relating to both parameter updating and the cooling schedule itself, as explained below. 4.1. Cooling Schedule Cooling schedule refers to the strategy used to modify the temperature while the process evolves. Unlike classical simulated annealing algorithms [16], where T in (8) decreases mono- PP oe Φ∆ T --------– = Figure 3: Operation flow in the proposed methodology. MOVEMENT NEW MOVEMENT ∆xn INITIAL DESIGN PARAMETER ESTIMATE x0 ACCEPTED? YES NO END xnxn1– ∆xn1– += COST FUNCTION EVALUATION Φ(x) (ELECTRICAL SIMULATION) UPDATE TEMPERATURE SCALE UPDATE MOVEMENT AMPLITUDE xnxn1– = ACCEPT MOVEMENT STATISTICAL ACCEPTANCE P=P(∆Φ,T) END PROCESS? ∆Φ(x)? NO YES > 0 < 0 Global Design of Analog Cells using Statistical Optimization Techniques 17 costly in CPU time and, consequently, not well suited to be used into an iterative optimization loop. Since dispersion of the transistor parameter values is inversely proportional to the device’s area, and to the distance among nominally identical devices [21], a strategy to reduce variability of the cells is to put additional constraints on the design variables. However, this strategy drastically reduces the search space, limiting the achievement of demanding performances. The heuristics described below provides a more convenient approach that take advantage of the large amount of data generated during the statistical optimization process. It encompasses a modification of the cost function structure and a new comparison methodology, in combination to the nonmonotonic cooling schedule. First of all, design specifications, and, hence, the cost function is made to depend not only on the vector of design parameters x, but also on a vector of transistor model parameters e. These model parameters change during the optimization process as a consequence of the dependance of their statistical variability with device area and distances between devices [21]. At each iteration, design parameters are updated according to the heuristics in Section 4.2 and device model parameters are changed according to the statistical distribution of the technological independent parameters [20]. In addition to enlarging the number of parameters, a new addend is incorporated to the cost function to evaluate the sensitivity of performance specifications to device model parameter variations. Such addend is: (15) which incorporates information from the last M iterations, where M corresponds typically to the number of iterations performed in one cooling. Each addend in (15) contains the ratio of the relative increase in the specifications (either weak specifications or design objectives) to the increase in the L device model parameters with respect to previous iteration. The numerator evaluates relative variations of the P performance specifications with respect to previous iteration due to variations in the design parameters x, and the device model parameters e. The amplitude of design parameter variations decreases along each cooling. Therefore, the variability of performance specifications is evaluated with higher precision as the optimization process evolves. This fact is reflected in (15) by the weight parameter w1, which is given by: (16) where r in an heuristic parameter larger than 1. Hence, w1 increases along a cooling, giving more importance in (15) to the addends corresponding to the last iterations within each cooling. A similar weighting between different coolings is done with parameter w2, which is given 1 M ----- yspecixnen ,()yspecixn1– en1– ,()– yspecixnen ,() --------------------------------------------------------------------------------- i1= P ∑ ejn,ejn 1–, – j 1= L ∑ -----------------------------------------------------------------------------------------------w1w2 ⋅⋅        n1= M ∑ w1rn 1 – = Global Design of Analog Cells using Statistical Optimization Techniques 18 by (17) where r’ is a heuristically chosen constant parameter which must be smaller than 1 and l is the ordinal of the current re-heating within the cooling schedule. The cost function at some given iteration must be compared with some previous iteration in order to accept or reject the current design parameter movement. A new comparison methodology is introduced adapted to the new cost function formulation. Each iteration in a given cooling is compared with the iteration of equal ordinal from the best of previous coolings, for acceptance or rejection, following the statistical optimization principles of Section 2. If rejected, the design point of the best cooling is adopted as new point in the current iteration and the optimization process continues. Since (15) is added to the cost function, the optimization process tends to minimize it. That implies small specification increases in the last M iterations and, hence, reduced performance statistical deviations. A mathematical test function has also been used here, to prove the method’s capability and as a benchmark for heuristics refinements. Its analytical struture for a N-dimensional case is, (18) The first addend in (18), sets the mean value of f(•) and the second one creates variations around that mean value. Statistical deviations are simulated at the third addend by means of a random variable, h. The global minimum of dispersion is located in xmin. Sinusoidal variations set local dispersion minima. A method to reduce variance will be acceptable, if the final solution is close to xmin. For a test example with eight independent variables comprised in the interval xn∈[−0.7,0.7], a mean value K=100 and sinusoidal variations with an amplitude K´=10, the new heuristics provides a solution to a distance of 1.75 from the global minimum, where standard deviation is σ= 0.25. A conventional statistical optimization technique ends in distances around 12 from xmin, where standard deviation is σ= 12. 6. Practical Results Proposed techniques have been applied to a wide variety of analog building blocks. Results are shown for the design of two fully-differential opamps, a comparator and an output buffer. Simulated results and measurement of silicon prototypes of the circuits demonstrate the feasibility of the approach. w2r'l1– = fx() KK'2πxk 3 ----------   sin h dist2xx min ,() 2πxk 6 ----------   sin k1= N ∑ +    + k1= n ∑ += Global Design of Analog Cells using Statistical Optimization Techniques 19 6.1. Fully Differential Class-AB Opamp with Dynamic Biasing Let us first consider the fully differential opamp of Fig.7 [22], intended for a 16bit@16KHz second order ∑∆ modulator. This class-AB opamp includes dynamic biasing of the output branches to obtain large output swing and high slew-rate, and uses a dynamic common-mode feedback network. These advanced circuit strategies, and the complexity of the circuit itself (it contains 48 transistors) renders its sizing a difficult task, hard to handle for system level designers. However, the herein proposed methodology was able to automatically size the circuit for the intended application after 1hour CPU time on a 100mips sparcstation, starting from scratch and with no designer interaction required. Table 2 shows the sizing obtained. The first column in Table 1 contains the design goals, which includes a design objective on the power consumption and weak restrictions on the gain-bandwidth product (GBW), phase margin (PM), input white noise and output swing (OS). Fig.7 shows the evolution of the cost function during the optimization process. Note that the vertical axis contains two regions, separated by a dashed line. The weak region corresponds to the case where any of the weak restric- Table 1. Simulated and measured results for the class-AB opamp. Specifications Simulated Measured Units A0≥ 70 74.9 74.6 dB GBW ≥ 20 19.7 19.4 MHz PM ≥ 60 63.3 65 o Input white noise ≤ 50 44.7 - nV/√Hz OS ≥7 8.0 8.2 V Offset - − 3.35 mV Power minimize 4.3 4.3 mW M1M2 M3M4 M8 M6 M10 M9 M22 M26 M18 M30 M14 M20 M28 Mbias Mbias Mbias M7 M5 Ibias M21 M25 M17 M13 M29 M19 M23 M15 M31 M33 M35 M41 M43 M45 M47 M39 M37 C1C2 M42 M44 M34 M36 M38 M40 M48 M46 C1 C2 M16 M32 M24 M12 M11 M27 Vcm+ Vcm- Vo+Vo- V-V+ Figure 7: Fully-differential opamp. Global Design of Analog Cells using Statistical Optimization Techniques 20 tions is violated, while the objective region corresponds to the case where all weak restrictions are fulfilled; inside this region the optimization process focuses on the design objectives. Note that a good design (meaning one that fulfills all the weak restrictions) is obtained after 750 iterations. Simulated results corresponding to the obtained sizing are shown in the second column of Table 1. Fig.9 is a microphotograph of a CMOS 1.2µm double poly n-well prototype of the fully differential opamp. Measured results from the silicon prototype are also shown in Table 1. The Table 2. Sizing for the opamp of Fig.7 M1,2 149.2 / 2.2 µmM 21,22 48.2 / 2.2 µm M3,4 22.0 / 2.2 “ M23,24 42.8 / 2.2 “ M5,6 80.4 / 2.2 “ M25,26 6.2 / 2.2 “ M7,8 11.8 / 2.2 “ M27,28 5.4 / 2.2 “ M9,10 149.8 / 2.2 “ M29,30 78.8 / 2.2 “ M11,12 65 / 2.2 “ M31,32 34.2 / 2.2 “ M13,14 78.8 / 2.2 “ M33-48 5.0 / 1.2 “ M15,16 34.2 / 2.2 “ Mbias 378.0/ 5 “ M17,18 121.8 / 2.2 “ C1-4 0.4 pF M19,20 142.8 / 2.2 “ Ibias 74 µA 0500 1000 # iterations -0.5 0.5 1.5 2.5 3.5 Cost Function Figure 8: Cost function evolution for the optimization of Fig.7. Weak Region Objective Region Global Design of Analog Cells using Statistical Optimization Techniques 21 Σ∆ modulator CMOS prototype, which was built using this opamp, displayed a measured resolution of 15.7bit@16Khz. 6.2. Fully-Differential Folded-Cascode Opamp As a second example, let us consider the folded-cascode fully-differential opamp of Fig.10, which displays the sizes provided by the tool. These sizes were obtained fot the specifications needed in a 17bit@40KHz fourth order ∑∆ modulator. The specifications are given in the first column of Table 3. Once again only the power consumption was a design objective. The optimization process started from scratch on a 10-dimension design space and required about 45mins. of CPU time on a 100mips sparcstation. Simulation results for the sized circuit are shown in the second column of Table 3. The opamp has been integrated in a CMOS 1.2µm double poly n-well technology. Experimental results are given in third column of Table 3. The final Σ∆ modulator prototype displayed 16.8bit@40Khz [23]. Table 3. Simulated and measured results for the folded-cascode opamp. Specifications Simulated Measured Units A0≥ 70 78.52 76.01 dB GBW (1pF) ≥ 30 34.88 - MHz GBW(12pF,1MΩ) 4.17 4.21 MHz PM(1pF) ≥ 60 66.28 - o PM(12pF, 1ΜΩ) 87.2 86.8 o Input white noise ≤ 12 13.53 - nV/√Hz SR ≥ 70 74.81 70.5 V/µs OS ≥±3±3.2 ±3.0 V Offset - − 3.35 mV Power minimize 1.95 1.93 mW Figure 9: Microphotograph of the fully-differential opamp of Fig.7. Global Design of Analog Cells using Statistical Optimization Techniques 22 6.3. Regenerative Comparator The comparator used in the same 17bit ∑∆ modulator was designed using the high-fre- quency regenerative latch of Fig.11 to meet the specifications of Table 4. The simulated and measured results of the sized schematics provided by the design tool are also shown in Table 4. As for the previous opamp, measurements correspond to a prototype built in a CMOS 1.2µm double poly n-well technology. We have analyzed the origin of the slight deviations observed in the measured resolution time and have found that they can be fully explained by taking into account the dynamics of the measurement set-up. 6.4. High-Frequency Analog Buffer The analog buffer of Fig.1 was designed for very low input capacitance. The sizing obtained after 30mins CPU time is shown in Table 5. Table 6 shows the specifications, where the DC gain (A0), output range (OS), and power consumption are design objectives; the 3-dB frequency is a weak restrictions, and the input capacitance is included as a constrained design objective. As shown in the third column of Table 6 the tool was able to obtain a solution with input capacitance as low as 0.07pF and f3dB of 34.35Mhz. Table 4. Simulated and measured results for the comparator. Specifications Simulated Measured Units TPHL < 20 8.0 12.0 ns TPLH < 20 10.0 14.0 ns Resolution < 60 40 36.4 mV Offset - 77 22.5 mV 183.6/9.4 61.8/3 63.8/3 29/3 274.4/3 166.2/36 19.4/5 21.2/5 20/5 50/5 20/5 48/5 10/5 6.8/5 6.8/5 40µA v−v+ o+o− Figure 10: Fully-differential folded-cascode opamp. 61.8/3 183.6/9.4 166.2/36 20/5 50/5 48/5 10/5 20/5 20/5 21.2/5 Global Design of Analog Cells using Statistical Optimization Techniques 23 6.5. An Example of Low Variability Sizing The reduced variability technique has been applied to practical topologies with good results. Table 7 gives the results of the application to the folded-cascode opamp of Fig.10. Electrical parameters were correlated according to [16], and their variations are proportional to transistor area and the distances between them [21]. Comparative Monte Carlo analyses are shown for the design obtained with the statistical optimization technique described in Section 3 and 4, and that described in this Section. In particular, we have focused on those specifications which are more sensitive to technological variations: offset, DC gain, common-mode rejection ratio, and power supply rejection ratio. Probability distributions resulting from Monte Carlo analysis for the latter two are very asymmetric. Hence, it is more interesting to show their possible minimum value in said probability distribution. Experimental results with the memory-less technique of Section 3 and 4 are seen to differ with the results shown in Table 3 for the same example. This is a due to the change in techno- Table 5. Transistor sizes for the analog buffer of Fig.1. M1,2 48/2.2 M5,6 20.8/2.2 M8403.2/2.2 µm M3,4 167.2/2.2 M7148.8/3 Cc4.7 pF Table 6. Simulated results for the analog buffer (Output load 10pF@1MΩ). Specifications Simulated Units f-3dB > 30Mhz 34.35 MHz minimize Cin, with Cin < 0.1pF 0.07 pF maximize A0−0.169 dB maximize OS 0.6 <-> −2.2 V minimize Power 3.726 mW 2/1.8 11/1.8 12.2/1.8 12.2/1.8 2.4/1.8 10.4/1.8 2/1.8 vin+ vin− φ φφ SR Figure 11: Regenerative latch. 2/1.8 11/1.8 2/1.8 2/1.8 2/1.8 2.4/1.8 Global Design of Analog Cells using Statistical Optimization Techniques 24 logical parameters. A technology with available data about electrical parameter correlations was necessary to apply the reduced variance technique. Hence, it was reasonable to compare the results with the memory-less technique using the same technological parameters. 6.6. Discussion of Results Summarizing, previous results demonstrate the possibility to size complex analog cells in fully automatic way, starting from scratch and without designer iteraction required -- features that render the proposed methodology very appealing for system designers. As a matter of fact, resorting to the concourse of this methodology, and using it also at the functional and system levels has enabled to design full-custom Σ∆ modulators with reduced manpower in short time cycles [23]. 7. References [1] M.G.R. Degrauwe et al. “IDAC: An Interactive Design Tool for Analog CMOS Circuits”. IEEE Journal of Solid-State Circuits, Vol. 22, pp. 1106-1114, December 1987. [2] C. Meixenberger, R. Henderson, L. Astier and M. Degrauwe: “Tools for Analog Design”, Proc. Workshop on Advances in Analog Circuit Design, pp. 357-368, Scheveningen, The Netherlands, 1992. [3] F. El-Turky and E.E. Perry: “BLADES: An Artificial Intelligence Approach to Analog Circuits Design”. IEEE Transactions on Computer-Aided Design, Vol. 8, pp. 680-691, June 1989. [4] G. Gielen and W. Sansen: “Symbolic Analysis for Automated Design of Analog Integrated Circuits”. Kluwer, 1991. [5] R. Harjani, R. Rutenbar and L.R. Carley: “OASYS: A Framework for Analog Circuits Synthesis”. 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