(a) (b)
Fig. 1. (a) Finge p in image om he public da abase FVC2002 DB1
and (b) i s associa ed QFinge Map.
Dedica ed Ha dwa e IP Module o Finge p in
Recogni ion
M.C. Ma ínez-Rod íguez, R. A jona, P. B ox, I. Ba u one
Ins i u o de Mic oelec ónica de Se illa (IMSE-CNM),
Spanish Na ional Resea ch Council (CSIC) and Uni e si y o Se ille
Se ille, Spain
{maca ena, a jona, b ox, lumi}@imse-cnm.csic.es
Abs ac —This wo k p esen s a dedica ed ha dwa e IP
module o inge p in s ecogni ion based on a ea u e, named
QFinge Map, which is e y sui able o VLSI design. FPGA
implemen a ion esul s o he IP module a e gi en. A
demons a o has been de eloped o e alua e he IP module
beha io in a eal scena io.
Keywo ds— Biome ics; Finge p in ecogni ion; IP module;
FPGAs
I. INTRODUCTION
Biome ic solu ions a e widely employed o indi idual
ecogni ion. In pa icula , inge p in ecogni ion is widely
accep ed o i s dis inc i eness and ease o use. Mos o
inge p in ecogni ion sys ems ca y ou complex algo i hms
ha ha e o be implemen ed in ha dwa e pla o ms wi h high
compu a ional esou ces o o e eal- ime pe o mance. To
include inge p in ecogni ion in small de ices such as
wea able de ices, ca keys, e c., dedica ed ha dwa e solu ions
a e demanded. Complexi y o he algo i hms should be educed
o o e eal- ime esponse wi h small size and powe
consump ion.
Finge p in ea u es can be classi ied in o h ee le els [1].
The ea u e is mo e local, and he algo i hm o ex ac i is
mo e complex, as highe he le el is. Minu iae, which a e
le el-2 ea u es, a e ypically employed in ecogni ion sys ems.
Le el-1 ea u es, which a e mo e global, a e usually ex ac ed
p e iously o aid he ex ac ion o le el-2 ea u es. The use o
le el-1 ea u es allows educing conside ably he algo i hm
complexi y. Dis inc i eness can be main ained i he use
collabo a es o be ecognized and mul i-biome ics is employed
( o example se e al samples o se e al inge s a e p o ided o
he sys em).
Recen ly, a new le el-1 ea u e called QFinge Map (QFM)
has been p esen ed [2]. Since i o e s a good ade-o be ween
ease o VLSI design and capabili y o ecogni ion, an IP
module has been designed o ex ac i om a inge p in
image. To e alua e i s pe o mance in a eal scena io, a FPGA-
based demons a o has been de eloped.
The pape is o ganized as ollows. The IP module
a chi ec u e and FPGA implemen a ion esul s a e desc ibed
b ie ly in Sec ion II. Sec ion III summa izes he ea u es o a
demons a o ha uses he designed module. Finally,
conclusions a e gi en in Sec ion IV.
II. IP MODULE DESCRIPTION
The module ex ac s a QFM om a inge p in image. The
QFM is ex ac ed om a window cen e ed a he con ex co e
(a singula poin ) o he inge p in . The IP module is o med
by se e al blocks connec ed in cascade which p ocess se ially
he inge p in image un il he QFM is ex ac ed. These blocks
a e he ollowing [2]-[3]:
 Di ec ional image ex ac o : ex ac s a di ec ional
image om he inge p in by assigning a symbol o
each pixel. The symbol ep esen s he one ou o 8
ep esen a i e di ec ion in e als which he idges a
ha pixel belong o. I is calcula ed by applying wo
Sobel masks o ob ain ho izon al and e ical g adien
alues a ound he pixel and e alua ing he ela ion
be ween bo h g adien alues (Fig. 1b illus a es each
symbol wi h a colo ).
 Smoo hing p ocess: main ains he symbol wi h he
highes numbe o occu ences wi hin a 27 x 27
window cen e ed a he cu en pixel. The esul is a
segmen ed di ec ional image wi h homogeneous
di ec ion egions (as illus a ed in Fig. 1b).
 Singula poin s ex ac ion: iden i ies possible con ex
co es using se e al 9 x 9 pa e n masks.
 Singula poin pos -p ocessing: de ec s he con ex
co e, elimina ing alse co es.
QFinge Map
ex ac o
capaci i e
senso SPI in e ace Finge p in image
memo y
clk di ide FPGA
QFM memo y
IP Module
Fig. 3. Scheme o he demons a o .
Fig. 2. Pho og aph o he demons a o .
 Singula window ex ac ion: ex ac s a 129 x 129
window cen e ed a he con ex co e de ec ed.
 QFM ex ac ion: down-samples he singula window
o 17 x 17 symbols, ep esen ed by 867 bi s.
All he blocks we e desc ibed in Ve ilog ha dwa e
desc ip ion language. The IP module employs a gene ic
a chi ec u e ha can be implemen ed in bo h a digi al
in eg a ed ci cui and a FPGA. The implemen a ion esul s o
he module in a 45-nm FPGA a e shown in Table I. The IP
module can each a maximum equency o 116.41MHz. Fo a
whole image o 152 x 200 pixels he ime needed o ex ac he
QFM is 0.26ms. The o al powe consump ion es ima ed is
75mW. The ope a ion equency can be smalle main aining
eal- ime esponse, which would educe powe consump ion.
TABLE I. IMPLEMENTATION RESULTS IN A 45-NM FPGA
Resou ces
Occupied
slices
Slice
egis e s
Slice
LUTs
RAM
Kbi s
IP module
744
1945
2158
270.4
III. DEMONSTRATOR
A demons a o has been de eloped using a comme cial
inge p in senso and a gene al-pu pose FPGA boa d. A
pho og aph o he demons a o is shown in Fig. 2. The module
is employed in he egis a ion and ecogni ion s ages o ex ac
one o se e al QFMs. Fig. 3 shows a schema ic o he
demons a o .
The senso is a compac capaci i e CMOS a ea senso wi h
a size o 10.64mm x 14mm and an e gonomic guidance ame
o imp o ing he placemen o he inge . I cap u es an 8-bi
g eyscale image wi h a esolu ion o 152 x 200 pixels and
ansmi s i by a SPI in e ace a up o 32MHz. I admi s supply
ol age om 2.5V o 3.3V and includes a 30kV ESD
p o ec ion. The FPGA boa d con ains gene al-pu pose inpu -
ou pu s (GPIOs) o which he senso was connec ed. The
a chi ec u e desc ibed in Sec ion II was implemen ed in he
FPGA oge he wi h he SPI p o ocol and a dedica ed SRAM
memo y whe e he inge p in image is s o ed. The image is
hen ead pixel by pixel om he memo y and each 8-bi pixel
is he inpu o he module ha ex ac s he QFM. The FPGA
boa d can wo k a a maximum equency o 48MHz bu a
block ixes i o 24MHz o adap he ope a ion equency o
bo h he FPGA and he senso .
The FPGA boa d also includes an USB mic ocon olle so
ha he demons a o can be connec ed ia USB o a PC. The
PC is used o download he p og am iles in he FPGA and o
isualize esul s om he demons a o .
IV. CONCLUSIONS
A dedica ed ha dwa e IP module o inge p in ecogni ion
has been designed in Ve ilog. I employs simple logic and
a i hme ic ope a ions so ha allows e y low powe
consump ion and apid ex ac ion o he inge p in ea u e.
The module has been implemen ed in a FPGA boa d connec ed
o a inge p in senso and o a PC, so ha he IP module can
be es ed in a eal scena io.
ACKNOWLEDGMENT
This wo k was pa ially suppo ed by TEC2014-57971-R,
TEC2011-24319, IPT-2012-0695 and RTC-2014-2932-8
p ojec s om he Spanish Go e nmen (wi h suppo om
FEDER). M.C. Ma ínez-Rod íguez is suppo ed by FPI
ellowship p og am o Ph.D. S uden s om Spanish
Go e nmen . The wo k o R. A jona has been suppo ed by a
Pos -Doc Fellowship om he Regional Go e nmen o
Andalusia. P. B ox is suppo ed by ‘V Plan P opio de
In es igación’ om he Uni e si y o Se ille.
REFERENCES
[1] D. Mal oni, D. Maio, A. Jain, and S. P abhaka , Handbook o
Finge p in Recogni ion. London, Uni ed Kingdom: Sp inge -Ve lag,
2009.
[2] R. A jona and I. Ba u one, “Finge p in iden i ica ion me hod and
de ice using he same”, WO2015015022 A1, pa en applica ion numbe
PCT/ES2014/000131.
[3] R. A jona and I. Ba u one, “A ha dwa e solu ion o eal- ime in elligen
inge p in acquisi ion,” Jou nal o Real-Time Image P ocessing, ol. 9,
no. 1, pp. 95 – 109, 2014.