Citations refer to the original publication, not to a Scieee localized version.
Avedillo de Juan, M. J., & Núñez Martínez, J. (2018). Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Wiley. https://doi.org/10.1002/cta.2398
Avedillo de Juan, María José, and Juan Núñez Martínez. Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Wiley, 2018. https://doi.org/10.1002/cta.2398.
Avedillo de Juan, María José, and Juan Núñez Martínez. Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Wiley, 2018. https://doi.org/10.1002/cta.2398.
Avedillo de Juan, M. J. and Núñez Martínez, J. (2018) Impact of the RT-level architecture on the power performance of tunnel transistor circuits. Wiley. Available at: https://doi.org/10.1002/cta.2398.
M. J. Avedillo de Juan and J. Núñez Martínez, “Impact of the RT-level architecture on the power performance of tunnel transistor circuits,” Wiley, 2018, doi: 10.1002/cta.2398.
@misc{avedillodejuan2018impact,
author = {Avedillo de Juan, María José and Núñez Martínez, Juan},
title = {Impact of the RT-level architecture on the power performance of tunnel transistor circuits},
year = {2018},
publisher = {Wiley},
doi = {10.1002/cta.2398},
url = {https://doi.org/10.1002/cta.2398}
}
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