A VHDL library for MTM/BST communication

CAV Sesimbra - Portugal INESC - PTSE A VHDL Library for MTM/BST Communication  Gustavo R. Alves, 1,2  José M. M. Ferreira 1,3  José A. R. Tavares, 1  Manuel G. Gericota, 1,2 1 INESC Porto - Portugal 2 Instituto Politécnico do Porto Porto - Portugal 3 Universidade do Porto Porto - Portugal CAV Sesimbra - Portugal INESC - PTSE Motivation  To build a library of VHDL models for an 1149.1 board-level test controller , including a P1149.5 interface layer, with the aim of enabling the development of an MTM/BST system-level test strategy CAV Sesimbra - Portugal INESC - PTSE Requirements  The system-level test specification should be an open ended specification allowing user-defined functionality  Reusability of proven models • board-level test controller • board-level ATPG tool  Flexible implementation accommodating changes in the system-level test specification CAV Sesimbra - Portugal INESC - PTSE Outline of the presentation  The IEEE 1149.1 and P1149.5 Standards  The test protocol  The board-level test controller  The VHDL library  Future directions  Conclusions CAV Sesimbra - Portugal INESC - PTSE The P1149.5 Module Test and Maintenance (MTM) - Bus • The IEEE P1149.5 MTM - Bus defines a serial backplane bus, linking a Master-module and up to 250 Slave-modules. The MTM Bus is formed by 5 dedicated signals: MTM Clock (MCLK), MTM Control (MCTL), MTM Master Data (MMD), MTM Slave Data (MSD) and the optional MTM Pause Request (MPR) CAV Sesimbra - Portugal INESC - PTSE The P1149.5 Module Test and Maintenance (MTM) - Bus • Message exchanging between the M-module and S-modules is based on a packet transfer protocol. Packets are delimited by Bus Pause conditions and messages are delimited by Bus Idle conditions MESSAGE MESSAGE MESSAGE Bus in Idle State Bus in Idle State PACKET COUNT HEADER M DATA 1 S DATA 1 ACKNOWLEDGE MASTER SLAVE Bus in Pause State Bus in Pause State ................ ................ CAV Sesimbra - Portugal INESC - PTSE The P1149.5 Module Test and Maintenance (MTM) - Bus • State transitions of the Master Link Layer State Machine (LLSM) and of the Slaves LLSMs are controlled by MCTL and MMD. The MSD line may also be used to signal an interrupt to the Master during a Pause or Idle Bus condition. The MPR line may be used by the Slave to extend the Bus Pause condition HEADER PACKET MASTER DATA PACKET SLAVE DATA PACKET MCLK MCTL MMD MSD IDLE BUS CONDITION IDLE BUS CONDITION PAUSE BUS CONDITION PAUSE BUS CONDITION DATA TRANSFER BUS CONDITION DATA TRANSFER BUS CONDITION CAV Sesimbra - Portugal INESC - PTSE Boundary Scan Test: The IEEE 1149.1 Std. • The IEEE 1149.1 Std. defines a standard boundary scan architecture and test access port Inst. Reg.: Instruction Register BP Reg.: Bypass Register Dec.: Instruction decoder BS Reg.: Boundary Scan Register TAP Cont.: Test Access Port Controller TDI /TRST TMS TCK BP Reg. Dec. TAP Cont. Inst. Reg. BST Reg. mux mux TDO CAV Sesimbra - Portugal INESC - PTSE Boundary Scan Test: The IEEE 1149.1 Std. • Keywords: Board-level, structural, digital Board-level test controller BST MTM Systemlevel Boardlevel CAV Sesimbra - Portugal INESC - PTSE The board-level test controller • The Slave Status Registers store information about the system activity and errors that may have occurred. All these registers can be read by the Master SLAVE STATUS REGISTER General Status Condition of MTM - Slave. The BSE and EVO bits, when set, require an interrupt. BUS ERROR REGISTER Reports several Bus error conditions. The logical OR of some bits drives the BSE bit of the Slave Status Register. MODULE STATUS REGISTER Module Specific Status that may set the EVO bit - (recommended; presently not implemented). USER-DEFINED STATUS REGISTER Additional Status registers that may set the EVO bit of the Slave Status Register. The MTM interface layer CAV Sesimbra - Portugal INESC - PTSE The board-level test controller • The instruction decode and execution control unit links all MTM blocks The MTM interface layer Command Register Packet Counter Finite State Machine To/From other MTM blocks MTM2BST Linker block CAV Sesimbra - Portugal INESC - PTSE The board-level test controller  The BST controller is a fourth generation dedicated processor core able to control two board-level scan chains  It’s instruction set maps the low-level operations required to control the board-level BST infrastructure The BST controller CAV Sesimbra - Portugal INESC - PTSE The board-level test controller Block diagram of the BST controller Instruction decode and control 16 and 24-bit counters Scan out TAP selector Scan in Status and sync control outputs error TDI TDO D[ 0..7] Sync inputs error end of test sync outputs SelTAP TAP outputs (TAP 0, TAP 1) TAP inputs (TAP 0, TAP 1) DeserEn status inputs ErrFlag [0..15] The BST controller CAV Sesimbra - Portugal INESC - PTSE The board-level test controller Command class Operation description Command name Apply a ‘0’ pulse to TRST line TRST control of Apply a test clock pulse while helding TMS at a given value ‘X’ TMS0, TMS1 BST Shift out vector, no comparation NSHF infrastructure Shift out vector, comparing with expected values NSHFCP Apply N test clock pulses, while helding TMS at ‘0’ NTCK Select active TAP SELTAP0, SELTAP1 control of the Set synchronism output to a given value ‘X’ SSA0, SSA1, SSB0, SSB1 synchronism protocol Wait for synchronism input to be at a given value ‘X’ WSA0, WSA1, WSB0, WSB1 control of Load internal counter (16 or 24 bits long) with N LD C16,N LD C24,N internal resources Select internal error flag ( 15..0) SERFLAG N Stop test program execution HALT The BST controller The instruction set of the BST controller CAV Sesimbra - Portugal INESC - PTSE The board-level test controller FSM Controller 16 bit packet 8 bit instruction/data MTM Interface Layer BST controller DATA MEMORY The MTM2BST Linker Block Block diagram of the MTM2BST Linker Block CAV Sesimbra - Portugal INESC - PTSE The VHDL library  The VHDL library contains a set of functional models leading to a modular architecture based on the three main blocks described: • The MTM interface layer • The BST controller • The MTM2BST Linker block  This library allows customised solutions  The VHDL models were successfully simulated using the MINT software from the Swedish Institute for Microelectronics CAV Sesimbra - Portugal INESC - PTSE Future directions  Synthesis  Local test program memory  MTM/BST system-level test strategy  Diagnostic resolution CAV Sesimbra - Portugal INESC - PTSE Conclusion  The work presented described a library of VHDL models developed to enable a MTM/BST systemlevel strategy  Reusability and flexibility are two key attributes of the proposed implementation  Approval of the P1149.5 by the IEEE Standards Board will create the required conditions to fully exploit a MTM/BST (test) infrastructure