Citations refer to the original publication, not to a Scieee localized version.
Rullán Ayza, M., Ferrer Ramis, C., Oliver, J., Mateo Peña, D., & Rubio Sola, J. A. (1996). Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design. Institute of Electrical and Electronics Engineers (IEEE). https://doi.org/10.1109/EDTC.1996.494360
Rullán Ayza, Mercedes, et al. Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design. Institute of Electrical and Electronics Engineers (IEEE), 1996. https://doi.org/10.1109/EDTC.1996.494360.
Rullán Ayza, Mercedes, Carles Ferrer Ramis, Joan Oliver, Diego Mateo Peña, and Jose Antonio Rubio Sola. Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design. Institute of Electrical and Electronics Engineers (IEEE), 1996. https://doi.org/10.1109/EDTC.1996.494360.
Rullán Ayza, M. et al. (1996) Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design. Institute of Electrical and Electronics Engineers (IEEE). Available at: https://doi.org/10.1109/EDTC.1996.494360.
M. Rullán Ayza, C. Ferrer Ramis, J. Oliver, D. Mateo Peña, and J. A. Rubio Sola, “Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design,” Institute of Electrical and Electronics Engineers (IEEE), 1996, doi: 10.1109/EDTC.1996.494360.
@misc{rullanayza1996analysis,
author = {Rullán Ayza, Mercedes and Ferrer Ramis, Carles and Oliver, Joan and Mateo Peña, Diego and Rubio Sola, Jose Antonio},
title = {Analysis of ISSQ/IDDQ testing implementation and circuit partitioning in CMOS cell-based design},
year = {1996},
pages = {584--588},
publisher = {Institute of Electrical and Electronics Engineers (IEEE)},
doi = {10.1109/EDTC.1996.494360},
url = {https://doi.org/10.1109/EDTC.1996.494360}
}
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