Citations refer to the original publication, not to a Scieee localized version.
Zanotti, T., Zambelli, C., Puglisi, F. M., Milo, V., Pérez Díez, E., Mahadevaiah, M. K., González Ossorio, Ó., Wenger, C., Pavan, P., Olivo, P., Ielmini, D., & Valladolid, U. D. (2020). Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays. Institute of Electrical and Electronics Engineers. https://doi.org/10.1109/TED.2020.3025271
Zanotti, Tommaso, et al. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays. Institute of Electrical and Electronics Engineers, 2020. https://doi.org/10.1109/TED.2020.3025271.
Zanotti, Tommaso, Cristian Zambelli, Francesco Maria Puglisi, Valerio Milo, Eduardo Pérez Díez, Mamathamba K. Mahadevaiah, Óscar González Ossorio, et al. Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays. Institute of Electrical and Electronics Engineers, 2020. https://doi.org/10.1109/TED.2020.3025271.
Zanotti, T. et al. (2020) Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays. Institute of Electrical and Electronics Engineers. Available at: https://doi.org/10.1109/TED.2020.3025271.
T. Zanotti et al., “Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays,” Institute of Electrical and Electronics Engineers, 2020, doi: 10.1109/TED.2020.3025271.
@misc{zanotti2020reliability,
author = {Zanotti, Tommaso and Zambelli, Cristian and Puglisi, Francesco Maria and Milo, Valerio and Pérez Díez, Eduardo and Mahadevaiah, Mamathamba K. and González Ossorio, Óscar and Wenger, Christian and Pavan, Paolo and Olivo, Piero and Ielmini, Daniele and Valladolid, Universidad de},
title = {Reliability of Logic-in-Memory Circuits in Resistive Memory Arrays},
year = {2020},
publisher = {Institute of Electrical and Electronics Engineers},
doi = {10.1109/TED.2020.3025271},
url = {https://doi.org/10.1109/TED.2020.3025271}
}
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