Co esponding au ho : Ka an Diwan.
Copy igh © 2025 Au ho (s) e ain he copy igh o his a icle. This a icle is published unde he e ms o he C ea i e Commons A ibu ion License 4.0.
B eaking bo lenecks: CPU op imiza ion h ough a chi ec u al and neu omo phic
echniques
M L Sha ma, Neelam Sha ma, Sunil Kuma , Ka an Diwan *, Vibho e Aga wal, Ansh Pa hak, Shubham Gup a,
Sh esh h Jain and Ram Ka a a
Depa men o Elec onics and Communica ion Enginee ing, Maha aja Ag asen Ins i u e o Technology, Delhi, India.
Wo ld Jou nal o Ad anced Resea ch and Re iews, 2025, 26(02), 190-204
Publica ion his o y: Recei ed on 17 Ma ch 2025; e ised on 26 Ap il 2025; accep ed on 29 Ap il 2025
A icle DOI: h ps://doi.o g/10.30574/wja .2025.26.2.1463
Abs ac
This esea ch explo es wo di e en app oaches o imp o ing how compu e s p ocess in o ma ion e icien ly. The i s
pa uses he Gem5 simula o o es and compa e h ee ypes o CPU designs—Timing Simple CPU, Mino CPU, and
O3CPU—by unning a basic p og am. We looked a how ea u es like pipelining, caching, and b anch p edic ion a ec
how as he p og am uns and how e icien ly he CPU wo ks. The second pa ocuses on ecognizing handw i en
digi s om he MNIST da ase using wo ypes o AI models. One model is a adi ional neu al ne wo k (MLP) ha uns
on a s anda d compu e se up (Von Neumann a chi ec u e), and he o he is a spiking neu al ne wo k (SNN) ha uns
on a neu omo phic sys em, which mimics how he human b ain wo ks. O e all, his s udy shows how bo h a chi ec u al
imp o emen s and b ain-inspi ed compu ing can help sol e pe o mance and e iciency issues in mode n compu ing
sys ems.
Keywo ds: CPU Op imiza ion; Bo lenecks; Pipelining; Neu omo phic Compu ing; Spiking Neu al Ne wo ks
1. In oduc ion
1.1. Me hod 1 CPU op imiza ion using a chi ec u al me hods
The Cen al P ocessing Uni (CPU) is o en e e ed o as he b ain o he compu e . I is a mul ipu pose, egis e -based,
p og ammable, clock-d i en elec onic de ice ha eads bina y ins uc ions om memo y, accep s bina y da a, and
p ocesses he da a acco ding o hose ins uc ions. The CPU plays a cen al ole in communica ing wi h bo h memo y
and inpu /ou pu (I/O) de ices. Howe e , he Con ol Uni wi hin he CPU manages he iming and coo dina ion o hese
communica ion p ocesses. Wi h ad ancemen s in in eg a ed ci cui (IC) echnology, he CPU was e en ually buil on o
a single chip, leading o he de elopmen o he mic op ocesso .
Despi e he imp essi e speed and capabili ies o mode n CPU’s, hey ope a e below hei maximum po en ial due o
a ious bo lenecks, ac o s ha limi s he o e all speed o execu ion, despi e CPU’s high clock a e. One common o m
o a bo leneck a ises due o he di e ence be ween CPU p ocessing speed and slowe speed o da a ans e which is
especially common in sys ems ha ollow Von Neumann a chi ec u e. In such sys ems, ins uc ions and da a sha e he
same da a bus leading o delays when CPU has o e ch hem one a e ano he .
This pa o he esea ch ocuses on unde s anding hese bo lenecks and explo ing CPU op imiza ion echniques such
as caching, pipelining, b anch p edic ion and ou o o de execu ion. Using gem5 simula o we e alua e h ee buil in
CPU models- TimingSimpleCPU, Mino CPU and O3 CPU each implemen ing di e en ypes o op imiza ion echniques.
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By unning a simila wo kload on each model and obse ing hei beha iou , we aim o unde s and how hese
echniques a ec execu ion pe o mance.
1.2. Me hod 2 CPU op imiza ion using neu omo phic compu ing
Neu omo phic compu ing, inspi ed by he s uc u e and unc ioning o he human b ain, p esen s a adically di e en
app oach o p ocessing in o ma ion. In his esea ch, a Spiking Neu al Ne wo k (SNN) is implemen ed on a
neu omo phic sys em, o e ing an e en -d i en a chi ec u e ha mimics he b ain’s neu al p ocesses. This con as s
wi h he adi ional Von Neumann a chi ec u e, whe e compu a ion and memo y a e sepa a e, c ea ing bo lenecks in
p ocessing speed and powe e iciency.
The SNN model akes ad an age o hese neu omo phic p inciples o imp o e e iciency in asks such as handw i en
digi classi ica ion, using he MNIST da ase . Unlike con en ional neu al ne wo ks, SNNs p ocess in o ma ion in disc e e
e en s, allowing hem o ope a e wi h lowe powe consump ion and memo y usage, making hem highly sui able o
eal- ime and esou ce-cons ained applica ions. This app oach explo es he ade-o s in accu acy, memo y usage,
aining ime, and in e ence la ency compa ed o he MLP model on he Von Neumann a chi ec u e.
Despi e sligh ly lowe accu acy, he SNN model signi ican ly educes memo y usage and la ency, highligh ing he
po en ial o neu omo phic sys ems o o e come he limi a ions o adi ional compu ing a chi ec u es, pa icula ly in
AI asks.
2. Ma e ial and Me hods
2.1. Me hod 1 a chi ec u al me hods
2.1.1. Bo lenecks
The Cen al P ocessing Uni (CPU) plays a c ucial ole in e e yday compu ing— om unning applica ions o b owsing
he in e ne and p ocessing documen s. Despi e apid ad ancemen s in p ocesso echnology, use s o en encoun e
slow o un esponsi e sys ems, especially du ing mul i asking o hea y wo kloads.
This slowdown is commonly due o CPU bo lenecks—si ua ions whe e he p ocesso ’s po en ial is limi ed by slowe
componen s o a chi ec u al cons ain s. Bo lenecks p e en he CPU om execu ing ins uc ions a i s maximum
e iciency, leading o pe o mance deg ada ion. One p ominen ype is he Von Neumann bo leneck, which a ises when
he CPU mus e ch bo h ins uc ions and da a o e a single sha ed bus, causing delays. O he bo lenecks include
memo y la ency, cache misses, poo b anch p edic ion, and lack o pipelining, all o which s all he ins uc ion pipeline
o educe h oughpu .
Unde s anding hese bo lenecks is key o de eloping a chi ec u al imp o emen s like caching, pipelining, and ou -o -
o de execu ion— echniques ha aim o minimize idle CPU cycles and maximize pe o mance.
2.2. Va ious ypes o bo lenecks a e men ioned below
2.2.1. Ins uc ion Fe ch Bo leneck
Happens when he CPU canno e ch ins uc ions as enough, o en due o a sha ed bus o limi ed ins uc ion
h oughpu .
2.2.2. Memo y Bo leneck
Occu s when memo y access is slowe han CPU execu ion speed. Leads o s alls as CPU wai s o da a o load.
2.2.3. Cache Bo leneck
When he wo king se o da a doesn' i in cache, esul ing in equen cache misses and slow memo y accesses.
2.2.4. B anch P edic ion Bo leneck
Happens when he CPU inco ec ly p edic s a b anch, was ing cycles on w ong ins uc ion pa hs.
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2.2.5. Pipeline Bo leneck (o S alls)
In pipelined CPUs, haza ds like da a dependencies, con ol haza ds (b anches), o s uc u al haza ds can cause delays.
2.2.6. In-o de Execu ion Bo leneck
In in-o de CPUs, ins uc ions mus comple e in o de , so one slow ins uc ion can block all o he s.
2.2.7. Resou ce Con en ion
When mul iple ins uc ions compe e o he same execu ion esou ce (ALUs, buses, e c.).
3. Me hodology
To analyze he impac o di e en CPU op imiza ion echniques on execu ion pe o mance, we u ilized he gem5
simula o , a widely used open-sou ce pla o m o compu e a chi ec u e esea ch.
In his s udy, we selec ed h ee buil -in CPU models om gem5’s X86 a chi ec u e:
• Timing Simple CPU – a basic in-o de CPU model wi h no pipelining o caching.
• Mino CPU – an in-o de pipelined CPU ha includes basic b anch p edic ion and suppo o caches.
• O3CPU – a complex ou -o -o de CPU wi h agg essi e pipelining, ad anced b anch p edic ion, and ull cache
hie a chy.
To ensu e consis ency, he same wo kload was execu ed on all h ee CPU models:
A simple "Hello Wo ld" p og am compiled o he x86 a chi ec u e.
The p ima y pa ame e eco ded o pe o mance compa ison was execu ion ime, measu ed in simula ion icks.
Assuming a de aul CPU equency o 1 GHz in gem5, we con e ed he numbe o icks o seconds using he o mula:
Execu ion ime (seconds) = icks ÷ 1,000,000,000,000
This allowed o di ec compa ison o he ime aken by each CPU model o comple e he same ask. The goal was o see
how he inclusion o pipelining, caching, and b anch p edic ion a ec s pe o mance, he eby o e ing insigh in o he
p ac ical impac o each op imiza ion echnique.
3.1. Expe imen s
3.1.1. Hello Wo ld p og am
The “Hello, Wo ld!” p og am is a simple applica ion ha pe o ms a basic ou pu ope a ion wi hou in ol ing complex
da a p ocessing o ex ensi e memo y usage. I ypically consis s o a single unc ion call o p in a sho s ing o he
console. Since he p og am does no in ol e loops, la ge da a s uc u es, o dynamic memo y alloca ion, he numbe o
ins uc ions execu ed is minimal, and memo y access is limi ed p ima ily o e ching he ins uc ions hemsel es and
accessing a small amoun o da a (i.e., he s ing "Hello, Wo ld!"). This simplici y makes i an ideal wo kload o isola ing
and analyzing he aw execu ion e iciency o di e en CPU models wi hou in e e ence om highe -le el so wa e
beha io .
3.1.2. Timing Simple CPU
Timing Simple CPU is he mos basic CPU model a ailable in he gem5 simula o . I ep esen s a non-pipelined, in-o de
p ocesso whe e ins uc ions a e e ched, decoded, execu ed, and e i ed sequen ially. Unlike mo e ad anced models,
Timing Simple CPU does no suppo pipelining, b anch p edic ion, o cache mechanisms by de aul . Each ins uc ion
mus ully comple e be o e he nex one begins, making his model simple bu inhe en ly slow and ine icien o
complex o high- h oughpu asks. Howe e , i s s aigh o wa d design makes i an excellen e e ence poin o
unde s anding how di e en a chi ec u al enhancemen s impac CPU pe o mance. Due o he absence o o e lapping
ins uc ion s ages, any delay—such as memo y access la ency o con ol haza ds—s alls he en i e p ocesso , esul ing
in longe execu ion imes. This model se es as a baseline in ou s udy o highligh he pe o mance gains achie ed
h ough pipelining and o he op imiza ions in mo e ad anced CPUs.
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3.1.3. Possible Bo lenecks in Timing Simple CPU:
Lack o Pipelining: Wi hou pipelining, each ins uc ion mus ully comple e be o e he nex begins, leading o
unde u iliza ion o CPU esou ces. Memo y La ency: Wi hou a cache, he CPU expe iences longe wai imes o
memo y ope a ions, as each access mus e ie e da a di ec ly om main memo y.
BASH COMMAND: ./build/X86/gem5.op con igs/dep eca ed/example/se.py -cpu- ype=Timing Simple CPU -c
es s/ es -p ogs/hello/bin/x86/linux/hello
OUTPUT: Exi ing@ 454646000 icks which means he execu ion ime o Timing Simple CPU o un Hello Wo ld p og am
is 0.454646 milliseconds.
3.1.4. X86Mino CPU
Mino CPU is an in-o de pipelined CPU model in gem5 ha simula es a mo e ealis ic p ocesso compa ed o
TimingSimpleCPU. I b eaks ins uc ion execu ion in o mul iple pipeline s ages— e ch, decode, execu e, and
w i eback—allowing mul iple ins uc ions o be in di e en s ages o execu ion simul aneously. This pipelining
imp o es h oughpu by o e lapping ope a ions and educing idle cycles. Mino CPU also in oduces basic caching
mechanisms and simple b anch p edic ion, making i capable o handling mode a e wo kloads wi h be e pe o mance
han a non-pipelined a chi ec u e.
3.2. CPU Op imiza ion Techniques in Mino CPU
Pipelining is a undamen al echnique used in mode n CPUs o inc ease ins uc ion h oughpu . I wo ks by b eaking
down he execu ion o ins uc ions in o se e al dis inc s ages, such as e ch, decode, execu e, and w i eback. Ins ead o
wai ing o one ins uc ion o ully comple e be o e s a ing he nex , pipelining allows he CPU o wo k on mul iple
ins uc ions a once—each a a di e en s age. This o e lapping o ope a ions signi ican ly imp o es pe o mance by
keeping di e en pa s o he CPU ac i e simul aneously.
B anch P edic ion is used o o e come one o he key challenges o pipelining—con ol haza ds. When he CPU
encoun e s a condi ional b anch (e.g., an "i " s a emen ), i mus decide which ins uc ion pa h o load nex . Wai ing o
he condi ion o esol e would s all he pipeline, so ins ead, b anch p edic ion guesses he likely ou come o he b anch.
Cache is a small, high-speed memo y uni loca ed close o he CPU ha empo a ily s o es copies o equen ly accessed
da a and ins uc ions. I s main pu pose is o educe he ime i akes o he CPU o e ie e in o ma ion om he main
memo y (RAM), which is much slowe . When he CPU needs da a, i i s checks he cache. I he da a is ound he e
(called a cache hi ), i is accessed quickly
3.3. Possible Bo lenecks in X86Mino CPU:
3.3.1. In-o de Execu ion
Mino CPU execu es ins uc ions sequen ially. I an ins uc ion s alls due o a da a dependency o memo y la ency, all
subsequen ins uc ions a e delayed, educing o e all e iciency.
3.3.2. Simple B anch P edic ion
Mino CPU employs a basic b anch p edic ion mechanism. In p og ams wi h complex con ol lows, equen
misp edic ions can lead o pipeline lushes and was ed cycles.
3.3.3. Limi ed Cache Hie a chy
Al hough Mino CPU uses caching, he cache is ela i ely small and basic. High cache miss a es o ce he CPU o e ch
da a om slowe main memo y, inc easing execu ion ime.
• BASH COMMAND./build/X86/gem5.op con igs/dep eca ed/example/se.py -cpu- ype=X86Mino CPU --
caches -c es s/ es -p ogs/hello/bin/x86/linux/hello
• OUTPUT: Exi ing@ 28096500 icks which means he execu ion ime o X86Mino CPU o un Hello Wo ld
p og am is 0.0280965 milliseconds.
Mino CPU pe o ms be e han Timing Simple CPU, Mino CPU is app oxima ely 16 imes as e han Timing Simple
CPU when unning he same "Hello Wo ld" p og am, p ima ily because i employs a pipelined a chi ec u e ha allows
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mul iple ins uc ions o be p ocessed simul aneously in di e en s ages o execu ion. In con as , Timing Simple CPU is
a simple, non-pipelined p ocesso ha execu es ins uc ions sequen ially— e ching, decoding, and execu ing one
ins uc ion a a ime, and only s a ing he nex ins uc ion a e he cu en one has ully comple ed. This sequen ial
na u e leads o ine iciencies, especially when memo y access delays occu . On he o he hand, Mino CPU can o e lap
ins uc ion execu ion, imp o ing h oughpu and educing idle CPU cycles. Addi ionally, Mino CPU includes basic cache
suppo and b anch p edic ion mechanisms, which u he help in minimizing delays due o memo y access and con ol
low changes. These a chi ec u al imp o emen s esul in be e pe o mance, e en o simple p og ams like "hello
wo ld."
3.4. O3CPU
O3CPU, o Ou -o -O de CPU, is he mos ad anced CPU model a ailable in gem5. Unlike in-o de CPUs like Timing
Simple CPU and Mino CPU, O3CPU is capable o execu ing ins uc ions ou o hei o iginal p og am o de o maximize
pe o mance. This a chi ec u e allows he CPU o bypass s alled ins uc ions (such as hose wai ing o memo y) and
con inue execu ing independen ins uc ions, he eby imp o ing ins uc ion-le el pa allelism. These ea u es
collec i ely educe idle ime, make be e use o execu ion uni s, and minimize pe o mance bo lenecks caused by da a
o con ol dependencies. Due o i s complexi y, O3CPU is bes sui ed o simula ing high-pe o mance p ocesso s.
3.4.1. CPU Op imiza ion Techniques in O3CPU
Ou -o -O de Execu ion allows he CPU o execu e ins uc ions as hei ope ands become a ailable, a he han s ic ly
ollowing he o iginal p og am o de . This helps a oid delays caused by ins uc ion dependencies and keeps execu ion
uni s busy.
Specula i e Execu ion and B anch P edic ion allows O3CPU o guess he ou come o b anches. I hen specula i ely
execu es ins uc ions along he p edic ed pa h. I he p edic ion is co ec , his sa es ime, i no , i disca ds he esul s
and olls back.
Pipelining is Simila o Mino CPU bu deepe and mo e dynamic, pipelining enables mul iple ins uc ions o be in
di e en s ages o execu ion a he same ime, imp o ing ins uc ion h oughpu .
Caching in O3CPU u ilizes a hie a chical caching sys em, including L1 and L2 caches, o educe memo y la ency. This
speeds up da a access and helps a oid equen s alls caused by slow memo y.
3.4.2. Possible Bo lenecks in O3CPU
Cache Misses, i da a is no ound in he cache, i mus be e ched om slowe main memo y, causing delays.
Misp edic ed B anches, Al hough he p edic ion is sophis ica ed, inco ec guesses esul in cos ly ollbacks and was ed
cycles.
Pipeline S alls, Due o complex ins uc ion dependencies o esou ce con lic s, pa s o he pipeline can s ill s all.
• BASH COMMAND: ./build/X86/gem5.op con igs/dep eca ed/example/se.py --cpu ype=O3CPU --caches -c
es s/ es -p ogs/hello/bin/x86/linux/hello
• OUTPUT: Exi ing@ 16119500 icks which means he execu ion ime o O3CPU o un Hello Wo ld p og am is
0.0161195 milliseconds.
The execu ion o he “hello wo ld” p og am ac oss h ee di e en CPU models in gem5—Timing Simple CPU, Mino CPU,
and O3CPU—demons a es he signi ican impac o a chi ec u al op imiza ions on pe o mance. Timing Simple CPU,
which lacks pipelining and execu es ins uc ions s ic ly in o de , eco ded he highes numbe o icks a 454,646,000,
indica ing slowes pe o mance. Mino CPU, wi h i s in-o de pipelined design and basic cache and b anch p edic ion
suppo , showed a subs an ial imp o emen , comple ing execu ion in 28,096,500 icks. O3CPU, ea u ing ou -o -o de
execu ion, egis e enaming, specula i e execu ion, and ad anced b anch p edic ion, deli e ed he bes pe o mance
wi h jus 16,119,500 icks. These esul s con i m ha a chi ec u al enhancemen s like pipelining, caching, and ou -o -
o de execu ion g ea ly educe execu ion ime, e en o simple wo kloads. The execu ion speed o he "Hello Wo ld"
p og am ac oss he h ee CPU models in Gem5 e eals signi ican pe o mance di e ences. In Gem5, simula ion ime is
measu ed in icks, whe e 1 ick equals 1 picosecond (1e-12 seconds). The Timing Simple CPU ook app oxima ely
454,646,000 icks, which con e s o 0.000454 seconds. Mino CPU execu ed he same p og am in a ound 28,096,500
icks (0.000028 seconds), and O3CPU comple ed i in jus 16,119,500 icks (0.000016 seconds). These esul s
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demons a e ha while all models comple ed he simple ask wi hin a ac ion o a millisecond, he deg ee o
a chi ec u al op imiza ion g ea ly in luenced pe o mance. TimingSimpleCPU, being a simple non-pipelined model, had
he slowes execu ion. Mino CPU, which inco po a es pipelining and limi ed b anch p edic ion, showed a subs an ial
speed imp o emen . O3CPU, which suppo s ou -o -o de execu ion and mo e agg essi e op imiza ions, ou pe o med
bo h, highligh ing he impac o ad anced CPU ea u es e en on ligh weigh wo kloads.
3.5. Me hod 2: Neu omo phic me hods
3.5.1. Neu omo phic compu ing
Neu omo phic compu ing is inspi ed by he human b ain's a chi ec u e, aiming o c ea e sys ems ha mimic biological
neu al ne wo ks. Unlike adi ional compu ing, which elies on he Von Neumann a chi ec u e, neu omo phic sys ems
use Spiking Neu al Ne wo ks (SNNs). In SNNs, da a is ep esen ed by spikes, mimicking he way neu ons in he b ain
communica e h ough elec ical impulses.
The key bene i s o his app oach a e ene gy e iciency and eal- ime p ocessing. SNNs ac i a e only when necessa y,
educing powe consump ion compa ed o adi ional models ha con inuously p ocess da a. This makes hem ideal
o esou ce cons ained en i onmen s like embedded sys ems and edge compu ing.
To analyze he impac o neu omo phic compu ing on pe o mance and e iciency, we employed he B ian2 simula o ,
a widely used amewo k o simula ing spiking neu al ne wo ks (SNNs) and neu omo phic sys ems.
Fo es ing, we used he popula MNIST da ase , which con ains 70,000 images o handw i en digi s ( om 0 o 9). Each
image is 28x28 pixels. Be o e eeding hem in o he ne wo k, we no malized he pixel alues and con e ed hem in o
spike ains using a simple a e-based me hod — whe e b igh e pixels cause neu ons o spike mo e equen ly.
The ne wo k used in his expe imen was an SNN wi h h ee laye s:
• Inpu Laye : 784 neu ons (one o each pixel).
• Two Hidden Laye s: These helped he ne wo k lea n pa e ns in he digi s.
• Ou pu Laye : 10 neu ons, one o each digi om 0 o 9. The neu on ha spiked he mos was conside ed he
ne wo k’s guess.
The ne wo k was ained using a b ain-inspi ed ule called STDP (Spike-Timing Dependen Plas ici y), which adjus s
he s eng h o connec ions based on he iming o neu on spikes.
We eco ded he ollowing alues o measu e pe o mance: Accu acy, la ency and memo y usage. We hen compa ed
hese esul s wi h a adi ional neu al ne wo k (MLP) ha was ained on he same da ase using PyTo ch on a Von
Neumann sys em. This helped us see how he b ain-like SNN model pe o ms di e en ly om s anda d models in e ms
o speed, memo y, and accu acy.
3.6. Expe imen s
3.6.1. MNIST da ase
Fo es ing, a s anda d handw i en digi ecogni ion ask was used — he MNIST da ase — which is widely accep ed
o e alua ing classi ica ion models. I consis s o 70,000 g ayscale images (28x28 pixels) o digi s om 0 o 9. This
da ase was chosen because i is simple, ye e ec i e o compa ing he lea ning abili y, speed, and e iciency o di e en
neu al ne wo k app oaches. Bo h he adi ional MLP and he b ain-inspi ed SNN we e ained and e alua ed on his
da ase o ensu e a consis en basis o compa ison.
3.6.2. Classi ying digi s om he MNIST Da ase (Von Neumann)
This code ains and es s an AI model (a simple mul i-laye pe cep on neu al ne wo k) o ecognize handw i en digi s.
I measu es how as , how accu a e, and how much memo y i uses and as well as how long i akes o make p edic ions.
I basically akes a 28x28 pixel image o a digi (like ‘4’) and la ens i in o a 1D ec o . I passes i h ough wo hidden
laye s wi h 512 and 256 neu ons.
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3.6.3. CODE:
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3.6.4. OUTPUT:
