Academic Edi o s: A men Sed akian,
S e ano Giagu, La issa B a ina and
Sonia Kabana
Recei ed: 31 Decembe 2024
Re ised: 26 Feb ua y 2025
Accep ed: 26 Ma ch 2025
Published: 1 Ap il 2025
Ci a ion: Pinol, J., on behal o he
ATLAS Collabo a ion. The High-
G anula i y Timing De ec o o
ATLAS a HL-LHC. Pa icles 2025,8,
36. h ps://doi.o g/10.3390/
pa icles8020036
Copy igh : © 2025 by he au ho .
Licensee MDPI, Basel, Swi ze land.
This a icle is an open access a icle
dis ibu ed unde he e ms and
condi ions o he C ea i e Commons
A ibu ion (CC BY) license
(h ps://c ea i ecommons.o g/
licenses/by/4.0/).
A icle
The High-G anula i y Timing De ec o o ATLAS a HL-LHC †
Joaquim Pinol on behal o he ATLAS Collabo a ion
Ins i u Física d’Al es Ene gies (IFAE), The Ba celona Ins i u e o Technology (BIST), Campus UAB,
08193 Ba celona, Spain; [email p o ec ed]
†
This pape is based on he alk a he 13 h In e na ional Con e ence on New F on ie s in Physics (ICNFP 2024),
C e e, G eece, 26 Augus –4 Sep embe 2024.
Abs ac : The inc eased pa icle lux expec ed a he HL-LHC poses a se ious challenge o
he ATLAS de ec o pe o mance, especially in he o wa d egion. The High-G anula i y
Timing De ec o (HGTD), ea u ing no el Low-Gain A alanche De ec o silicon echnology,
will p o ide pile-up mi iga ion and luminosi y measu emen capabili ies, and augmen he
new all-silicon Inne T acke in he pseudo- apidi y ange om 2.4 o 4.0. Two double-sided
laye s will p o ide a iming esolu ion be e han 50 ps/ ack o MIPs h oughou he
HL-LHC unning pe iod, and p o ide a new iming-based handle o assign pa icles o
he co ec e ex. The LGAD echnology p o ides sui able gain o each he equi ed
signal- o-noise a io, and a g anula i y o 1.3
×
1.3 mm
2
(wi h 3.6 M channels in o al).
This pape p esen s he cu en s a us o he HGTD p ojec wi h emphasis on he senso
de elopmen and module esul s.
Keywo ds: LGAD; ALTIROC; iming; es beam; HGTD; ATLAS; HL-LHC
1. In oduc ion
The La ge Had on Collide will s a he High Luminosi y upg ade (HL-LHC) by he
end o 2026. The luminosi y is p ojec ed o inc ease by 7.5 imes and each a o al in eg a ed
luminosi y o 4000/ b [1]. The collisions pe bunch c ossing (BX) will be be ween 140 and
200 wi h 1.5 e ex/mm on a e age along he z-axis. This p esen s impo an challenges o
he adia ion ha dness o he de ec o s as well as o he acking pe o mance o ATLAS.
The Inne T acke (ITk) will be in oduced o imp o e he acking pe o mance up o
|η|=
4 [
2
]. I s z
0
esolu ion on he o wa d egion hough, especially o he low ans e se
momen um (
pT
) pa icles, will no each a good enough posi ion esolu ion o esol e all
he e ices.
The High-G anula i y Timing De ec o (HGTD) is being in oduced o add iming
in o ma ion, which, combined wi h ITk spa ial in o ma ion, will allow he LHC o eco e
pe o mance in he o wa d egion whe e he ITk esolu ion is wo se [
3
]. By enabling a
be e sepa a ion o o e lapping e en s, he HGTD will lead o imp o ed iden i ica ion o
signal p ocesses ( h ough pile-up ejec ion and be e lep on isola ion, o example), which
in u n will enhance he disco e y po en ial o new physics. Addi ionally, he HGTD will
enable mo e accu a e measu emen s o decay imes and p ope ies o sho -li ed pa icles,
en iching he o e all physics p og am o he ATLAS collabo a ion.
In addi ion, i will also p o ide a luminosi y measu emen wi h 1% unce ain y pe BX
o u he imp o e he expe imen pe o mance since he luminosi y is a c i ical con ibu ion
o he o e all sys ema ic e o .
As i will be de ailed below, he HGTD elies on Low-Gain A alanche De ec o s
(LGADs), which a e silicon senso s wi h a hin mul iplica ion laye ha p o ides excel-
Pa icles 2025,8, 36 h ps://doi.o g/10.3390/pa icles8020036
Pa icles 2025,8, 36 2 o 12
len iming esolu ion. The LGAD senso s a e segmen ed in o a 15
×
15 ma ix wi h
1.3 ×1.3 mm2pads
, which a e eadou ia solde bumps by a dedica ed on -end chip
(called ALTIROC). Two hyb ids joined by a lex PCB de ine he HGTD module. In o al,
8032 modules will be moun ed on wo disks a each side o he ATLAS in e ac ion poin
co e ing he pseudo- apidi y egion be ween 2.4 and 4.0. This pape p esen s he cu en
s a us o he HGTD p ojec , which, a his ime, is abou o s a he p e-p oduc ion s age.
2. HGTD Layou
The HGTD is composed o wo end-cap disks placed be ween he ba el and he
end-cap calo ime e s. They will be placed symme ically along he
z
-axis a 3.5 m om he
in e ac ion poin . Each end-cap will con ain wo ac i e double-sided disks, hei elec onics,
connec ions and cooling equi ed o he de ec o ope a ion. The ac i e a ea o each disk
will co e he adius om 120 o 640 mm, wi h a o al de ec o adius o 1.1 m including
he pe iphe al elec onics and o he se ices (see Figu e 1).
Figu e 1. Posi ion o he wo double-sided HGTD disks wi hin ATLAS. The yellow, u quoise and
pu ple ings depic he HGTD modules and he ou e g een a cs he Pe iphe al Elec onics Boa ds
(PEBs). Figu e om [3].
The HGTD will be comp ised o 8032 modules o abou 20
×
40 mm
2
wi h a o al o
mo e han 3.6 M channels. The modules will be o ganized in de ec o uni s (DUs), which
will consis o di e en se s o modules a ached o mechanical PEEK (Polye he E he
Ke one) ames ha will hold hem oge he and in con ac wi h an aluminum cooling pla e
(see Figu e 2). A he ou e mos adius, a se o Pe iphe al Elec onics Boa ds (PEBs) will
be placed o connec o each single module using a lex ail [
4
]. The same layou will be
epea ed o e e y quad an o a double-sided disk.
The PEBs will me ge and ansla e elec ical signals h ough Low Powe Giga Bi
T anscei e (lpGBT) channels [
5
] om di e en modules o op ical connec ions in e acing
he F on -End Link eXchange (FELIX) eadou sys em [6]. They will also p o ide he Low
Vol age (LV) DC powe o he modules using bPOL12 Poin o Load DC/DC
con e e s [7],
ou e an independen High Vol age (HV) channel o each module and moni o he module
powe consump ion and empe a u e. Figu e 1also depic s an axial iew o one HGTD
disk showing he h ee g oups o modules (discussed in he nex sec ion) and he PEBs
dis ibu ed a he pe ime e .
Pa icles 2025,8, 36 3 o 12
Figu e 2. De ec o uni dis ibu ion o a quad an . Each colo ep esen s a di e en DU. The
Pe iphe al Elec onic Boa ds a e also shown in g ay in he ou e egion o he quad an (labeled 1F,
2F, e c.).
3. Challenges
3.1. Time Resolu ion
The main con ibu ion o he HGTD o ATLAS is o add iming in o ma ion o he
acks in he o wa d egion in o de o be able o esol e he e ices no only spa ially
bu also in ime, hus educing he de imen al e ec o pile-up. Du ing he HL-LHC
phase, as is cu en ly he case, he bunch c ossing (BX) ime will be 25 ns. Each BX will
con ain up o 200 collisions wi h a ypical sp ead in ime o
σ ≈
200 ps, and hus he ime
esolu ion needed o disc imina e hei acks is in he ange o a ew ens o pico-seconds.
The iming esolu ion equi emen s o he HGTD a e 30 ps pe ack a he s a o he
li e ime and 50 ps pe ack a e maximum luence while main aining a hi econs uc ion
e iciency abo e 95%. The main con ibu ions o he hi ime esolu ion a e summa ized in
he ollowing equa ion:
σ2
Thi =σ2
Landau +σ2
TW +σ2
ji e +σ2
clock +σ2
TDC (1)
The Landau con ibu ion,
σLandau
, is caused by he non-uni o m ene gy deposi by a
cha ged pa icle along he pa h o a silicon senso . I is in insic o he senso and i depends
on i s cons uc ion and ope a ional a iables, such as bias ol age and empe a u e.
The Time-walk (TW) con ibu ion,
σTW
, a ises om he appa en a ia ion in he Time
o A i al (ToA) o pa icles hi ing he senso simul aneously bu wi h di e ing signal
ampli udes. This occu s when he ToA is de e mined using only a single disc imina o
h eshold. In o de o compensa e o ha e ec , he Time o e Th eshold (ToT) is measu ed,
co ec ing he ToA signi ican ly.
The es o he con ibu ions a e expec ed o be less ele an o he o al ime esolu ion.
The ji e ,
σji e
, is caused by he noise supe imposed on o he senso signal ha leads o
a dispe sion o he ToA. The ji e on he clock,
σclock
, used by he ASIC as a e e ence o
measu e he ToAs adds up o he o al ime esolu ion. This e m includes he LHC clock
ji e con ibu ion, which is known o be eally small, and he con ibu ion om he signal
dis ibu ion wi hin he HGTD, which is es ima ed and expec ed o be o he o de o a ew
pico-seconds. Finally he Time- o-Digi al Con e e (TDC) bin wid h,
σTDC
, a ec s also he
inal ime esolu ion.
The ime esolu ion o a ack imp o es wi h he amoun o hi s acco ding o he
ollowing equa ion.
Pa icles 2025,8, 36 4 o 12
σT ack =σThi
√Nhi s
(2)
3.2. Radia ion Ha dness
Radia ion ha dness is o u mos impo ance o he HGTD due o i being ela i ely
close o he in e ac ion poin and hus subjec ed o conside able adia ion damage. All he
componen s o he HGTD mus be able o wi hs and he adia ion le els i is expec ed o
encoun e du ing i s ope a ional li e ime, a maximum luence o 2.5
×
10
15
1 MeV
neq/
cm
2
.
The acks o he pa icles p oduced by he collisions will no be e enly dis ibu ed o e
he ac i e ange co e ed by he HGTD, ha ing mos o he acks in e sec ing he a ea wi h
highe |η|.
Due o he high adia ion ha dness equi emen s and non-uni o mi y co e age o he
acks, each de ec o disk is g ouped in o h ee independen ly eplaceable ings co e ing
h ee di e en
|η|
anges. The o eseen s a egy is o eplace he inne mos ing h ee
imes (e e y 1000/ b) and he middle ing one ime (e e y 2000/ b), while he ou e ing
is expec ed o wi hs and he ull 4000/ b un il he end o li e o he de ec o . The h ee
independen ly eplaceable ings also ea u e di e en senso o e lap (see Figu e 3).
Figu e 3. The diag am shows he HGTD double-sided laye wi h he cooling pla e (in blue) ins u-
men ed wi h LGAD senso s (in ed). The di e en o e laps wi hin egions a e indica ed wi h he
e ical lines, which also co espond o he h ee disk ings (see ex ). Figu e om [3].
This eplacemen s a egy was chosen o limi he adia ion ha he componen s o
HGTD will ha e o endu e o a maximum luence o 2.5
×
10
15
1 MeV
neq/
cm
2
and a co -
esponding dose o 2 MGy du ing hei li e ime. The limi ing ac o ha equi es eplacing
he disks is he expec ed deg ada ion o he silicon senso s (LGADs) wi h adia ion.
4. HGTD Componen s
4.1. Low-Gain A alanche De ec o s
The senso s used by HGTD a e Low-Gain A alanche De ec o s (LGADs), p o iding
he necessa y ime esolu ion and adia ion ha dness. They a e designed as n-on-p sil-
icon senso s wi h a p- ype mul iplica ion laye and a gain o a ound 20 o keep signal
p opo ionali y and educe he noise.
The ac i e hickness o he senso s is 50 µm o educe he Landau con ibu ion o he
ime esolu ion, by educing he pa h ha cha ged pa icles can a el h ough he senso .
The senso s a e ca bon-en iched. Ca bon is in oduced in he egion o he mul ipli-
ca ion laye o educe he accep o emo al e ec ha o he wise educes signi ican ly he
gain o he mul iplica ion laye a e i adia ion [8].
The HV will be limi ed o 550 V o keep he elec ic ield s eng h below 11 V/µm in
o de o a oid damaging he senso due o he collapse o he elec ic ield induced by a
single cha ged pa icle, a p ocess called Single E en Bu nou (SEB). This ype o ailu e
was obse ed in p e ious p o o ypes, and i has been cha ac e ized on se e al es beams
o de e mine he maximum le el o HV [9,10].
Pa icles 2025,8, 36 5 o 12
4.2. F on -End ASIC
The senso eadou ASIC will be he ALTIROC (ATLAS LGAD Timing In eg a ed
Read-Ou Chips), manu ac u ed using he 130 nm CMOS node om TSMC. I will p o ide
he ToA and ToT and column/ ow in o ma ion o each hi on he 15
×
15 senso ma ix, as
well as a luminosi y measu emen coun ing hi s in each bunch c ossing [
3
]. The con ol logic
and da a p ocessing a e iplica ed o imp o e he immuni y o Single E en Upse s (SEUs).
The elec onics ji e o an inpu cha ge o 10 C ( he expec ed cha ge o a MIP on a
50 µm hick senso and a gain o 20) is equi ed o be smalle han 25 ps. The con ibu ion
o he ime esolu ion om he ASIC TDC bin wid h (20 ps) should be negligible, while he
ime-walk should be smalle han 10 ps a e co ec ion. A he end o li e ime, i.e., a e
i adia ion o 2 MGy, he ji e should be below 70 ps also a a h eshold o 10 C.
The s udies p esen ed he e a e based on he ALTIROC3. I con ains he ull pixel
eadou ma ix wi h a ansimpedance ampli ie pe channel and he equi ed pe iphe al
elec onics, while being adia ion ha d. The nex e sion o he chip, he ALTIROCA, which
includes mino imp o emen s, has been ecen ly p oduced and i is being es ed.
4.3. Modules
The HGTD modules consis o a lex PCB (P in ed Ci cui Boa d), which is glued
on op o wo senso s each con aining 225 channels o 1.3
×
1.3 mm
2
dis ibu ed on a
15 ×15 ma ix.
The senso s a e bump bonded o hei espec i e F on -End (FE) eadou
ASICs, he ALTIROC. Figu e 4shows one o he HGTD modules a e he assembly.
Figu e 4. Module pic u e showing he wo hyb ids (sil e ) below he lex PCB (blue) and he wi e
bonds on op connec ing he hyb ids o he lex. The bias ol age bonds a e also isible in he ci cula
openings nex o he la ge cen al capaci o s. The lex ail connec o is on he side opposi e o he
wi e bonds.
5. Assembly
The assembly o modules and he loading o hem o de ec o uni s is ca ied ou by
di e en esea ch g oups belonging o he ATLAS HGTD collabo a ion, while he inal
assembly and in eg a ion o he de ec o will be ca ied ou a CERN.
5.1. Module Assembly
Each assembly si e will ecei e he componen s o build and es he modules, hese
being hyb ids (senso s bump bonded o he eadou chips), module lex PCBs and de ec o
uni ames.
Pa icles 2025,8, 36 6 o 12
To comple e he assembly p ocess o a module, wo hyb ids need o be a ached o a
module lex PCB while main aining a se o s ic mechanical ole ances (in he o de o
ens o mic ome e s). Those ole ances ensu e ha he module can la e be wi e bonded
and loaded o a suppo uni . The e a e cu en ly wo me hods o pe o ming he hyb id
posi ioning and gluing: one uses dedica ed jigs while he second one elies on a Ca esian
obo . Figu e 5shows a ep esen a ion o h ee modules in con ac wi h he cooling pla e
and connec ed o he lex ails.
The si es using jigs place he wo hyb ids on an inlay ha p o ides an
X
-
Y
and o a ion
e e ence o each (on a co ne ) while a plane holds hem wi h a acuum a a speci ic heigh .
The jigs also p o ide a simila inlay e e ence on he lex PCB and hold i also wi h a
acuum. The glue is hen deposi ed on o he lex wi h a speci ic pa e n o do s o abou
1 mm in diame e using a s encil o wi h a Ca esian obo wi h a glue dispense . Then,
using ou p ecisely machined columns, he wo inlays, one o he wo hyb ids and one o
he lex PCB wi h deposi ed glue, a e b ough o a con olled dis ance, which de e mines
he module hickness. The jig emains closed un il he glue is cu ed.
Tools o enable he assembly o se e al modules in one jig a e being de eloped. This
will allow he speed up o he assembly p ocess while educing he labo a o y space needed
o he pa allel assembly o modules.
A e assembly, isual inspec ion and me ology will need o be pe o med as Quali y
Con ol (QC). I success ul, he module can p oceed o he wi e bonding s ep. The wi e
bonding will elec ically connec he ALTIROC on each hyb id o he co esponding pads on
he lex PCB, and he senso s o he HV lex PCB ings by means o 25 µm hick aluminum
wi es. Once he wi e bonding is comple ed, he module can be cha ac e ized on a es bench.
Du ing he p o o yping phase o he p ojec , hund eds o modules we e p oduced.
This e o culmina ed in No embe 2024 a e abou 50 hyb ids wi h ALTIROC3 ASICs and
p e-p oduc ion LGAD senso s we e p oduced and success ully es ed, as
men ioned below.
Figu e 5. Scheme o h ee HGTD modules a ached o he cooling pla e (in blue). Figu e om [3].
5.2. De ec o Uni Assembly
A a ying amoun o modules will popula e he di e en ypes o de ec o uni s. To
build a de ec o uni , he modules a e placed on a acuum pla e p o iding
X
-
Y
posi ioning
e e ences o he module edges on bo ed holes accessible by using dowel pins. Accu a ely
Pa icles 2025,8, 36 7 o 12
posi ioning he modules is c i ical o ensu e ha hey can be connec ed o he PEBs h ough
he lex ails.
Fou glue do s a e applied a he pe iphe y o each o he lex PCBs o he modules,
which a e used o a ach hem o he de ec o uni PEEK ame, which is placed on op o he
modules and ixed wi h sc ews (see Figu e 6). Those sc ews p ess he ame o he acuum
pla e wi h he modules in be ween. This ensu es ha all he module hyb ids (on he ASIC
side) a e coplana and hus a e all in con ac wi h he cooling pla e in he inal de ec o .
When he loading is inalized, he de ec o uni is mo ed o a anspo pla e and
isual inspec ion and elec ical es s can be pe o med o ensu e no modules we e damaged
du ing loading. Finally, he DUs will be shipped o CERN o he assembly on o he
cooling disks and in eg a ion. The cooling will be p o ided by a CO
2
sys em ope a ed a
−
35
◦
C, which will un h ough he ubes inside he cooling pla e on which he modules
a e moun ed.
Figu e 6. Suppo uni loading es conduc ed a Mainz (Ge many). The modules a e placed in o
p ede e mined posi ions de ined by he dowel pins.
5.3. The mal Cycle S udies
Du ing i s li e ime, he HGTD will expe ience he mal cycles h ough no mal ope a-
ion o he de ec o . As he modules con ain ma e ials wi h di e en coe icien s o he mal
expansion, he mal cycles esul in mechanical s ess applied o he componen s o he sys-
em. Especially sensi i e a e he bump bonds be ween he ASIC and he LGAD senso , since
empe a u e a ia ions can lead o c acking o he bumps, esul ing in
disconnec ed pixels.
To e alua e he de imen al e ec s o empe a u e changes, he modules ha e been i s
cha ac e ized wi h an S -90 be a sou ce, hen exposed o he mal cycles be ween
−45 ◦C
and 40
◦
C on a clima e chambe , and hen measu ed again. The numbe and loca ions o
disconnec ed pixels a e he mal cycles has been s udied.
A e ini ial s udies o ensu e he modules su i e he he mal cycles, he o al hick-
ness o he senso s was inc eased o 775 µm (ac i e a ea + subs a e). Wi h his hickness,
modules we e able o sus ain mo e han 100 cycles be o e su e ing he i s bump ailu es.
Fu he mo e, he ALTIROC-A chip will inc ease he numbe o bumps in he pe iphe y o
u he inc ease obus ness agains he mal cycles.
Pa icles 2025,8, 36 8 o 12
6. Cha ac e iza ion
The cha ac e iza ion is pe o med on es benches using he ALTIROC injec ion mech-
anism and adia ion sou ces, and, o a small numbe o modules, wi h pa icle beams.
The es bench measu emen s o ALTIROC p o ide basic pe o mance e alua ion and
QC, while he es beam cha ac e iza ion p o ides aluable ime esolu ion and senso
e iciency esul s.
6.1. Tes Bench
Fo he es bench cha ac e iza ion o he ALTIROC modules, wo eadou sys ems a e
a ailable: FADA [
11
] (de eloped a IJCLab) and AlVin [
12
] (de eloped a IFAE). Bo h sha e
common ha dwa e, shown in Figu e 7.
Figu e 7. Tes bench measu emen se up used by he FADA and AlVin eadou sys ems o conduc
able- op and beam es s o he HGTD module p o o ypes. The di e en componen s o he sys em
a e indica ed in he pic u es (in his case, an ALTIROC2 hyb id is being es ed).
The eadou ha dwa e is based on a ZC706 boa d om Xilinx [
13
] which con ains a
Zynq FPGA connec ed o a PC wi h an RJ45 using he TCP/IP ne wo k p o ocol. One o he
wo FPGA Mezzanine Ca d (FMC) po s a ailable is used o connec o a cus om in e ace
boa d p o iding a lex ail connec o , which enables communica ion o a module. The LV
powe o he in e ace boa d and he ALTIROC is p o ided by an ex e nal powe supply,
while he HV o bo h senso s (one in each module hyb id) is p o ided ia a BNC po on
he same in e ace boa d. The es bench cha ac e iza ion can be used o e alua e basic
module unc ionali y as well as he senso IV, minimum h eshold, ji e , bump connec i i y
and ToA/ToT bin wid h measu emen s. The bump connec i i y es is pe o med placing a
adioac i e sou ce on op o he module. All pixels should de ec e en s i hey a e well
connec ed, o he wise hey a e conside ed o ha e had a bump ailu e on he pixels showing
no e en s. The esul o such a es is p o ided in Figu e 8.
Pa icles 2025,8, 36 9 o 12
Figu e 8. Occupancy map showing he amoun o de ec ed e en s pe pixel while es ing bump
connec i i y o an HGTD module wi h an S -90 adioac i e sou ce showing all pixels connec ed on
chip0 (le ) and on chip1 ( igh ). Pixel 0-0 is no connec ed by design. Figu e om [14].
6.2. Tes Beam
The es beam se up is c i ical o e alua e he pe o mance o he modules in a ealis ic
en i onmen , mainly wi h beams o pa icles ha a e simila o MIPs. A ypical se up
o he mos ecen es beams includes a elescope o p o ide acking in o ma ion, an
FEI4 [
15
] used o igge ing on a speci ic spa ial egion, a Mic o Channel Pla e (MCP)
p o iding ou s anding ime esolu ion and, o cou se, he hyb id o module as he de ice
unde es (DUT). Addi ionally, o measu e he MCP signal, he ALTIROC TDC e e ence
clock and some o he debug signals, an oscilloscope wi h 1 GHz bandwid h and a sampling
a e o 6.25 Gs/s is used. Figu e 9shows he de ec o s in he measu emen se up.
Figu e 9. Tes beam se up o simul aneous HGTD hyb id and senso es ing a DESY (Hambu g).
The s udied de ices we e placed inside he cooling box in he cen e o he se up.
All he de ec o s and he oscilloscope a e con olled and synch onized wi h he EU-
DAQ2 da a acquisi ion amewo k [
16
] and a igge logic uni (TLU) [
17
]. AlVin is used as
he es beam DAQ sys em, as in he es bench se up. The main di e ence a e wo cus om
PCBs connec ed o he second FMC po on he FPGA boa d o in e ace he TLU. The
AlVin EUDAQ2 p oduce enables he communica ion be ween AlVin and he elescope.
Fo he analysis o he es beam da a, he Co y eckan [
18
] amewo k is used. I
allows o he ack econs uc ion and e iciency calcula ion and plo ing, as depic ed
below. The e iciency is calcula ed o he DUT as e en s on a gi en pixel di ided by he
amoun o eliable acks (de ec ed on a minimum amoun o elescope planes) passing
h ough i . Figu e 10 shows ha , wi hin he cen al pa o he senso pixels, an e iciency
