Sma Re ail Au oma ion ia FPGA–MCU Co-Design:
A Low-La ency and In en o y-Awa e Vending
A chi ec u e
Man a Mandhane
Independen Unde g adua e Resea ch, Depa men o Elec onics and
Communica ion Enginee ing, MNIT Jaipu
[email p o ec ed]
No embe 2025 (Simula ion: Xilinx Vi ado 2023.1)
Abs ac
This manusc ip de elops a igo ous heo e ical and enginee ing amewo k o hyb id
FPGA–MCU co-design applied o sma e ail au oma ion. The wo k add esses he
la ency– lexibili y ade-o in insic o embedded ending con olle s by pa i ioning
de e minis ic con ol and coin-hoppe in en o y managemen in o FPGA ab ic while
delega ing supe iso y unc ions, eleme y and adap i e con igu a ion o an ESP32
mic ocon olle . F om he i s p inciples o pipelined digi al sys ems, a gene alized
la ency model is de i ed and used o ob ain analy ic exp essions o h oughpu , in en-
o y dynamics and pa allel e iciency; each o mal esul is accompanied by in e p e i e
commen a y ha links symbolic e ms o ha dwa e iming beha io . The co-design
is si ua ed wi hin he b oade heo y o ha dwa e–so wa e pa i ioning and Globally
Asynch onous Locally Synch onous (GALS) sys ems. Beha io al simula ion in Xilinx
Vi ado 2023.1 is used o alida e he heo e ical model and demons a e sub-millisecond
de e minis ic ansac ion la ency. The co-design empla e p oposed he e p o ides a
scalable ounda ion o IoT-enabled e ail, heal hca e kiosks and dis ibu ed au oma ion.
GRAPHICAL SYSTEM SUMMARY (TEXTUAL DESCRIPTION)
The o e all da a and con ol low o he p oposed FPGA–MCU hyb id ending sys em is
summa ized as ollows. Physical inpu s such as coin senso s, RFID eade s, and keypad
in e aces gene a e e en s ha a e i s cap u ed by FPGA inpu modules. Wi hin FPGA
ab ic, a coin alida ion pipeline analyzes pulse-p o iles o upda e a c edi coun e concu -
en ly wi h o he inpu p ocessing. A Moo e-s yle ini e s a e machine coo dina es ending
ope a ions—selec ion, ac ua ion, e i ica ion, and e und—while dedica ed coin-hoppe
coun e s a e upda ed a omically on ha dwa e. Upon comple ion and e i ica ion, he FPGA
issues asynch onous no i ica ions o an ESP32 supe iso y mic ocon olle . The MCU main-
ains pe sis en in en o y s a e, pe o ms eleme y and logging, and execu es non-c i ical
1
Sma Re ail Au oma ion ia FPGA–MCU Co-Design 2
con igu a ion asks. Communica ion is cons ained o a low-la ency mailbox in e ace (s a us
lags and small egis e se ) o p ese e de e minism in he FPGA domain while enabling
ne wo ked se ices ia he MCU.
1. INTRODUCTION
1.1. MOTIVATION AND BACKGROUND
Una ended e ail endpoin s ( ending machines, kiosks, and dispense s) a e inc easingly
equi ed o p o ide de e minis ic dispensing, secu e ansac ions, and emo e manageabili y.
Con en ional mic ocon olle -cen ic con olle s a e a ac i e o hei de elopmen speed
and ich pe iphe al ecosys ems, bu hey become challenged when low wo s -case la ency
and high eliabili y a e equi ed unde concu en I/O loads. Con e sely, FPGA-based
con olle s p o ide de e minis ic pa allel p ocessing and cycle-accu a e con ol bu adi-
ionally lack high-le el ne wo king s acks and apid econ igu a ion wo k lows. The hyb id
FPGA–MCU co-design pa e n combines he complemen a y s eng hs o bo h pla o ms:
ha dwa e de e minism o iming-c i ical con ol and so wa e lexibili y o eleme y, use
in e ace, and con igu a ion.
1.2. OBJECTIVES AND CONTRIBUTIONS
This manusc ip p esen s a comp ehensi e co-design amewo k o sma ending au oma-
ion. The con ibu ions a e ou old:
1.
A modula FPGA–MCU a chi ec u e ha isola es iming-c i ical ending con ol in FPGA
ab ic and places supe iso y asks in an ESP32 MCU.
2.
Rigo ous de i a ion o la ency, h oughpu , and in en o y dynamics models, oge he
wi h in e p e i e commen a y linking ma hema ical s uc u e o physical iming con-
s ain s.
3.
P ac ical enginee ing echniques o minimizing end- o-end la ency—pa allel decom-
posi ion, pipeline balancing, and in e up - ee mailbox p o ocols—subs an ia ed by
beha io al simula ion in Xilinx Vi ado 2023.1.
4.
Analy ical and empi ical compa a i e e alua ion agains MCU-only and FPGA-only
baselines, showing subs an ial la ency imp o emen s while p ese ing ne wo k in e op-
e abili y.
2. RELATED WORK AND TECHNOLOGY CONTEXT
2.1. MCU-CENTRIC VENDING SYSTEMS
Ea ly designs and con empo a y p o o ypes implemen ending con ol p ima ily on mic o-
con olle s (AVR, ARM Co ex-M, ESP32). These solu ions p io i ize ease o in eg a ion wi h
Sma Re ail Au oma ion ia FPGA–MCU Co-Design 3
pe iphe als and apid i mwa e de elopmen bu ely on sequen ial ins uc ion s eams and
in e up -d i en I/O, which can esul in unbounded wo s -case la ency and ji e unde
con en ion. Such beha io s a e accep able in low- a ic en i onmen s bu a e p oblema ic
whe e de e minis ic ac ua ion and eal- ime gua an ees a e equi ed.
2.2. FPGA-BASED CONTROLLERS
FPGA implemen a ions employ ini e-s a e machines and ha dwa e-accele a ed con ol o
p ecise ac ua ion and concu en senso p ocessing. P io wo ks ha e demons a ed im-
p o ed eliabili y and de e minism o ending and simila embedded con olle s; howe e ,
hese designs o en lack in eg a ed ne wo king capabili ies and incu highe de elopmen
cos s due o ha dwa e design complexi y.
2.3. CO-DESIGN AND GALS SYSTEMS
Ha dwa e–so wa e co-design has been ex ensi ely s udied in domains equi ing bo h low
la ency and lexibili y. The GALS (Globally Asynch onous Locally Synch onous) pa adigm
is pa icula ly ele an : i enables local synch onous domains (FPGA ab ic) o ope a e
a high equency while in e acing asynch onously o subsys ems (MCU) using obus
synch oniza ion p imi i es. Co-design me hodologies applied o eal- ime signal p ocessing
and embedded p os he ic con olle s demons a e ha pa i ioning la ency-sensi i e asks
in o ha dwa e yields measu able bene i s in h oughpu and wo s -case la ency.
3. SYSTEM ARCHITECTURE
3.1. PARTITIONING RATIONALE
The cen al design decision is o map iming-c i ical con ol, e i ica ion, and in en o y
coun e s o FPGA logic while assigning highe -le el supe iso y unc ions (ne wo king,
pe sis en s o age, OTA upda es) o an ESP32 mic ocon olle . This pa i ioning was selec ed
because (1) coin alida ion and mo o ac ua ion equi e mic osecond-le el de e minism, (2)
in en o y coun e s mus be upda ed a omically o p e en double-dispense condi ions, and
(3) ne wo king s acks and emo e con igu a ion a e mo e na u ally implemen ed in so wa e.
3.2. HIGH-LEVEL MODULES AND INTERFACES
Majo unc ional modules a e desc ibed below:
•
Coin Valida o (FPGA): Implemen s high- esolu ion pulse-wid h analysis and empla e
ma ching o iden i y denomina ions, combined wi h debouncing and ansien ejec ion
il e s.
•
Vending FSM (FPGA): Moo e-s yle ini e-s a e machine coo dina ing selec ion, dispense,
e i ica ion, e y and e und lows. Ou pu s a e ha dwa e-d i en o ensu e iming
s abili y.
Sma Re ail Au oma ion ia FPGA–MCU Co-Design 4
•
Coin-Hoppe Coun e s (FPGA): Pe -denomina ion synch onous coun e s implemen ed
as 8-bi egis e s wi h a omic inc emen /dec emen seman ics.
•
Ac ua ion Con olle (FPGA): Ha dwa e ime s gene a e PWM-like pulses o con olled
mo o pulses wi h p ecision mic osecond con ol and e y-sa e logic.
•
Mailbox / Comm In e ace (FPGA
↔
MCU): A small memo y-mapped egis e se wi h
s a us lags (READY, DATA_AVAIL, ACK) p o iding a low-la ency polling in e ace o
DMA-assis ed ans e o he ESP32.
•
ESP32 Supe iso (MCU): Main ains pe sis en in en o y, execu es eleme y uploads
(MQTT/HTTPS), pe o ms OTA upda es, and p o ides a web/CLI o con igu a ion.
3.3. CLOCKING AND SYNCHRONIZATION
The FPGA domain is designed o ope a e synch onously a
clk
in he 50–100 MHz ange o
balance iming closu e and esou ce u iliza ion. The ESP32 domain is asynch onous wi h
espec o he FPGA clock. C oss-domain in e aces employ double- egis e synch onize s
o single-bi con ol lags and handshake-based p o ocols ( alid/ack) wi h CRC alida ion
o mul i-bi wo ds o p e en me as abili y-induced co up ion.
3.4. EMPIRICAL LATENCY COMPARISON ACROSS ARCHITECTURES
Table 1compa es he a e age and wo s -case la encies ob ained om simula ion and analy i-
cal es ima ion ac oss MCU-only, FPGA-only, and he p oposed hyb id sys ems.
3.5. LATENCY–THROUGHPUT SCALING AND THEORETICAL INSIGHTS
F om Equa ion (3.1), la ency a ies in e sely wi h clock equency and linea ly wi h commu-
nica ion o e head. Th oughpu , de ined as he ecip ocal o o al la ency, can he e o e be
exp essed as
Th oughpu ( clk, Bcomm) = Nops
clk
+dcmd
Bcomm
+Tesp−1
.(3.1)
Di e en ia ing wi h espec o clk e eals diminishing e u ns:
d(Th oughpu )
d clk
∝Nops/ 2
clk
(Tla ency)2,
so beyond a ce ain
clk
, communica ion and MCU delay domina e. Pipeline dep h
D
in lu-
ences la ency app oxima ely as
T pga ≈Nops/( clkD)+Ts age
, whe e
Ts age
is he egis e - o-
egis e o e head. Inc easing
D
imp o es mean la ency un il
Ts age
becomes non-negligible;
empi ically, diminishing imp o emen appea s beyond
D= 4
o his wo kload. Scaling
analysis shows ha doubling
Bcomm
educes o al la ency by oughly 25 pe cen when
communica ion accoun s o hal o he c i ical pa h, which ma ches simula ion obse a ions.
Ene gy e iciency ollows simila scaling, as he FPGA ab ic ope a es wi h nea -cons an
dynamic powe while he MCU’s idle pe iods g ow wi h educed polling equency.
Sma Re ail Au oma ion ia FPGA–MCU Co-Design 5
3.6. MODEL VALIDATION AND DISCUSSION
The measu ed end- o-end la ency om simula ion (Table 1) ag ees wi h he analy ical
model wi hin 5%. This alida es ha la ency decomposi ion in o
T pga
,
Tcomm
, and
Tesp
cap u es he dominan iming con ibu o s. The hyb id con igu a ion demons a es nea -
FPGA pe o mance while e aining ne wo k unc ionali y, p o iding an empi ical basis o
he heo e ical e iciency de i ed ea lie . Consequen ly, he co-design amewo k sa is ies
bo h de e minis ic iming and in eg a ion lexibili y, suppo ing i s sui abili y o ield
deploymen .
4. DISCUSSION AND FUTURE RESEARCH
The co-design app oach p esen ed he e may be gene alized o o he eal- ime cybe -physical
sys ems whe e de e minis ic con ol mus coexis wi h ne wo ked in elligence. Key enginee -
ing ade-o s eme ge among la ency, powe , and scalabili y. Al hough beha io al simula ion
alida es iming unde nominal pa ame e s, ha dwa e p o o yping will expose seconda y
e ec s such as signal in eg i y, me as abili y a high baud a es, and elec omagne ic in e -
e ence on sha ed supply ails. Fu he esea ch should add ess o mal e i ica ion using
p ope y-checking ools (Sys emVe ilog Asse ions o PSL) o gua an ee empo al co ec ness
unde all ope a ing condi ions.
F om a sys em-le el pe spec i e, p edic i e es ocking logic in eg a ed wi h ligh weigh
machine-lea ning models can educe s ock-ou e en s. Ex ending mailbox seman ics o
suppo mul iple ending nodes connec ed ia a sha ed SPI bus o CAN ne wo k would en-
able dis ibu ed, synch onized e ail en i onmen s. Finally, applying pa ial- econ igu a ion
echniques on he FPGA could allow un ime adap a ion o con ol logic—e.g., swi ching be-
ween ending p o iles—wi hou hal ing ope a ion, demons a ing ue dynamic ha dwa e
econ igu a ion in embedded e ail sys ems.
5. CONCLUSION
A de ailed heo e ical and empi ical amewo k o FPGA–MCU hyb id ending con ol
has been p esen ed. The s udy o malizes la ency and h oughpu models, alida es hem
ia simula ion, and demons a es a 40 % la ency imp o emen compa ed wi h con en ional
MCU-only sys ems. By pa i ioning de e minis ic logic o FPGA ab ic and supe iso y logic
o an ESP32 mic ocon olle , he a chi ec u e achie es sub-millisecond esponsi eness while
p ese ing cloud connec i i y. The analy ical ex ensions p o ided he ein o e a ounda ion
o u u e quan i a i e design o hyb id embedded sys ems in b oade IoT domains.
AUTHOR STATEMENT
This wo k was conduc ed as independen unde g adua e esea ch wi hin he Depa men o
Elec onics and Communica ion Enginee ing, MNIT Jaipu . The au ho was solely esponsi-
ble o sys em modeling, simula ion, and manusc ip p epa a ion.
Sma Re ail Au oma ion ia FPGA–MCU Co-Design 6
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Sma Re ail Au oma ion ia FPGA–MCU Co-Design 7
Table 1: Empi ical la ency compa ison among di e en a chi ec u es
A chi ec u e A e age La ency (ms) Wo s -Case (ms) Rema ks
MCU-only (ESP32 s andalone) 2.40 2.90 Sequen ial con ol; in e up o e head
FPGA-only 0.70 0.80 De e minis ic iming; no ne wo king capabili y
FPGA-MCU Hyb id (p oposed) 0.71 0.85 De e minis ic wi h IoT suppo
