THEORETICAL AND APPLIED ELECTRICAL ENGINEERING VOLUME: 14 |NUMBER: 1 |2016 |MARCH
Ul a Low Powe High Speed Domino Logic Ci cui
by Using FinFET Technology
Ajay Kuma DADORIA, Ka i a KHARE, Ta un Kuma GUPTA, R. P. SINGH
Depa men o Elec onics and Communica ion Enginee ing,
Maulana Azad Na ional Ins i u e o Technology, Bhopal, 462003, India
aja[email p o ec ed], ka i a_kha [email protected], [email p o ec ed], [email p o ec ed]
DOI: 10.15598/aeee. 14i1.1538
Abs ac . Scaling o he MOSFET aces g ea e chal-
lenge because o ex eme powe densi y due o leakage
cu en in ul a-deep sub-mic on (UDSM) echnology.
To o e come his si ua ion double ga e de ice such as
FinFET is used which has excellen con ol o e he
hin silicon ins wi h wo elec ically coupled ga es ha
mi iga e sho e channel e ec and exponen ially e-
duce leakage cu en . The p esen wo k u ilized he
p ope y o FinFET in domino logic, o high speed op-
e a ion and educ ion o powe consump ion in wide
an-in OR ga e. The p oposed ci cui is simula ed in
FinFET echnology by BISM4 model using HSPICE
and 32nm p ocess echnology a 25 ◦C wi h CL=1 pF
and 100 MHz equency. Fo 8 and 16 inpu OR ga e
in SG mode, we sa ed an a e age powe o 11.5 %
and 11.39 % in SFLD, 22.97 % and 18.12 % in HSD,
30.90 % and 34.57 % in CKD, espec i ely; while o
ha in LP mode, we sa ed an a e age powe o 11.26 %
and 15.78 % in SFLD, 19.74 % and 17.94 % in HSD,
45.23 % and 34.69 % in CKD espec i ely.
Keywo ds
FinFET, high speed, mul iga e de ice, sho
channel e ec .
1. In oduc ion
Scaling o CMOS echnology is needed o imp o e de-
ice densi y and pe o mance o he ci cui . How-
e e di icul ies in scaling o bulk CMOS a e he p ime
h us o de eloping a new a chi ec u e wi h a dou-
ble ga e which has highe scalabili y han single ga e
ansis o , because bo h he ga es con ol he in po-
en ial o e he body [1]. I is impo an o de elop
an e icien echnique o o e come sho e channel e -
ec and; powe consump ion as well as main ain he
pe o mance o he ci cui . As shown in Fig. 1(a) and
Fig. 1(b), double ga e FinFET has an excellen con-
ol o e hin silicon body which supp esses he sho e
channel e ec in sub 22 nm and beyond, and educes
he sub h eshold and ga e oxide leakage cu en [2].
FinFET echnology has a wide ange o cha ac e is ics.
The ga e e minal can be sho ened o eplace CMOS
echnology in SG mode. In Independen Ga e (IG)
mode, wo ga es wo k independen ly, o be e con-
ol o e he silicon in. The in body o a double-ga e
de ice is ypically undoped o ligh ly doped; he e o e,
enhancemen o ca ie mobili y and de ice a ia ions
due o doping luc ua ions a e educed. To inc ease he
ION cu en o he FinFET he numbe o ins in he
FinFET can be inc eased, which in u n inc eases he
cu en d i ing capabili y.
The pape is o ganized as ollows: Sec ion 2. de-
sc ibes he FinFET echnology o DSM. Sec ion 3.
p esen s he li e a u e e iew o high speed domino
ci cui s. Sec ion 4. depic s he p oposed ci cui
o low-powe and high- speed ope a ion. Sec ion 5.
desc ibes he simula ion esul s and discussion using
HSPICE EDA ool, and inally, he conclusion is p e-
sen ed in Sec ion 6.
2. FinFET Technology
The main ad an age o he FinFET s uc u e is he
ab ica ion o double ga e using a single li hog aphy
and e ch s ep. A ga e is easily w apped o e he sili-
con in. As he on and back ga e ha e di e en dop-
ing p o ile, hey ope a e independen ly acco ding o
he equi emen [3]. One o he main challenges in de-
eloping FinFET o e bulk-CMOS is he high cu en
d i e by educing pa asi ic esis ance, and he sou ce
d ain egion equi es e-enginee ing.
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Fig. 1: (a) 3D iew o a single in o FinFET. (b) Top iew o
FinFET.
Owing o he e ical ga e s uc u e, he wid h o
FinFET is quan ized, and he in heigh is de e mined
by minimum ansis o wid h (Wmin). When wo
ga es o a single-FinFET is ied oge he as shown in
Fig. 1(a), Wmin is e ec i e channel wid h:
Wmin = 2H in +T in,(1)
e ec i e channel leng h:
Le =Lga e + 2 ·Lex ,(2)
whe e H in is he heigh o he in, T in is he hick-
ness o he silicon body, and Lex is he ex ension o in
om ga e o sou ce o d ain e minal [4]. To supp ess
sho e channel e ec and enhance he a ea e iciency in
FinFET, he in hickness should be much lowe han
he in heigh [5], [6], [7]. Table 1 shows he pa ame-
e s ha mus be aken in o conside a ion du ing he
simula ion o N-FinFET and P-FinFET.
Tab. 1: De ice echnology pa ame e s.
Pa ame e 32nm
N-FinFET
32 nm
P-FinFET
Leng h o Channel (L) 32 nm 32 nm
Fin hickness( si) 8.6 nm 8.6 nm
Fin heigh (H in) 40 nm 50 nm
Oxide hickness( ox) 1.4 nm 1.4 nm
Sou ce/d ain doping
(N- ype and
P- ype FinFETs)
2·10−20 cm−32·10−20 cm−3
Powe Supply (V dd) 0.8 V 0.8 V
FinFET wo ks in h ee di e en modes acco ding o
he supply o on and back ga es, namely Sho Ga e
(SG) mode, Low Powe (LP) mode and Independen
ga e (IG) mode as shown in Fig. 2 [8].
•SG mode - In his mode, he on and back ga es
a e ied oge he wi h common supply ol age.
The sho ga e is as e and has highe ION cu -
en .
•LP mode - In his mode, he on and back ga es
bias independen ly, and back ga e is e e se biased
o educ ion o leakage cu en .
•IG mode - In his mode, bo h ga es a e connec ed
o di e en inpu s, simila o a wo pa allel an-
sis o s which educes he a ea o he ci cui .
Fig. 2: Mode o ope a ion o FinFET.
Fig. 3: SG mode ((VF G =VBG)), IG mode (VF G 6=VBG) con-
igu a ion o FinFET.
Biasing o he back ga e o FinFET inc eases he
ON s a e cu en (ION ) and mi iga es he OFF s a e
cu en (IOF F ). ION can be de ined when Vds=0.8 V
and VGS=0.8 V, whe e IOF F can be de ined when
Vds=0.8 V and VGS=0 V. A symbolic ep esen a ion
and biasing is shown in Fig. 3, FinFET has ou e -
minals ha ’s why we call i is 4T de ice. As shown
in Tab. 2 and Tab. 3 ollowing applica ion o di e -
en biasing on he back ga e o N and P FinFET, P-
FinFET p esen ed signi ican ly lowe leakage cu en
han N-FinFET. Fu he mo e, i can be obse ed ha
wi h he inc ease in VBG o 4T P-FinFET om 0.6
o 1.6 V bo h he ION and IOF F dec eased, bu he
pe cen age o educ ion o IOF F was much highe han
ION ( educ ion is 250x) om o ignal [8].
Table 3 p esen s he alue o ION and IOF F calcu-
la ed o VGB om -0.6 V o 0.4 V bo h IOF F and ION
inc eases bu inc emen o IOF F is much highe han
ION cu en . The simula ion esul s indica e ha he
d i ing capabili y o N-FinFET was highe han ha
o P-FinFET when VBG was e e se biased N-FinFET
p esen ed g ea e ad an age han P-FinFET when he
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back ga e biased, which signi ican ly educed he leak-
age cu en in FinFET based digi al ci cui . Ne e he-
less P-FinFET exhibi ed highe d i ing capabili y and
dec eased he sub- h eshold leakage cu en [9].
Tab. 2: Resul s o IOF F and ION o 4T P-FinFET o single
Fin.
VBG IOF F (aA)ION (µA)
0.6 487.5 8.27
0.8 256.2 6.67
1.0 25.15 4.35
1.2 5.57 3.02
1.4 2.11 1.45
1.6 1.06 0.94
Tab. 3: Resul s o IOF F and ION o 4T N-FinFET o single
Fin.
VBG IOF F (pA)ION (µA)
-0.6 0.067 0.81
-0.4 0.251 12.20
-0.2 2.75 14.63
0.0 37.24 16.25
0.2 867.36 19.37
0.4 22930 21.32
3. Li e a u e Re iew
Domino logic ci cui is used in high-speed mic op oces-
so s, whe e speed and high pe o mance a e he p ime
conce n wi h espec o scaling o echnology.
3.1. Foo less Domino Logic Ci cui
Foo less domino logic ci cui is an exis ing domino
logic ci cui . The majo di e ence be ween oo less
and oo ed domino logic ci cui is he oo ed NMOS
ansis o which is placed below he e alua ion ne wo k
in oo ed domino logic ci cui , and which is absen in
oo less domino logic ci cui . The ci cui diag am o
oo less domino logic ci cui is shown in Fig. 4.
Fig. 4: Foo less Domino logic ci cui .
3.2. Foo ed Domino Logic Ci cui
Foo ed domino logic is a gene al o m o domino logic
ci cui . I is called so because o he p esence o a
oo e ansis o in he ci cui . The oo e ansis o is
gene ally an NMOS ansis o and shows be e noise
and leakage ole ance because o leakage educ ion due
o s acking e ec [6], [7]. The ci cui diag am o oo ed
domino logic ci cui is shown in Fig. 5.
Fig. 5: Foo ed Domino logic ci cui .
3.3. High-speed Domino Logic
Ci cui
In high speed domino logic ci cui cu en is d awn
h ough he keepe ansis o and e alua ion ne wo k
a he beginning o he e alua ion phase. Thus cu en
can be educed on applying a clock delay a keepe
ansis o [10], his leads o high speed domino logic
ci cui shown Fig. 6. This a angemen does no a ec
he leakage cu en in he ci cui ; howe e , he ex a
clock delay consumes ex a a ea and powe , which is a
big d awback o he ci cui [11].
In High-speed domino logic ci cui when he clock
becomes high, Mn1 is s ill o and Mp2 is s ill on.
The e o e, Mp2 u ns o he keepe ansis o . A e
some delay in in e e Mp2 u ns o . Now, i he dy-
namic node emains high du ing he e alua ion phase,
NMOS is u ned on which u ns on he keepe ansis-
o . Hence, a he beginning o he e alua ion phase
he dynamic node is a loa , and hence in he absence
o keepe ansis o , he e alua ion node may be dis-
cha ged o any noise a he inpu sec ion. Fu he mo e
he ol age a he ga e o he keepe ansis o is VDD-
V Mn1, which could p o ide a DC cu en low h ough
he PMOS keepe ansis o and he NMOS ne wo k.
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Fig. 6: High-speed Domino logic ci cui .
3.4. Condi ional Keepe Domino
Logic Ci cui
In mos o he high-speed iming pe o mance schemes,
inpu signals o he dynamic logic ga es a e eady jus
be o e o close o he s a o he e alua ion phase. In
such si ua ions he maximum ime slo o any ou pu
ansi ion is only a ac ion o he o al e alua ion ime,
which akes hal ime pe iod o 50 % du y cycle clock.
The e o e leakage and noise exis unnecessa ily o a
long ime a he ou pu o he ga e [12]. In he con-
en ional ci cui a s anda d keepe ansis o is used,
which is u ned on uncondi ionally a he s a o he
e alua ion phase, and akes down he pe o mance o
he dynamic logic ga e as shown in Fig. 7.
Fig. 7: Condi ional keepe Domino logic ci cui .
The condi ional keepe domino logic con ains
wo PMOS keepe ansis o ci cui s wi h a iable
s eng h. One keepe ansis o has lowe s eng h,
while he o he has highe s eng h [13]. When he dy-
namic node is a high ol age Mkp1 u ns on o a oid
he ol age d op a he dynamic node. I he dynamic
node is s ill high, hen a e a ce ain amoun o delay,
du ing he e alua ion phase, he ou pu o NAND ga e
becomes low, hus u ning on Mkp2. I mus be no ed
ha Mkp1 is esponsible o main aining he s a e o he
dynamic node, du ing he beginning o he e alua ion
phase, while Mkp2 is esponsible o i o he es o
he e alua ion phase. Ano he ype o domino ci cui
de eloped om CMOS echnology is he diode oo ed
domino logic (DFD), which educes powe consump-
ion and delay o he ci cui by inse ing he mi o
ci cui below he e alua ion ne wo k. By inse ing he
mi o , he pa h o discha ge o he dynamic node in-
c eases as shown in Fig. 8. Thus, he dynamic node
discha ges slowly and emo es he con en ion cu en
be ween he dynamic node and e alua ion ne wo k,
imp o ing he pe o mance and obus ness o he ci -
cui [6], [14], [15].
Fig. 8: Diode oo ed Domino logic.
In Leakage Con olled Replica (LCR) modi ica ion is
achie ed o e he keepe ansis o by inse ing a mi -
o ci cui in pa allel o he keepe ansis o , which
mi iga es powe consump ion and a ea o he ci cui ,
as shown in Fig. 9 [15]. This ci cui is help ul in im-
p o ing he noise immuni y o he ci cui in e alua ion
phase [16], [17].
Se e al s udies ha e been conduc ed on domino logic
o achie e as e ope a ion o he ci cui and educ ion
o powe consump ion. In he p esen s udy, a new
cu en compa ison o domino (CCD) ci cui has been
p oposed which enhances he pe o mance o he ci -
cui ; and imp o es he UNG o he ci cui by main ain-
ing i s obus ness [18]. Thus, ou p oposed ci cui is a
new class o domino ci cui wi h lowe powe and high
speed wi h cons an delay o he ci cui .
A ecen addi ion o he di e en ype o domino
ci cui is ol age compa ison ci cui which has been
de eloped, wi h domino ci cui o wide an in ga e. In
p esen s udy, he ol age swing o he dynamic node
has been educed by dec easing he powe consump ion
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Fig. 9: Leakage con olled eplica.
by hea y swing o he swi ching capaci ance [14]. All
simula ions we e pe o med wi h 90 nm echnology o
64-bi OR ga e, which sa ed 36 % powe and p o ided
2.32x noise immuni y.
4. P oposed Ci cui
In p oposed ci cui we ha e modi ied he keepe an-
sis o . Fo he educ ion o con en ion be ween he
keepe and e alua ion ne wo k, we spli he keepe
ansis o in o wo o p ope s eng h. Fu he mo e,
by sizing he keepe ansis o we educed he powe
and delay o he domino ci cui .
As shown in Fig. 10 we use Ul a Low Powe S acked
Design (ULSD) which is a combina ion o PMOS and
NMOS. ULSD achie es highe educ ion o leakage cu -
en , when compa ed wi h o he s anda d logic.
Fig. 10: Ul a low powe s acked design.
Ou p oposed ci cui wo ks in wo phases. In i s
phase when he clock pulse is 0, he ci cui emains
in p e-cha ge phase, which cha ges he dynamic node
and he ou pu o he logic is always 0. Du ing second
phase he ci cui en e s he e alua ion phase, he clock
pulse becomes 1, and i one o he inpu s o he OR ga e
is ac i e hen he dynamic node is discha ged. Subse-
quen ly ansis o MN1is is u ned ON, dynamic node
easily discha ges h ough MN1, and also MN2 ansis-
o is u ned ON as ga e ol age is high on ansis-
o MN2, dynamic node discha ges h ough e alua ion
and MN1 ansis o slowly due o ga e delays, hence
wo in e o s a e connec ed in se ies a a ga e o MN1
o p o ide delay in making MN1 ON. This will sa e
powe o he ci cui . As shown in Fig. 11 ansis o s
MN3 and MP4 y o discha ge he dynamic node o-
wa ds he g ound. The main unc ion o his ansis o
is o d aw he con en ion cu en o he PMOS keepe ,
which also speeds up he discha ging p ocess o he ca-
paci o a he dynamic node. A he beginning o he
p e-cha ge phase he p e-cha ge ansis o is in ac i e
mode and he ol age a he dynamic node will be a
0 V. This 0 V is ed o he in e e as an inpu which
makes he ou pu o he in e e as VDD. The modi i-
ca ion o he keepe ansis o helps in discha ging he
dynamic node, and he cha ge s o ed o e he dynamic
node loa s, when all he inpu s o he OR ga e a e
disconnec ed. By p o iding a p ope s acking wi h he
help o ULSD ansis o , which helps in imp o ing he
UNG o he ci cui , powe consump ion is educed and
speed is enhanced by using FinFET echnology in di -
e en mode. The ansis o s MN3, MP4 and MN2 a e
a anged as s ack ansis o s and p o ide a s acked e -
ec in pull down ne wo k, and by educing he leakage
cu en simul aneously a p ope logic le el is achie ed
as shown in Fig. 12.
Fig. 11: P oposed ci cui .
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Fig. 12: T ansien cha ac e is ics o he p oposed wo inpu
Domino OR using HSPICE in FinFET echnology.
5. Simula ion Resul s and
Discussion
The simula ion esul s we e ob ained by using BISM4,
HSPICE model a 32 nm echnology, by using P edic-
i e Technology Model (PTM). In FinFET echnology,
he ci cui is simula ed in SG and LP modes wi h 0.8 V
supply a 100 MHz equency. All simula ions we e
pe o med a oom empe a u e o 25 ◦C o all he
exis ing and p oposed ci cui s. The ISUB and IGATE
leakage cu en s a y wi h VDD and empe a u e in a
32-nm CMOS and FinFET echnology. A oom em-
pe a u e, IGATE was no ed o be 2.4 imes highe han
ISUB, wi h ou pu capaci ance, IL= 1 pF o 8 and 16
inpu OR ga e as shown in Tab. 4 and Tab. 5. Fig-
u e 11 and Fig. 12 p esen he compa ison o COMS
and SP, LP mode o FinFET echnology. The FinFET
echnology mi iga es, he a e age powe in SG and LP
modes. The keepe a io (K) is de ined as he a io o
he cu en d i abili y o he keepe ansis o o ha
o he e alua ion ansis o ,
K=
µpW
Lkeepe ansis o
µnW
Le alua ion ansis o
,(3)
whe e Wand Ldeno e he ansis o size, and µn,µp
a e he mobili y o elec on and hole espec i ely [2].
The simula ion was pe o med by se ing Mkeepe
(W/L) = 16/32 n, PMOS (W/L) =128/32 n, NMOS
(W/L) = 64/32 n and CL=1 pF o ai compa ison o
he esul s.
Table 4 and Tab. 5 show he compa ison o he a e -
age powe , delay and PDP using FinFET echnology.
I can be obse ed ha he p oposed FinFET based
ci cui sha ed maximum powe , wi h an a e age powe
11.25 % and 11.39 % in FLD, 18.76 % and 18.12 % in
HSD, 30.90 % and 34.57 % in CKD o 8 inpu OR
ga e in SG and LP modes o he FinFET echnology.
Fu he mo e, he sa ing o he delay was 24.31 % and
13.18 % in FLD, 53.19 % and 46.79 % in FDL, 20.60 %
and 10.34 % in HSD, 29.34 % and 24.99 % in CKD o
8 inpu OR ga e in SG and LP mode o FinFET ech-
nology espec i ely. The sa ing o he a e age powe o
he p oposed ci cui was 15.60 % and 14.86 % in DFD
and 13.93 % and 17.64 % in LCR o 8 and 16 inpu
OR ga e espec i ely.
Subsequen ly, he Uni Noise Gain (UNG) o he ci -
cui was calcula ed (Tab. 6) by applying na ow wid h
o pulse ha ing 50 ps and measu ing he ampli ude a
he ou pu o he ci cui . I he ampli ude ob ained
a he inpu and ou pu was he same, we conside ed
as he UNG o he ci cui . UNG can be de ined as
he ampli ude o he inpu noise ha causes he same
ampli ude o noise a he ou pu :
UNG = {Vnoise;Vnoise =Vou }.(4)
UNG is in e sely p opo ional o he leakage cu en .
As shown in Tab. 6 he p oposed ci cui p esen ed
highe UNG han he exis ing ci cui , which was, 0.382
in SG mode and 0.532 in LP mode. Howe e , he UNG
was lowe in LP mode due o e e se biase o he pull
down ne wo k o he ci cui which educed he leakage
powe o he ci cui .
In he s andby powe , he e alua ion ne wo k o he
ci cui is u ned o and he p echa ge ansis o comes
in o he exis ence. Subsequen ly, he PMOS o he
ansis o u ns on and cha ges he dynamic node. As
dynamic node does no acqui e any pa h o discha ge
he ol age, he ola ge is loa s o e hedynamic node
Tab. 4: Calcula ion o a e age powe , delay and PDP o 8 inpu OR ga e in SG and LP mode using FinFET echnology.
A e age Powe (µW) Delay (pS) PDP (aJ)
SG Mode LP Mode SG Mode LP Mode SG Mode LP Mode
FLD 0.1200 0.0316 9.635 8.243 1.156 0.2608
FDL 0.0776 0.0242 15.58 13.45 0.492 0.0119
HSD 0.1306 0.0342 9.185 7.982 1.199 0.3987
CKD 0.1537 0.0428 10.32 9.541 1.586 0.4083
DFD 0.1256 0.0345 9.723 8.934 1.215 0.2997
LCR 0.1234 0.0324 9.854 9.251 1.215 0.2997
P oposed
Ci cui 0.1062 0.0280 7.292 7.156 0.774 0.0216
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Tab. 5: Calcula ion o a e age powe , delay and PDP o 16 inpu OR ga e in SG and LP mode using FinFET echnology.
A e age Powe (µW) Delay (pS) PDP (aJ)
SG Mode LP Mode SG Mode LP Mode SG Mode LP Mode
FLD 0.142 0.038 10.235 9.317 1.461 0.364
FDL 0.096 0.027 19.94 15.34 1.914 0.426
HSD 0.157 0.039 10.02 9.254 1.460 0.362
CKD 0.183 0.049 11.01 10.25 1.883 0.506
DFD 0.148 0.041 10.94 9.89 1.619 0.066
LCR 0.153 0.045 11.03 10.32 1.728 0.464
P oposed
Ci cui 0.126 0.032 8.384 8.945 1.058 0.0273
Tab. 6: Calcula ion o UNG, s andby powe and e alua ion delay o 8 inpu OR ga e in SG and LP mode using FinFET echnology.
UNG S andby Powe (µW) E alua ion Delay (ps)
SG Mode LP Mode SG Mode LP Mode SG Mode LP Mode
FLD 0.293 0.282 0.091 0.014 6.333 5.124
FDL 0.352 0.337 0.046 0.010 12.05 11.324
HSD 0.314 0.289 0.105 0.018 6.461 5.0129
CKD 0.325 0.294 0.127 0.025 7.031 5.1455
DFD 0.316 0.310 0.103 0.024 6.217 5.935
LCR 0.338 0.298 0.093 0.021 6.753 6.255
P oposed
Ci cui 0.382 0.352 0.080 0.009 5.193 4.615
and his powe is known as s andby powe . As shown in
Tab. 6, he p oposed ci cui , achie ed maximum sa ing
o s andby powe wi h 37.0 % and 96.4 % CKD in SG
and LP modes o FinFET echnology, espec i ely. I
can be no ed ha he sa ing o s andby powe was
e y high in LP mode when compa ed wi h ha in
SG mode due o e e se bias o he pull down ne wo k
which inc eased he h eshold ol age o he ansis o
and educed he leakage powe o he ci cui .
Fu he mo e, calcula ion o he E ala ion delay e-
ealed ha he p oposed ci cui sa ed maximum de-
lay (Tab. 6), which inc eased he speed o he ci cui .
When CLK=1 he ci cui en e ed he e alua ion phase,
he dynamic node ied o discha ge h ough he e alu-
a ion ne wo k and he cu en lowed om minimum e-
sis ance pa h. The ime aken by he dynamic node o
discha ge is known as e alua ion delay. The p oposed
ci cui p esen ed imp o ed e alua ion delay when com-
pa ed wi h o he exis ing ci cui s in low-powe ci cui
design.
5.1. Powe Analysis
I he e a e many pulses, hen bu e equen ly u ns
on and o . The powe consump ion o he logic ci cui
in con en ional ci cui can be gi en as ollows.
Pa g =K·VDD2·Cdyn + · ·VDD ·Vnoise ·Cdyn,(5)
whe e
=Ton
(Ton +To ).(6)
Ton is he ime when he inpu logic is on, To is he
ime when he inpu logic is o , Kis he p obabili y o
he s a e ha he inpu logic changes in a uni ime,
Cdyn is he capaci o in dynamic node and Vnoise is he
pulse in dynamic node.
Figu e 13 shows he compa ison o CMOS and Fin-
FET Technology, om he Fig. 12. We obse e ha
powe consump ion o CMOS echnology is huge in
compa ison wi h SG and LP mode o FinFET ech-
nology his is because, FinFET echnology has h ee
dimensional s uc u e, whe e cu en lows e ically,
whe e CMOS is a plana de ice, whe e cu en lows
ho izon ally wi h espec o he channel. In Fig. 14
i is obse e ha FinFET echnique ha e lowe delay
han CMOS and p oposed ci cui sa e powe and delay
wi h o he exis ing ci cui o 8 inpu domino OR ga e.
Fig. 13: A e age powe compa ison CMOS and FinFET o 8
inpu s OR Ga e (SG, LP modes).
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Fig. 14: Delay compa ison CMOS and FinFET o 8 inpu s OR
Ga e (SG, LP modes).
6. Conclusion
In his pape we discussed abou FinFET and ecen
domino ci cui s design o enligh en ou knowledge.
He e in UDSM echnology FinFET based domino logic
ci cui is p oposed. Va ious exis ing domino logic ci -
cui s along wi h ou p oposed ci cui we e simula ed we
obse ed ha FinFET based domino ci cui is as e
and consume less powe han he bulk CMOS de ice.
The new ci cui echnique was ound o educe he
powe consump ion up o 32 % and 38 % wi hou sac-
i icing he speed o he ci cui . The p oposed ech-
nique can be applied on high pe o mance, low powe
applica ions, whe e leakage is a majo conce n such
as mic op ocesso s, memo y uni s, and o he po able
de ices. Thus, FinFET echnology can comple ely e-
place CMOS by main aining he law o echnology scal-
ing. Mo eo e , FinFET echnology educes he size o
he ansis o by up o 10 nm, he p ocess pa ame-
e s such as ol age and empe a u e can be a ied
wi h he scaling o echnology. In u u e, we can im-
plemen nex -gene a ion domino ci cui using ca bon
nano ubes, which has ad an ages such as low powe ,
high speed and smalle a ea o 10 nm - 7 nm.
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Abou Au ho s
Ajay Kuma DADORIA ecei ed B.Sc. (Elec-
onics and Communica ion) in 2009 om Go e men
Enginee ing College Ujjain and M.Sc. in Hono s in
2012 wi h specializa ion in Ve y La ge Scale In e-
g a ion (VLSI) and Embedded Sys em om MANIT
Bhopal, Cu en ly he is pu suing Ph.D. in Elec onics
and Communica ion in Maulana Azad Na ional
Ins i u e o Technology (MANIT), Bhopal. His a ea
o in e es is Design and De elopmen o Low powe
high speed con igu a ion o po able de ices.
Ka i a KHARE ecei ed he B.Sc. deg ee in
Elec onics and Communica ion Enginee ing in 1989,
M.Sc. deg ee in digi al communica ion sys ems in
1993, and he Ph.D. deg ee in he ield o VLSI
design in 2004. Cu en ly, she is wo king as P o esso
in Elec onics and Communica ion Enginee ing in
MANIT, Bhopal, India. He ields o in e es a e VLSI
design and communica ion sys ems. He esea ch
mainly includes Design o a i hme ic ci cui s and
a ious communica ion algo i hms ela ed o synch o-
niza ion, es ima ion and ou ing. She has nea ly 150
publica ions in a ious in e na ional con e ences and
jou nals.
Ta un Kuma GUPTA ecei ed B.Sc. (Elec-
onics and Communica ion) in 2001, M.Sc. deg ee in
Digi al Sys ems in 2003, and he Ph.D. deg ee in he
ield o VLSI design in 2013. Cu en ly, he is wo king
as Assis an P o esso in Elec onics and Communi-
ca ion Enginee ing in MANIT, Bhopal, India. His
ields o in e es a e Low powe VLSI design and
semiconduc o de ices. His esea ch mainly includes
implemen a ion o low powe dynamic ci cui s. He
has nea ly 25 publica ions in a ious in e na ional
con e ences and jou nals.
R. P. SINGH ecei ed he B.Sc. Enginee ing
deg ee in Elec onics Enginee ing om Ins i u e o
Technology, Bana as Hindu Uni e si y (IT BHU)
in 1971. In 1973, M.Sc. Enginee ing deg ee in IT
BHU and he Ph.D. deg ee in he ield o Elec onics
Enginee ing in 1991. Cu en ly, he is wo king as P o-
esso in Elec onics and Communica ion Enginee ing
in MANIT, Bhopal, India. His ields o in e es a e
communica ion sys ems and esea ch mainly includes
a ious communica ion algo i hms ela ed o synch o-
niza ion, es ima ion and ou ing. He has nea ly 200
publica ions in a ious in e na ional con e ences and
jou nals.
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