P oyec o Fin de Ca e a
Ingenie ía de Telecomunicación
Fo ma o de Publicación de la Escuela Técnica
Supe io de Ingenie ía
Au o : F. Ja ie Payán Some
Tu o : Juan José Mu illo Fuen es
Dep. Teo ía de la Señal y Comunicaciones
Escuela Técnica Supe io de Ingenie ía
Uni e sidad de Se illa
Se illa, 2013
T abajo Fin de Más e
Más e en Ingenie ía Ae onáu ica
Design and Modelling o a
Bidi ec ional DC-DC Con e e
based on Full B idge Cu en
Double Topology o Ae onau ical
Applica ions
Au o : Ál a o de Jesús Ojeda Rod íguez
Tu o : Ma ía Ángeles Ma ín P a s
Ingenie ía Elec ónica
Escuela Técnica Supe io de Ingenie ía
Uni e sidad de Se illa
Se illa, 2019
T abajo Fin de Más e
Más e en Ingenie ía Ae onáu ica
Design and Modelling o a Bidi ec ional
DC-DC Con e e based on Full B idge
Cu en Double Topology o
Ae onau ical Applica ions
Au o :
Ál a o de Jesús Ojeda Rod íguez
Tu o :
Ma ía Ángeles Ma ín P a s
P o eso a Ti ula
Ingenie ía Elec ónica
Escuela Técnica Supe io de Ingenie ía
Uni e sidad de Se illa
Se illa, 2019
T abajo Fin de Más e : Design and Modelling o a Bidi ec ional DC-DC Con e e
based on Full B idge Cu en Double Topology o
Ae onau ical Applica ions
Au o : Ál a o de Jesús Ojeda Rod íguez
Tu o : Ma ía Ángeles Ma ín P a s
El ibunal nomb ado pa a juzga el abajo a iba indicado, compues o po los siguien es
p o eso es:
P esiden e:
Vocal/es:
Sec e a io:
acue dan o o ga le la cali icación de:
El Sec e a io del T ibunal
Fecha:

Acknowledgemen s
This p ojec would no exis wi hou he encou agemen om a lo o people.
I would like o hank my pa en s, and also my whole amily, o hei cons an
suppo . They always help me o ake he bes decision. They always help me o be a
be e pe son.
I would also like o ank my colleague and iend Pablo González o his in aluable
collabo a ion. He knows how o see he bes ace o Powe Elec onics.
I could no o ge o hank p o esso s Ma ía Ángeles Ma ín and Joaquín Be nal,
who ga e me he oppo uni y o ake pa in his s udy and wo k wi h hei esea ch
g oup.
Finally, I would like o emembe all my iends, all my p o esso s, because
each one, om his posi ion, ha e helped me o each he objec i e: Ae onau ical
Enginee ing.
I
Abs ac
This p ojec alls wi hin he amewo k o he esea ch abou Mo e Elec ic
Ai c a (MEA) concep , which is he a ge o he cu en designs. In his con ex ,
elec ical sys em is being ein o ced as one o he main powe sys ems. Elec ical
powe le el and ol age le el ansmission a e inc easing – he las one is ending o
High Vol age Di ec Cu en (HVDC) le el– and equi emen s o gene a ion, dis ibu-
ion, managemen and con ol o his kind o powe a e becoming mo e and mo e
challenging.
Wi hin elec ical sys em, powe con e e s a e esponsible o elec ical powe
ansmission. Mo eo e , hey mus ul il ae onau ical s anda ds in espec o on-boa d
elec ical and elec onic sys ems. The p ecise aim o his p ojec is o s udy sui -
able opologies o DC-DC bidi ec ional and isola ed powe con e e s wi hin de ined
amewo k. Many indus ies, as ae onau ical o au omo i e, eques hem wi h be e
ea u es – o ins ance, powe densi y and e iciency a e c i ical KPI in ae onau ical
indus y–. A e a e iew o main powe ci cui s ha could ul il speci ica ions o hese
applica ions, a p omising opology will be analysed om a nume ical poin o iew.
Pa icula ly, Bidi ec ional Cu en Double is he opology subjec o s udy. I s
wo king p inciple will be analysed unde ce ain ope a ing ange domain. Simula ion
models will be de eloped o asses opology pe o mance in such ope a ing domain.
By knowing cu en s and ol ages on ideal elemen s, a mo e ealis ic componen s
selec ion will be ca ied ou , pa icula ly as a as MOSFETs conce ns. Finally, ega ding
a mo e li le bi accu a e model, e iciency will be calcula ed in e ms o inpu and
ou pu powe .
III
X Ac onyms
MEA Mo e Elec ic Ai c a .
PDS Powe Dis ibu ion Sys em.
PSM Phase Shi Modula ion.
PSPICE Pe sonal Simula ion P og am wi h In eg a ed Ci cui s Emphasis.
R&D Resea ch and De elopmen .
RMS Roo Mean Squa e.
SESAR Single Eu opean Sky ATM Resea ch.
SJU SESAR Join Unde akinhg.
SPRC Se ies-Pa allel Resonan Con e e .
SR Synch onous Rec i ica ion.
TRU T ans o me Rec i ie Uni .
VDC Vol s Di ec Cu en .
ZCS Ze o Cu en Swi ching.
ZVS Ze o Vol age Swi ching.

Symbols
∆ILDC2a+2b Peak- o-peak o al cu en h ough LV side induc o s.
Coss Mos e ou pu pa asi ic capaci ance.
Csnb Snubbe capaci ance.
DDu y cycle.
sSwi ching equency.
IAC1 T ans o me cu en a HV side.
IAC2 T ans o me cu en a LV side.
ILDC2a DC induc o cu en .
LLeakage induc ance.
LDC DC induc o .
LmMagne izing induc ance.
nT ans o me u n a io.
P2Nominal powe a low ol age side.
Rdclamped Ohmic esis ance clamped diode.
RDSon Ohmic swi ch esis ance when i is conduc ing.
RLDC Ohmic esis ance DC induc o .
XI
XII Symbols
RmMagne izing esis ance.
Rsnb Snubbe esis ance.
T1 Semiconduc o HV side 1.
T2 Semiconduc o HV side 2.
T3 Semiconduc o HV side 3.
T4 Semiconduc o HV side 4.
T5 Semiconduc o LV side 5.
T6 Semiconduc o LV side 6.
TCSwi ching ime.
Tdead Dead ime.
T ee F eewheeling ime.
TSSwi ching pe iod.
V1High ol age.
V2Low ol age.
VAC1 T ans o me ol age a HV side be o e leakage induc ance.
VAC2 T ans o me ol age a LV side.
Vaux Auxilia y ol age sou ce.
Vdclamped Fo wa d ol age d op clamped diode.
Vdswi ch Vol age d op ac oss swi ch an ipa allel diode.
VDS Mos e d ain o sou ce ol age d op.
VLVol age d op h ough leakage induc o .
Chap e 1
In oduc ion
1.1 Gene al p esen a ion o he s udy
Cu en ly, i is a ac ha
Mo e Elec ic Ai c a
(MEA) is no he u u e bu he
p esen . So R&D ends o ai c a designs ha in ol e highe powe le el, [
1
]. This
a ec s o powe gene a ion, ansmission, managemen and con ol. A good example
could be ai c a Ai bus A350 and Boeing B787
D eamline
. The i s one comes wi h
ou independen a iable equency gene a o s, each one o 100 kVA, [
2
]. The second
one is i ed wi h ou a iable equency gene a o s, each one o 250 kVA, [
3
], [
4
].
F om he elec ical powe gene a ed on-boa d poin o iew, Boeing
D eamline
is
close o MEA concep han Ai bus A350, since he i s one gene a es mo e han wice
he elec ical powe han he las one.
As a as sa e y, eliabili y and echnological ad ances conce ned, ae onau ics
is pe haps one o he mos challenging indus ies. Issues ela ed o weigh and size
educ ion, powe densi y and e iciency a e also especially impo an . Because o his,
elec ical sys ems and elec ical/elec onics de ices a e equi ed o be:
Ve y e icien .
Wi h high powe densi y.
Inc easing e iciency will help o educe en i onmen al impac , and also dec ease
ope a ing cos . In e na ional o ganisa ions, like SESAR Join Unde aking (SJU),
conside his R&D asks se iously and he e o e hey suppo many esea ch p ojec s
1
2 Chap e 1. In oduc ion
in his ield –and in many o he s ha could be ela ion wi h imp o ing e iciency, sa e y,
and so on–like Clean Sky p og ams.
Powe Elec onics is he subjec ha aces such a challenging ask. A good
de ini ion o Powe Elec onics is gi en by [5] :
“Powe elec onics in ol es he s udy o elec onics ci cui in ended o
con ol digi ally he low o elec ical ene gy. These ci cui s handle powe
low a le els much highe han he indi idual de ice a ings”.
Powe elec onics basic module is powe con e e . This elec onic ci cui
con ains swi ches (e.g. semiconduc o s), ene gy s o age elemen s (e.g. induc o s,
capaci o s) and ans o me s. An ex e nal con ol unc ion commands he swi ches
acco ding o he inpu ecei ed om he load and powe con e e s a e.
Rega ding he ype o elec ical powe a inpu and ou pu o powe con e e ,
a numbe o di e en kinds o con e e s exis s:
AC o DC con e e , also called ec i ie .
DC o AC con e e , also called in e e .
AC o AC con e e .
DC o DC con e e .
In o de o imp o e eliabili y and sa e y, elec ical powe gene a ion has been
mo ed om DC o AC, [
1
]. This change in opology inc eased he powe densi y due o
he bene i s o AC gene a o s, wi h he consequen size and weigh educ ion. Howe e ,
powe dis ibu ion in new ai c a designs ends o include a hyb id PDS wi h DC and
AC buses, in o de o supply powe o all ype o loads, [
3
]. Figu e 1.1 shows an
example o MEA elec ical powe sys em a chi ec u e.
1.1. Gene al p esen a ion o he s udy 3
Figu e 1.1: Gene ic elec ical a chi ec u e o MEA concep o ai c a , [6]
As i s conc e e s ep, p esen wo k will be ocused on HVDC o LVDC bidi ec ional
powe con e e . Typical nominal ol age le els a e p esen ed in Figu e 1.1: 270 VDC
a HVDC and 28 VDC a LVDC. Mo e p ecisely, his esea ch will e iew isola ed and
bidi ec ional powe elec onic ci cui s - opologies-. The S a e-o - he-a e ision goal
is o selec a p omising opology ha suppo s HVDC and LVDC anges men ioned
abo e. Applica ion anges a e desc ibed in de ail in Chap e 4.
This opology will be used o buil low powe modula b icks, whe e low powe
means ew kilowa s. I he applica ion equi es high powe ans e o high ol age
le els, b icks can be connec ed o ming a
cascaded mul i-con e e
, [
7
]. Each b ick
only handles a ac ion o he o al powe . Con e e b icks can be se in di e en
con igu a ions: i he b ick e minals a e connec ed in pa allel, hey will sha e he
DC line cu en ; in he o he hand, i b ick e minals a e connec ed in se ies, DC line
ol age is dis ibu ed among hem. The op imum choice depends on he applica ion.
Hence, despi e o he ol age and powe anges a e limi ed o magni ude o de
men ioned be o e, his esea ch keeps u ili y o applica ions whe e high powe and
inpu /ou pu ol ages a e in ol ed.

4 Chap e 1. In oduc ion
1.2 Documen s uc u e
A he i s place a condensed bu ai ly comple e S a e-o - he-a has been
ca ied ou explo ing he main a ailable bidi ec ional and isola ed opologies o DC
o DC powe con e sion a ce ain HVDC and LVDC nominal le els, Chap e 2.
Chap e 3 desc ibes b ie ly he key heo e ical ideas o unde s anding he
pe o mance and physical ope a ion o he powe elec onics ci cui . A de ailed
explana ion o wo basic ope a ing modes o con e e will be exposed, gi ing wa e o m
examples and desc ibing he con ol o swi ches.
Buck mode.
This is he mos usual wo king mode o such opology. The objec i e
is powe ans e om HVDC o LVDC.
Boos mode.
CDR is no widely used o his unc ion: ans e powe ising
ou pu ol age le el o high alues om low ol age inpu le el.
This heo e ical app oach will be based on he ci cui shows in Figu e 3.2. Powe
con e e will be connec ed a LV side ei he o load ha equi es LVDC powe supply
o LVDC ne wo k ha impose cons an ol age le el. The same occu s a HV side.
Chap e 4 ocuses on e iewing he main speci ica ions and c i e ia design ha
will cons i u e he s a ing poin o ob ain a i s es ima ion o main magni udes.
Chap e 5, "Design o Componen s", desc ibed he main componen s o he
powe ci cui and how hey ha e been modelled.
A ligh desc ip ion o nume ical models and comme cial so wa e use o he
simula ion is con ained in Chap e 6.
Chap e 7 collec s he esul s o he whole s udy, which will be p esen ed in
di e en o ma s: g aphics, ables, e c. Some o he expec ed esul s a e:RMS cu en s
h ough magne ics componen s and capaci o s, and i s o de es ima ions o e iciency.
All hese esul s will be p o ided wi hin he ope a ing ange p o ided by speci ica ions.
A he end, Chap e s 8 "Conclusions" and 9 "Fu u e Wo k" sum up he main
and mo e in e es ing ideas o he esea ch and also e iew hose issues ha due
o lack o ime could no be comple ely sol ed. Mo eo e , some sugges ions will be
p oposed as "wo k guidelines", i.e. pa ame e s op imiza ion and unc ional p o o ype
manu ac u ing o compa e expe imen al esul s wi h nume ical ones.
1.3. S udy objec i es 5
1.3 S udy objec i es
Main s udy goals a e summed up below.
Compa e opologies ha ul il essen ial equi emen s –high e iciency and high
powe densi y– o on-boa d elec ic and elec onics powe sys ems, as well
as ope a ing ange de ined by ae onau ical applica ion in he MEA concep
amewo k.
Selec a p omising opology and analyse i om a heo e ical app oach and also
om a nume ical app oach.
Using a single model wi h lossless componen s, es ima e ol age and cu en
le els o e hem. Accomplish an ini ial ealis ic componen s selec ion wi h his
in o ma ion, which wi hs and ol age and cu en maximum a ings.
Finally, elabo a e a sligh ly mo e ad anced simula ion model in o de o calcula e
e iciency a ce ain ope a ing poin s.
Chap e 2
S a e-o - he-a analysis
This chap e is a e iew on a ailable DC o DC powe con e e s, based on
isola ed and bidi ec ional opologies which a e able o ans e powe wi hin he ange
o 1-5 kW, [8]. They also suppo well nominal wo king HVDC and LVDC anges.
Hence he p esen ed S a e-o - he-a ocuses on some speci ic powe ci cui s
and excludes o he ones ha do no sui so well hose speci ica ions.
2.1 Gene al a chi ec u e o DC o DC con e e
A gene al con igu a ion o a bidi ec ional DC o DC con e e wi h gal anic
isola ion is shown in Figu e 2.1.
7
14 Chap e 2. S a e-o - he-a analysis
2.3.1. Swi ches
Fo each swi ch his a ing is calcula ed wi h Equa ion 2.1, [8]:
Sswi ch =max(Vswi ch,peak)·max(Iswi ch)(2.1)
Whe e max(
Vswi ch,peak
) is he maximum ol age applied o he swi ch and
max(Iswi ch) is he maximum RMS cu en h ough he swi ch, [8].
2.3.2. T ans o me
Fo a single-phase ans o me wi h
m
windings ope a ed wi h sinusoidal ol -
ages and cu en s, VA a ing is calcula ed using Equa ion 2.2, [8]:
S =1
2
m
X
i=1
ˆ
V ,i·ˆ
I ,i(2.2)
Whe e
ˆ
V ,i
deno es RMS ol age applied o he
i
- h winding and
ˆ
I ,i
makes
e e ence o RMS cu en h ough he i- h winding, [8].
Ne e heless, discussed DC o DC opologies do no employ pu ely sinusoidal
wa e o ms. So he sui able modi ied exp ession is Equa ion 2.3, [8]:
S =1
2
m
X
i=1
ˆ
V ,i,eq ·ˆ
I ,i,eq (2.3)
Whe e ˆ
V ,i,eq and ˆ
I ,i,eq a e de ined as Equa ions 2.4 and 2.5 s a e, [8].
ˆ
V ,i,eq =πD
p2V1(2.4)
ˆ
I ,i,eq =ˆ
I ,i(2.5)
Rega ding ma hema ical de ini ion abo e, conside ed i ems o compa ison a e
going o be enume a ed.

2.3. Topologies compa ison 15
Numbe o componen s.
•Ac i e ones.
•Magne ic ones.
Swi ches:
•VA a ing sum o LV side.
•VA a ing sum o HV side.
T ans o me :
•Maximum RMS cu en .
Induc o s:
•Maximum DC cu en .
•Maximum RMS cu en .
•Peak ene gy.
Capaci o s:
•Peak ene gy.
•RMS cu en .
O he conside a ions:
•P e-cha ge issues.
•Modula ion complexi y.
•Snubbe equi ed.
Table 2.1 sums up he inal compa ison be ween conside ed opologies.
16 Chap e 2. S a e-o - he-a analysis
Table 2.1: Topologies compa ison, [8]
Topology Ad an ages Disad an ages
DAB
(Con . Mod.)
Lowes componen
coun .
A oids DC induc o .
Simple modula ion.
Limi ed ZVS ange.
T ans o me la ge
cu en s.
LV DC capaci o : e y
la ge RMS cu en .
DAB
(Op . Mod.)
Lowes componen
coun .
A oids DC induc o .
Reduced ci cula ing
cu en .
Reduced capaci o
RMS cu en s.
HV side swi ches: ull
ange ZVS.
LV side swi ches: ull
ange ZCS.
achie able.
Complex modula ion.
LV DC capaci o :
la ge RMS cu en .
Th ee-Phase DAB
Compa a i ely low
capaci o RMS
cu en s.
A oids DC induc o s.
Reduced ci cula ing
cu en s.
Limi ed ZVS ange.
High componen
coun .
LV DC capaci o :
ah e la ge RMS
cu en s.
LLC
(Con . Mod.)
Sligh ly educed
componen s esses
compa ed o he DAB.
A oids DC induc o s.
Simple modula ion.
La ge L and C.
Limi ed ZVS ange.
T ans o me : la ge
ci cula ing cu en s.
LV DC capaci o : e y
la ge RMS cu en s.
2.3. Topologies compa ison 17
Topology Ad an ages Disad an ages
LLC
(Op . Mod.)
A oids DC induc o s.
Reduced ci cula ing
cu en s.
Reduced capaci o
RMS cu en s.
HV side: ull ange
ZVS.
LV side swi ches: ull
ange ZCS achie able.
Ra he la ge L and C.
LV DC capaci o :
la ge RMS cu en s.
Complex modula ion.
Full B idge Con e e
Cu en
Fed Full
B idge
LV side DC capaci o :
low RMS cu en s.
HV side: ull ange
ZVS.
La ge DC induc o
equi ed.
Snubbe may be
needed.
Limi ed ope a ing
ol age ange.
Cu en
Double
Lowes ans o me
cu en s: lowes
losses in con ac
esis ances (e.g.
ans . e minal).
Lowes swi ches
cu en s: be e
MOSFETs a ailable
(lowe losses).
LV side: no high-side
ga e d i e s.
LV side DC capaci o :
low RMS cu en s.
HV side: ull ange
ZVS.
Inc eased
ans o me VA
a ing.
La ge DC induc o s
equi ed.
Snubbe may be
needed.
Limi ed ope a ing
ol age ange.
18 Chap e 2. S a e-o - he-a analysis
Topology Ad an ages Disad an ages
Cu en
Fed Push
Pull
LV side: no high-side
ga e d i e s.
LV side DC capaci o :
low RMS cu en s.
HV side: ull ange
ZVS.
Inc eased
ans o me VA
a ing.
La ge DC induc o
equi ed.
Snubbe may be
needed.
Limi ed ope a ing
ol age ange.
Rega ding his compa ison, a p omising powe ci cui selec ed o s udying is
he Full B idge wi h Cu en Double .
Chap e 3
Wo king p inciple desc ip ion
The opology selec ed o he s udy is
Bidi ec ional and Isola ed DC o DC
Phase Shi Con e e wi h Cu en Double Rec i ie (CDR)
. The e a e some key-
wo ds ha con ain e y impo an in o ma ion abou his opology.
Bidi ec ional Con e e (BDC)
. Fi s , he con e e is able o ans e powe in
bo h di ec ions. A simple way o achie e his ea u e would be modi y con-
en ional opologies by eplacing ec i ie diodes wi h bidi ec ional swi ches.
The e o e, i is possible o he con e e o wo k in buck mode –HVDC o LVDC
–; and boos mode –LVDC o HVDC –.
Phase Shi Modula ion (PSM)
. Phase shi modula ion is an elemen a y modula-
ion scheme whose pa ame e con ol is du y cycle (D).
Cu en Double Rec i ie (CDR)
. Low ol age side has o wi hs and high cu en
alues. Mo eo e , he highe powe is eques ed, he highe cu en is – he
ol age le el is es ablished by speci ica ions –.
19

20 Chap e 3. Wo king p inciple desc ip ion
Full B idge Cu en Double
Figu e 3.1: Cu en double ec i ie o iginal opology, [8]
Figu e 3.1 shows he basic opology which mee s all hose ea u es men ioned
abo e. Ne e heless, a change will be in oduced in he opology in o de o limi
ol age spikes a LV swi ches (T5 and T6) due o ha d u n-o . The esul ing opology
is shown in Figu e 3.2.
V
aux
Figu e 3.2: Cu en double ec i ie modi ied opology, [8]
I is impo an o no ice ha V
1
ep esen s high ol age DC le el (HVDC) and V
2
ep esen s low ol age DC le el (LVDC).
Looking inside he opology, he e is a semiconduc o s ull b idge a HV side
and a cu en double a LV side. T ansis o s a e needed ins ead o diodes in o de o
make a bidi ec ional powe ans e .
T ans o me , ep esen ed by wo coupled induc o s, p o ides gal anic isola ion
be ween high and low ol age sides. Induc o connec ed in se ies wi h ans o me
21
HVDC winding emphasizes he leakage induc ance, ep esen ed by "L".
Rega ding he gene al a chi ec u e o bidi ec ional and isola ed DC o DC con-
e e , Figu e 2.1, ci cui in Figu e 3.2 also inco po a es a basic il e ne wo k consis ing
o a capaci o connec ed in pa allel wi h HVDC and LVDC.
Some o hese elemen s ha e o be dimensioned o mee speci ica ions and
design c i e ia. This aspec will be add essed la e .
As explained below, powe ans e is con olled by swi ches s a es. A modula-
o u ns on and u ns o swi ches acco ding o he PSM echnique and i s con ol
pa ame e .
Mo eo e , some basic ideas mus emain as unde lying aspec s o he cu en
heo e ical app oach:
Swi ches a e conside ed ideal, so swi ching will be assumed ins an aneous. This
simpli ies pe o mance desc ip ion and wa e o m analysis.
Swi ches on he seconda y side (HV o LV side, depends on he ope a ing mode)
a e in ended o ac as powe ec i ie s. This physical beha iou is called
Syn-
ch onous ec i ica ion, SR.
Rega ding which side is powe ed, i is possible o dis inguish wo basic modes
o ope a ion:
Boos mode. LVDC o HVDC.
Buck mode. HVDC o LVDC.
These ope a ing modes a e explained in de ail sepa a ely. Fo bo h modes, he ollow-
ing ela ionship be ween V1, V2and D applies (Equa ion 3.1), [11]:
D=2nV 2
V1(3.1)
22 Chap e 3. Wo king p inciple desc ip ion
3.1 S eady S a e Analysis
The s udy will be ca ied ou wi h a ixed du y cycle. A basic physical analysis o
he ci cui will be exposed. The explana ion will be ca y ou conside ing a swi ching
pe iod (TS). Fou basic s a es a e desc ibed du ing a pe iod.
3.1.1. Buck mode
Tu ning-on and u ning-o he igh swi ches a he igh ime allows he ol age
wa e o m in he ans o me shown in Figu e 3.7 which is necessa y o pe o m a
ol age educ ion ( om V1 o V2).
Powe deli e y mode ( 0→ 1)
Du ing his ime T1 is ON, T2 is OFF, T3 is OFF and T4 is ON. The cu en lows
h ough ac i e semiconduc o s in HV side, as i is shown in Figu e 3.3. To allow powe
ans e , T5 is OFF and T6 is ON. This ime in e al is app oxima ely D·TS
2. [12]
V
aux
Figu e 3.3: Powe Deli e y Mode, [13]
A his in e al o ime cu en h ough ans o me inc eases. The ela ion
be ween cu en and ol age is gi en by he Equa ions 3.2 and 3.3.
VAC1 =VAC2 ·n+VL(3.2)
3.1. S eady S a e Analysis 23
VL=L·dIAC1
d (3.3)
This beha iou is e i ied acco ding o Figu e 3.7. The slope o cu en h ough
ans o me is posi i e.
F eewheeling Mode ( 1→ 2)
The nex in e al o ime s a s when T4 is u ned o . I is cha ac e ized by he
ollowing HV side semiconduc o s s a es: T1 ON, T2 OFF, T3 ON and T4 OFF. In LV side
bo h swi ches a e ON. The cu en pa h is d a ed in Figu e 3.4. [12]
V
aux
V
aux
Figu e 3.4: F eewheeling Mode, [13]
In his case, he e is no ne inpu cu en . Mo eo e , he slope o cu en
h ough ans o me is nega i e. Seconda y ol age (V
AC2
) is closed o ze o. This
second in e al ends a he middle o he cycle, i.e. TS
2.
Powe Deli e y Mode ( 2→ 3)
The hi d global s a e o he HV side semiconduc o b idge is de e mined byT1
OFF, T2 ON, T3 ON and T4 OFF. Wi h his con igu a ion inpu cu en is allow o low,
as i is shown in Figu e 3.5. In his case, T5 is equi ed o be ON and T6 OFF. [12]
30 Chap e 3. Wo king p inciple desc ip ion
Fundamen al magni udes illus a ion
-500
-400
-300
-200
-100
0
100
200
300
400
500
VAC1
IAC2
ILDC2a
ILDC2b
0
1
T1
T2
0
1
T3
T4
0
1
T5
T6
Ts
F eewheeling
Powe deli e y
AC
2
n·V
0 1 2 3
Figu e 3.13: T ans o me and DC induc o s magni udes - Boos mode

3.1. S eady S a e Analysis 31
In he i s place, i is qui e appa en ha in boos mode diodes allow cu en o
low du ing sho in e al ime; his phenomena esul s in an o e ol age on LV side o
he ans o me . O e ol age does no appea in Figu e 3.7. The maximum alue is
limi ed by ac i e snubbe auxilia y ci cui , i.e. clamped diodes and V
aux
which is se o
150 V.
T ans o me cu en wa e o m is also di e en in boos and buck mode. Du ing
powe deli e y mode, cu en dec eases - ega ding absolu e alue- in boos mode
and inc eases in buck mode. Du ing eewheeling pe iod his magni ude is closed o
ze o in boos mode, and i is no in buck mode.
-20
-10
0
SWITCHES CURRENT - BOOST
T
1
T
2
-20
-10
0
T
3
T
4
0
50
100
T
5
T
6
Figu e 3.14: Cu en h ough swi ches - Boos mode
In boos case, cu en wa e o ms o (T1, T2) and (T3, T4) a e mo e simila each
o he han in buck case.
32 Chap e 3. Wo king p inciple desc ip ion
3.2 Phase-Shi ed Modula ion
In his sec ion modula ion echnique is ou lined b ie ly. The basic con ol
p inciples a e desc ibed:
Swi ches in he same leg ne e a e swi ched on a he same ime. Hence, he
du y cycle be ween hem is almos 50%, because i is necessa y o keep a delay
ime, also called
dead ime
, be ween he swi ch-on o one and he swi ch-o o
he o he -o he same b anch-.
Swi ches pai s o he wo legs o HVDC ull b idge a e delay ce ain ime. This ime
is con olled wi h a pa ame e called
du y cycle
, D, and i depends on ope a ing
poin . F om a physical poin o iew, powe ans e occu s du ing his ime.
Swi ches on LVDC side a e con olled acco ding o SR con ol s a egy.
The code ha implemen s phase-shi ed echnique is a ached in Appendix
A.2.2.
The e a e modula ion s a egies ha can achie e loss educ ion in some ope -
a ing poin s; wo o hem a e desc ibed below.
Mo eo e , he e could be some modula ion scheme ha imp o e swi ching
p ocess in boos mode. I will be discussed in Chap e 9.
3.2.1. So Swi ching
Basic equi emen s o con e e s a e high e iciencies and small sizes. Inc easing
swi ching equency may allow o educe size, [
16
], bu by his way swi ching losses
also aise. A solu ion o his p oblem could be use so swi ching echniques, [
16
],
such as Ze o Vol age Swi ching (ZVS) o Ze o Cu en Swi ching (ZCS). [17].
Swi ching losses a e due o d ain cu en and d ain o sou ce ol age o e lap
and discha ge o s o ed ene gy in C
oss
. Du ing ZVS, cu en a u n on is o ien ed
om sou ce o d ain, which discha ge MOSFET ou pu capaci ance be o e u ning he
de ice on, [
18
]. By his way, V
DS
goes closed o ze o be o e semiconduc o begins
o conduc , hence swi ching on losses a e nea ly elimina ed. No ice ha swi ching
o losses emain wi h ZVS. In he HV b idge, ZVS can be achie ed when, a e a ha d
3.2. Phase-Shi ed Modula ion 33
u n-o , he cu en in he leakage induc ance did no change i s sign a e dead ime.
In his manne , a u n-on, leakage induc ance is ci cula ing h ough he o mos e ,
and ZVS can be achie ed.
To allow wide ZVS ange, he modula o dead ime mus be la ge enough o
a oid c oss conduc ion, bu sho enough o a oid L sign change.
3.2.2. Synch onous Rec i ica ion
Cu en MOSFETs echnology allow lowe ol age d op compa ed o diodes,
so ec i ica ion becomes mo e e icien when cu en lows h ough he i s ones.
This echnique equi e high modula o p ecision: swi ches should be open exac ly
du ing he ime hey a e no conduc ing. Mo eo e his issue, he e a e some design
ade-o s implemen ing SR, [19], [20].
3.2.3. De ailed modula ion scheme
The conc e e scheme o PSM implemen ed is shown in Figu e 3.15.
0
1
SWITCHES GATE SIGNAL
T
1
T
2
0
1
T
3
T
4
0
1
T
5
T
6
Figu e 3.15: Swi ches logic ga e signal
34 Chap e 3. Wo king p inciple desc ip ion
No ice ha he e is a ime be ween he swi ch u n-o and he u n-on o he
o he same-b anch swi ch. A ine une o i , usually called
dead ime
, is c ucial because
his pa ame e a ec s o se e al aspec s o con e e pe o mance (a oiding sho
ci cui , achie ing ZVS).
0
1
DEAD TIME
T
1
T
2
Figu e 3.16: Dead ime
As i appea s in Figu e 3.16, be ween T1 u n-o and T2 u n-on he e is a ime
du ing which bo h logic ga e signals a e "OFF" because eal swi ches - o ins ance,
MOSFETs- need o discha ge and cha ge, espec i ely, ga e-sou ce capaci ances o
each a eal "OFF" o "ON" s a e.
Scheme modula ion p oposed in Figu e 6.5 allows o ge , in buck mode:
Synch onous ec i ica ion.
ZVS in almos he whole ope a ing domain.
Ne e heless, dead ime has o be calcula ed accu a ely in o de o gua an ee ZVS
and SR, when i is possible.
In boos mode none o hese enhancemen s a egies ha e been eached wi h
he modula ion p o ile used.
Chap e 4
Speci ica ions and c i e ia design
The c i e ia design has been es ablished based on ope a ing ange (Sec ion 4.1
and 4.2) and some design assump ions aken om [8] (Sec ion 4.3).
4.1 Ope a ing poin s
In i s place, domain o inpu a iables is speci ied in Table 4.1.
Table 4.1: Design ol age h esholds
Magni ude Buck ope a ing mode Boos ope a ing mode
V1[V] 235 < V1< 325 250 < V1< 360
V2[V] 22 < V2< 30 22 < V2< 30
P [W] 0 < P < 3000 -3000 < P < 0
35

36 Chap e 4. Speci ica ions and c i e ia design
4.2 Nominal ope a ing poin
In second place, nominal ope a ing poin is de ined in Table 4.2.
Table 4.2: Nominal ope a ing poin
V1[V] V2[V] P [W]
270 28 ±3000
4.3 Addi ional design c i e ia
In hi d place, i will be necessa y o include some assump ions, aken om [
8
].
TCis less o equal han 7.5%TS.
T ee is less o equal han 2.5%TS.
∆ILDC2a+2b is less o equal han 40%P2
V2
Chap e 5
Componen s design
5.1 T ans o me
5.1.1. Simple model
Simple model, as discussed below, only conside s n and L.
Tu n a io
In o de o es ima e n, he nex s eps ha e been ollowed.
Fi s o all, a ela ionship be ween V
1
, V
2
, n and D has been aken in o accoun ,
Equa ion 3.1.
Rega ding D de ini ion, i is ob ained he ollowing exp ession.
D= on
TS=1−2 s(TC+T ee)(5.1)
By eplacing T
C
and T
ee
wi h hei maximum alues in Equa ion 5.1, he maxi-
mum achie able alue o D is eached.
Then, se ing minimum alue o V
1
and maximum alue o V
2
in Equa ion 3.1,
37
38 Chap e 5. Componen s design
he maximum alue o n ha can be used is ob ained.
n=V1min
2V2max ·[1 −2 s·(TC+T ee)] (5.2)
Maximum admissible alue o n esul s:
Table 5.1: T ans o me u n a io esul s
Buck mode Boos mode Design alue
nminbuck = 3.1333 nminboos = 3.3333 n = 3
Leakage induc ance
A sui able design c i e ia o leakage induc ance would be o ex end as a as
possible ZVS condi ion. I is in ended o educe cu en a ia ion du ing swi ching
p ocess.
L = 1.5 µH
The p oposed alue has also been se acco ding o [
12
], which conside he
same basic design c i e ia and ope a ing condi ions closed o nominal ope a ion poin ,
Table 4.2
5.1.2. Ad anced model
Tu n a io is he only needed pa ame e o he ideal ans o me model. Ac ually,
ans o me s p esen losses bo h in he co e and in windings due o mul iple e ec s
(hys e esis, ohmic losses, Eddy cu en s). Mo eo e , a high equency ans o me
model has o be comple ed wi h pa asi ic capaci ances.
In his esea ch, he only pa ame e akes in o accoun in a mo e ad anced
design is magne izing induc ance, Lm. A ypical alue o Lmis p esen ed below.
Lm= 1 mH
Including L
m
explici ly allows o check ha cu en h ough ans o me co e
has ze o alue a e age and hence he co e is unsa u a ed.
5.2. DC Induc o 39
5.2 DC Induc o
5.2.1. Simple model
Induc ance o DC induc o s is di ec ly ela ed wi h peak- o-peak alue o LV
side cu en . Hence, in o de o es ima e hese induc ances, he ollowing assump ion
has been made.
∆ILDC2a+2b≤40% ·|P2|
V2(5.3)
Rega ding peak- o-peak cu en de ini ion and assuming an ideal beha iou ,
∆
ILDC2a+2b may be exp essed as i ollows.
∆ILDC2a+2b=max[iLDC2a( )+iLDC2b( )] −min[iLDC2a( )+iLDC2b( )] =(V1/n−V2)·(D/2)
s·LDC (5.4)
Imposing he addi ional condi ion:
LDC2a =LDC2b =LDC (5.5)
Combining 5.3, 5.4 and 5.5, he ollowing exp ession o DC induc o is ob ained.
LDC2a=D/2
s·∆ILDC2a+2b·(V1
n−V2)(5.6)
The aim is o ind he minimum alue ha ul ils Equa ion 5.3 a he wo s
ope a ing condi ion.
LDC2amin =D/2
s·40%|P2|/V2·max(V1
n−V2)(5.7)
Rega ding nominal powe (see Chap e 4, Table 4.2) and Equa ion 3.1, he
ollowing nume ical esul s ha e been ob ained:
46 Chap e 6. Simula ion models and So wa e ools
subsec ions o Chap e 5.
Modulado
1 2
+ +
TF
M1
g
D
S
M1
g
D
S
M2
M2
g
D
S
M4
M4
g
D
S
M3
M3
+
Llk
+
Ldc2a
+
Ldc2b
g
D
S
M5
g
D
S
M6
+
a k
a k
Vaux
1
Vhigh+
2
Vlow+
3
Vhigh-
4
Vlow-
M5
M6
+
Figu e 6.1: Basic MATLAB/Simulink model
6.1.2. Ad anced model
A mo e speci ic Simulink lib a y has been used o de elop an accu acy nume ical
model. In his case, i is Simscape/Elec onics Simulink lib a y.
Diodes and L
DC
inco po a e ohmic esis ances and hence hese models include
ohmic losses. T ans o me magne izing induc ance is also aking in o accoun .
Bu , abo e all, swi ches a e modelled as eal semiconduc o s -MOSFET in his
case- wi h ohmic losses and also pa asi ic e ec s. In his case, lis ed pa ame e s
in Chap e 5, Sec ion 5.5 ha e been added o he model and ealis ic e ec s ha e
been aking in o accoun , such as pa asi ic induc ance due o MOSFETs package and
swi ches layou . Figu es 6.2 and 6.3 illus a e i .
To see conc e e alues, go o Chap e 5.

6.1. MATLAB/Simulink Models 47
Figu e 6.2: HV MOSFET model wi h pa asi ic e ec s
Figu e 6.3: LV MOSFET model wi h pa asi ic e ec s
Face o esul s ha will be ob ained wi h ad anced model, i should be no ed
ha a HV side each swi ch is compound by one single MOSFET, whe eas a LV side
each swi ch is compound by eigh MOSFETs connec ed in pa allel. This conside a ion
is also impo an because esul s unde ac ual ope a ing condi ions will be di e en
o wha i will be ob ained wi h simple model.
48 Chap e 6. Simula ion models and So wa e ools
Bo h models, simple one and ad anced one, ha e been implemen ed so ha
buck and boos simula ions can be p og ammed. I has been achie ed using ideal
ci cui b eake s ha ac i a e and deac i a e pe inen ol age sou ce and load in each
case. Ci cui b eake s s a e a e p ese be o e simula ion calling a pa ame e unc ion.
A p og amming example is gi en in Appendix A.2.1.
6.2 Modula o
Modula o has he same design o bo h models.
Figu e 6.4: Simulink block diag am o Modula o
Modula ion p og amming has been ca ied ou ime independen ly. Compa ing
pe iodic e e ence iangula wa e o m which depends on swi ching equency and
cons an alues acco ding o Figu e 6.5 is possible o gene a e swi ches ga e signal.
Figu e 6.5 cla i ies his idea. To ce ain imed alue, e.g. = 0.5
·D·TS
, co e-
sponds an speci ic e ical alue, ega ding ela ionship be ween simila iangles.
6.2. Modula o 49
Re e ence signal
Ts
x
y
0D·Ts
2
x1=
y1= 1-D
Ts
2
Figu e 6.5: Ga e signal gene a ion p inciple
Modula o code is a ached in Appendix A.2.2.
Chap e 7
Resul s
Jus as in he p e ious chap e , he con en o his one a e di ided in o wo
ca ego ies: esul s coming om Simple model and esul s coming om Ad anced
model.
7.1 Simple model esul s
Figu es om 7.1 o 7.16 ha e a double objec i e. On he one hand, hey e eal
ci cui pe o mance pa e ns when inpu and ou pu ol age le el a e modi ied. On
he o he hand, by knowing ce ain magni udes help o make a p elimina y sizing o
componen s and also would allow o do an e iciency es ima ion. Choosing sui able
semiconduc o s -MOSFET in his case- o ca y ou swi ching unc ion is pa icula ly
c ucial.
51

52 Chap e 7. Resul s
7.1.1. Swi ches
Max. al. = 16.6 a
V1 = 303 , V2 = 22
12 320
20 300
14
280
High ol age ange [V]
25
Low ol age ange [V]
Buck mode
3000 W
16
260
SWITCH T1 RMS cu en [A]
240
18
30 220
20
Figu e 7.1: Cu en h ough HV side swi ches in buck mode ope a ion
8
Max. al. = 11.1 a
V1 = 250 , V2 = 22
350
20
10
High ol age ange [V]
300
25
Low ol age ange [V]
Boos mode
3000 W
SWITCH T1 RMS cu en [A]
12
250
30
14
Figu e 7.2: Cu en h ough HV side swi ches in boos mode ope a ion
7.1. Simple model esul s 53
Figu es 7.1 and 7.2 show RMS cu en h ough espec i e swi ches, and hey
also poin maximum alues - ed ball-. Maximum RMS cu en s a e: 16.6 A in buck
mode and 11.1 A in boos mode.
Max. al. = 89.8 a
V1 = 303 , V2 = 22
320
70
20 300
80
280
High ol age ange [V]
25
Low ol age ange [V]
Buck mode
3000 W
260
SWITCH T5 RMS cu en [A]
90
240
30
100
220
Figu e 7.3: Cu en h ough LV side swi ches in buck mode ope a ion
Max. al. = 89 a
V1 = 360 , V2 = 22
350
70
20
80
High ol age ange [V]
300
25
Low ol age ange [V]
Boos mode
3000 W
SWITCH T5 RMS cu en [A]
90
250
30
100
Figu e 7.4: Cu en h ough LV side swi ches in boos mode ope a ion
54 Chap e 7. Resul s
Figu es 7.3 and 7.4 show RMS cu en h ough LV swi ches. Cu en is much
highe han in HV swi ches clea ly. Maximum alues a e: 89.9 A in buck mode and 89
A in boos mode.
Knowing maximum RMS help o selec sui able eal semiconduc o s o swi ches.
Mo eo e , his maximum alues, oge he wi h ol age d op, would allow o es ima e
maximum VA a ings o swi ches. In o ma ion ob ained om his p elimina y esul s
and nominal ope a ing poin speci ica ions (Chap e 4) jus i y MOSFET selec ion o
bo h HV and LV sides. To see hei main cha ac e is ics in de ail, go o Chap e 5,
Sec ion 5.5.
320
20
20
300
22
280
Max. al. = 22 a
V1 = 235 , V2 = 22
High ol age ange [V]
25
Low ol age ange [V]
Buck mode
3000 W
260
SWITCH-OFF CURRENT T1 [A]
24
240
30
26
220
Figu e 7.5: Cu en a SWITCH-OFF on HV side swi ches in buck mode ope a ion
7.1. Simple model esul s 55
0350
20
High ol age ange [V]
300
2
25
Low ol age ange [V]
Boos mode
3000 W
SWITCH-OFF CURRENT T1 [A]
Max. al. = 3.72 a
V1 = 360 , V2 = 30
250
30
4
Figu e 7.6: Cu en a SWITCH-OFF on HV side swi ches in boos mode ope a ion
Figu es 7.5 and 7.6 p esen cu en a he swi ching-o ins an o HV swi ches.
In boos mode his cu en is e y low - he maximum alue eached is 3.72 A-, whe eas
un buck mode i is highe , om 20 o 22 A -maximum alue eached is 22 A.
Max. al. = -62.9 a
V1 = 235 , V2 = 22
320
-60
20 300
280
High ol age ange [V]
25
Low ol age ange [V]
Buck mode
3000 W
-40
260
SWITCH-OFF CURRENT T5 [A]
240
30 220
-20
Figu e 7.7: Cu en a SWITCH-OFF on LV side swi ches in buck mode ope a ion
62 Chap e 7. Resul s
I can be seen in Figu es 7.13 o 7.16 ha RMS cu en s h ough capaci o s a e
e y simila in bo h modes and e en in bo h HV and LV side. Ne e heless, his esul
does no obey o physical eason: i o he design c i e ia o L
DC
would be conside ed,
hose simila alues would no ha e been ge .
Again, maximum alues ob ained om his esul s allow o choose sui able
capaci o s.
7.2 Ad anced model esul s
In o ma ion p esen ed in his sec ion y o highligh con e e e iciency in
ce ain ope a ing poin s. Be o e a b ie explana ion abou nume ic esul s, some
de ini ions a e going o be es ablished in o de o unde s and hem be e .
I is impo an o no ice ha he only losses conside ed come om swi ches
mainly. Hence, con e e e iciency gi es in o ma ion abou swi ches e iciency. Swi ch
losses can be sepa a ed in o conduc ion losses and swi ching losses, [
27
]. They a e
calcula ed as indica ed in Equa ions 7.1 o 7.4.
¯
PCOND =¯
PCONDHV +¯
PCONDLV (7.1)
¯
PCONDHV =RDSonHV ·RMS(IHV )(7.2)
¯
PCONDLV =RDSonLV ·RMS(ILV )(7.3)
¯
PSW =(¯
PIN −¯
POUT )−¯
PCOND (7.4)
Whe e P
IN
deno es inpu powe , P
OUT
deno es ou pu powe , P
CONDi
deno es
conduc ion losses, P
SW
deno es swi ching losses, RMS(I
i
) deno es swi ch RMS cu en ,

7.2. Ad anced model esul s 63
and subindex i makes e e ence o ei he HV o LV.
Con e e e iciency is calcula ed acco ding o Equa ion 7.5.
η=Pou
Pin ·100 (7.5)
I is impo an o no e ha wi hin swi ching losses a e included passi e snubbe
losses.
Table 7.1 summa izes his sec ion esul s.
Table 7.1: Ad anced model esul s
V1V2PNOM PIN POUT PCOND PSW η
Buck mode
270 22 1500
1344.0 1278.2
28.2 37.6 95.1
270 28 1500
1387.1 1330.1
20.4 36.5 95.9
325 22 1500
1362.7 1282.6
28.0 52.1 94.1
325 28 1500
1404.2 1332.1
21.0 51.0 94.9
270 22 3000
2436.2 2301.0
91.0 44.2 94.5
270 28 3000
2585.2 2477.8
64.9 42.4 95.8
325 22 3000
2466.2 2317.4
89.9 58.9 94.0
325 28 3000
2611.6 2489.4
65.2 57.0 95.3
Boos mode
270 22 1500
1549.2 1434.5
22.2 92.6 92.6
270 28 1500
1568.1 1475.4
16.7 75.9 94.1
325 22 1500
1586.4 1442.5
21.2 122.7 90.9
64 Chap e 7. Resul s
325 28 1500
1604.8 1483.0
16.1 105.7 92.4
270 22 3000
2989.2 2599.6
86.1 303.5 87.0
270 28 3000
3047.9 2775.3
59.7 212.9 91.1
325 22 3000
3087.4 2625.8
83.2 378.4 85.0
325 28 3000
3133.3 2799.4
56.3 277.6 89.3
An o e iew o las column shows ha e iciency in boos mode is lowe han
buck mode in any case. Whe eas e iciency is equal o highe han 94% in buck mode,
maximum alue in boos mode is 94.1%.
I esul s a nominal powe a e compa ed wi h hal nominal powe , he conclusion
is ha di e ences in boos a e much highe han in buck mode. Di e ences a e
pe cen age en hs in buck mode, whe eas hey a e pe cen age uni s in boos mode.
A ending o swi ches losses, conduc ion losses a e app oxima ely simila bu
in boos mode swi ching losses g ow up eno mously.
Chap e 8
Conclusions
Bidi ec ional and Isola ed Cu en Double Topology wi h clamped diodes is a
p omising opology o de elop powe con e e s. I also allows modula i y implemen-
a ion, which is impo an o achie e highe powe le els han he op imal ope a ing
poin o single b ick.
In con as wi h o he opologies, impo an ad an ages o his one a e low RMS
cu en s a bo h HV and LV side swi ches and also a ans o me , which in ol es lowe
conduc ion losses. Ano he ad an age is low RMS cu en h ough DC link capaci o s,
which in ol es smalle size o hem. F om eliabili y poin o iew, his opology does
no ha e oo many componen s. The lowe numbe o componen s, he lowe ailu e
p obabili y.
P ojec objec i e has been o s udy wo king p inciple o his opology and,
aking a single modula ion echnique, pe o m nume ical simula ions o ob ain a
i s o de es ima ion esul s o e iciency. As in eal li e, i is necessa y o ollow an
i e a i e p ocess. So wi h in o ma ion abou cu en and ol age o e ideal swi ches,
eal semiconduc o s ha e been selec ed in o de o do a mo e accu a e e iciency
es ima ion, since swi ches a e componen s wi h highe losses, especially a high
equency.
As i can be checked in i s sec ion o Chap e 7, swi ches a e no wi hs and
cu en s oo high. In HV side hey a e specially low, so VA a ings also a e low o his
componen s.
Essen ial design pa ame e s o be conside ed a e e iciency and powe densi y.
65
66 Chap e 8. Conclusions
This s udy has been ocused on es ima ing he opology e iciency a ce ain ope a ing
poin s in o de o ensu e quan i a i ely how good is he opology unde es . Al hough
powe densi y has no been calcula ed, pa ame e s which a ec i ha e been aken
in o accoun , such as swi ching equency – he highe
s
is, he smalle magne ics
componen s a e bu he highe swi ching losses a e– ; ol age and cu en a ings o
DC link capaci o s, numbe o componen s, and so on.
F om e iciency poin o iew, Cu en Double Con e e is mo e e icien wo k-
ing in buck mode han in boos mode, since swi ching losses a e lowe - ega ding
modula ion echnique p og ammed-. Conside an enhanced modula ion echnique
would educe losses in boos mode, by a oiding ol age spikes a LV swi ches a
u n-o .
I should no be o ge ha eal powe ci cui s ha e mo e losses sou ces. DC
induc o s and ans o me s losses should be aking in o accoun in a deepe e iciency
analysis o he con e e .
Chap e 9
Fu u e Wo k
9.1 PSpice simula ions
Cu en ly he e a e se e al so wa e based on PSPICE sol e . A ine calcula ion
o e iciency and VA a ings should be done wi h hem, since hey p o ide accu a e
esul s o powe elec onics ci cui s. Mo eo e , he mal conside a ions -dynamic
he mal model o example- could be aking in o accoun wi h his ools.
Some manu ac u e s, as
In ineon Technologies
, supply PSPICE semiconduc o
models -MOSFETs, diodes,...- and hey also sugges he bes sol e con igu a ion o
make he p og am un.
9.2 Al e na i e modula ion echnique
Swi ches ga e signals a e d i en using Single PSM in his p ojec . The e is no
any di e ence be ween buck and boos mode om ga e signals poin o iew. Ne e -
heless, as i is p oposed in [
8
], he e is ano he modula ion scheme ha imp o es
he implemen ed one.
Al e na i e modula ion would gene a e di e ences be ween ope a ing modes
67

68 Chap e 9. Fu u e Wo k
ga e signals, since hey a e no symme ic (e en i hey ha e he same swi ches ga e
signals). Basically, i calcula es he eewheeling ime and swi ching-on and swi ching-
o LV side swi ches a e modi ied - educed in ac - acco ding o his ime. Figu es 9.1
and 9.2 illus a e he idea.
Figu e 9.1: Al e na i e modula ion scheme o buck mode, [8]
Figu e 9.1 shows ha in buck mode, whi he p oposed swi ching scheme o HV
side swi ches, du ing he eewheeling pe iod T5 and T6 emain ON and hey a e OFF
only du ing he e ec i e powe deli e y. F eewheeling pe iod occu s in buck mode
a he beginning, i.e. be o e powe ans e pe iod as i can be seen in Figu e 9.1. As
esul , he ime du ing LV swi hces a e ON is educed in a ime quan i y deno ed by
∆Tin espec o ime du ing swi ches o each HV b anch a e ON simul aneously.
9.2. Al e na i e modula ion echnique 69
Figu e 9.2: Al e na i e modula ion scheme o boos mode, [8]
In boos mode, on he o he hand, eewheeling pe iod akes place a e powe
deli e y pe iod. Howe e , in he same way as in buck mode, T5 and T6 only a e ON
du ing e ec i e powe deli e y whe eas HV swi ches (T1 o T4) a e ON du ing e ec i e
powe deli e y plus he ime in e al called ∆T.
Mo eo e , al e na i e modula ion in boos mode adds an addi ional ad an age,
because i allows o a oid ol age spikes on LV swi ches. The main disad an age o his
echnique is ha , e en i
∆T
could be calcula ed accu a ely in s eady s a e, i would
be necessa y a complex sol e o calcula e i du ing dynamic ansien , because i a
any swi ching e en he u ning-o cu en was om d ain o sou ce, a ol age spike,
possibly des uc i e, would occu . Ano he possible disad an age o his modula ion
scheme a e highe RMS cu en s in LV swi ches.
70 Chap e 9. Fu u e Wo k
9.3 Fu he simula ion analysis
Ad anced model simula ions esul s ha e pe mi ed o show an es ima ion o
e iciency and i s beha iou wi h he domain a iables. Ne e heless, hese simula ions
ake oo ime and only a ew ope a ing poin s ha e been analysed. I would be desi able
o explo e mo e ope a ing poin s o he whole domain in o de o achie e s onge
conclusions.
As men ioned in Chap e 7, i would be possible o calcula e e iciency using
p esen ed magni udes o e he whole domain. I would be in e es ing o make a
compa ison be ween e iciency ob ained om ad anced model simula ion esul s and
e iciency calcula ed ega ding ope a ing poin s om simple model esul s.
Appendices
71
78 A.1. Compa a i e esul s be ween medium powe and ull powe
LV SWITCH, P = PN/2= 1500 W
V1[V]/V2[V] 22 23 25 26 27 29 30
250 44.26 42.73 39.92 38.67 37.51 35.43 34.48
278 44.11 42.51 39.67 38.41 37.23 35.09 34.12
305 44.32 42.73 39.83 38.57 37.37 35.18 34.19
333 44.96 43.36 40.43 39.14 37.90 35.76 34.72
360 46.04 44.39 41.47 40.13 38.93 36.69 35.71
Table A.11: RMS cu en [A] on LV swi ch o PN/2in boos mode
LV SWITCH
V1[V]/V2[V] 22 23 25 26 27 29 30
250 -47.38 -47.78 -48.00 -48.15 -48.28 -47.61 -48.06
278 -48.23 -48.26 -48.34 -48.11 -48.54 -48.65 -48.58
305 -48.44 -48.32 -48.76 -48.84 -48.70 -48.50 -48.53
333 -48.96 -49.03 -48.87 -48.26 -48.83 -49.28 -49.38
360 -48.86 -48.06 -48.96 -49.46 -49.57 -48.91 -47.88
Table A.12: Pe cen age change in RMS cu en on LV swi ch o PN
/
2wi h ega d o PNin boos
mode

A.1. Compa a i e esul s be ween medium powe and ull powe 79
TRANSFORMER, P = PN/2= 1500 W
V1[V]/V2[V] 22 23 25 26 27 29 30
250 8.90 8.82 8.71 8.66 8.62 8.50 8.44
278 8.96 8.96 8.89 8.88 8.86 8.75 8.72
305 9.16 9.27 9.31 9.32 9.32 9.29 9.26
333 9.64 9.81 9.91 9.94 9.95 10.04 10.01
360 10.25 10.36 10.63 10.68 10.77 10.81 10.87
Table A.13: RMS cu en [A] on ans o me o PN/2in boos mode
TRANSFORMER
V1[V]/V2[V] 22 23 25 26 27 29 30
250 -43.17 -40.23 -36.51 -30.83 -24.22 -42.86 -39.40
278 -34.89 -28.61 -22.16 -42.01 -38.17 -32.74 -25.77
305 -17.83 -41.61 -37.47 -31.79 -24.56 -16.32 -41.16
333 -36.83 -30.95 -23.47 -14.81 -40.55 -36.06 -29.53
360 -21.25 -13.01 -40.30 -35.61 -28.98 -20.74 -12.10
Table A.14: Pe cen age change in RMS cu en on ans o me o PN
/
2wi h ega d o PNin
boos mode
80 A.1. Compa a i e esul s be ween medium powe and ull powe
LDC2A,P=PN/2= 1500 W
V1[V]/V2[V] 22 23 25 26 27 29 30
250 8.90 8.82 8.71 8.66 8.62 8.50 8.44
278 8.96 8.96 8.89 8.88 8.86 8.75 8.72
305 9.16 9.27 9.31 9.32 9.32 9.29 9.26
333 9.64 9.81 9.91 9.94 9.95 10.04 10.01
360 10.25 10.36 10.63 10.68 10.77 10.81 10.87
Table A.15: RMS cu en [A] on LDC2a o PN/2in boos mode
LDC2a
V1[V]/V2[V] 22 23 25 26 27 29 30
250 -46.20 -46.63 -47.11 -47.71 -48.86 -46.10 -46.62
278 -47.06 -47.77 -48.77 -45.98 -46.27 -46.82 -47.48
305 -48.48 -45.82 -46.09 -46.47 -47.26 -48.07 -45.53
333 -45.75 -46.19 -46.94 -47.25 -45.04 -45.22 -45.37
360 -45.48 -46.24 -44.72 -44.84 -44.96 -44.94 -45.59
Table A.16: Pe cen age change in RMS cu en on LDC2a o PN
/
2wi h ega d o PNin boos
mode
A.2. Ma lab code 81
A.2 Ma lab code
A.2.1. Code o se ing a simula ion
unc ion [pa am]=cu en _double _pa ame e s(V1, V2, P_ac , model_ ype)
% Time pa ame e s
pa am.Tin = 1e-9; % s
pa am. m = 50e-9; % s
pa am. s = 100e3; % Hz
pa am.Ts = 1/pa am. s; % s
% Ope a ing poin pa ame e s
pa am.Vhigh = V1; % V
pa am.Vlow = V2; % V
pa am.Pnom = abs(P_ac ); % W
% Ope a ing mode de ined by powe sign
i sign(P_ac )>=0
op_mode = ’buck’;
else
op_mode = ’boos ’;
end
% Componen s pa ame e s
% MOSFET
swi ch model_ ype
case ’simple’
pa am.Rds_on_l = 36.25e-3; %Ω
pa am.Ron_d_l = 0.8/64; %Ω
pa am.Vd_m_l = 0.8; % V
pa am.Rds_on_h = 36e-3; %Ω
pa am.Ron_d_h = 5/30; %Ω
82 A.2. Ma lab code
pa am.Vd_m_h = 5; % V
case ’ad anced’
pa am.sou ce_gain_h = 20;
pa am.sou ce_gain_l = 15;
pa am.L_pa _mos = 2e-9; % H
pa am.C_snb = 20e-9; % F
pa am.R_snb = 5; %Ω
% Mos e HV side
pa am.Rga e_high_on = 6; %Ω
pa am.Rga e_high_o = 12; %Ω
pa am.Rds_on_h = 36e-3; %Ω
pa am.Ids_h = 35; % A
pa am.Vgs_h = 15; % V
pa am.V h_h = 1.875; % V
pa am.Rs_h = 1.42e-3; %Ω
pa am.Rd_h = 77.52e-6; %Ω
pa am.Ciss_h = 1750; % nF
pa am.C ss_h = 9.5; % nF
pa am.Coss_h = 150; % nF
pa am.V d_h = 5; % V
pa am.Ron_d_h = 5/30; %Ω
pa am.lambda_h = 0.01;
% Mos e LV side
pa am.Rga e_low_on = 6; %Ω
pa am.Rga e_low_o = 12; %Ω
pa am.Rds_on_l = 36.25e-3; %Ω
pa am.Ids_l = 64; % A
pa am.Vgs_l = 10; % V
pa am.V h_l = 2.2; % V
pa am.Rs_l = 878e-6; %Ω
pa am.Rd_l = 50e-6; %Ω
pa am.Ciss_l = 5340; % nF
pa am.C ss_l = 4; % nF
pa am.Coss_l = 240; % nF
A.2. Ma lab code 83
pa am.V d_l = 0.8; % V
pa am.Ron_d_l = 0.8/64; %Ω
pa am.lambda_l = 0.25;
end
% TRANSFORMER
pa am.N2N1 = 3;
pa am.L_lk = 1.5e-6; % H
swi ch model_ ype
case ’simple’
pa am.Rm = 1e7; %Ω
case ’ad anced’
pa am.Rm = 1e7; %Ω
pa am.Lm = 1e-3; % H
end
% DC INDUCTOR
pa am.L_dc = 3.7e-6; % H
pa am.R_ldc = 0;
% VAUX AND CLAMPED DIODES
pa am.Rd = 20e-3; %Ω
pa am.Vd = 1.2; %Ω
pa am.Vaux = 150; % V
% CAPACITORS
pa am.Chigh = 500e-6; % F
pa am.Clow = 500e-6; % F
% CIRCUIT BREAKER RESISTANCE
pa am.Ron_b eak = 1e-15; %Ω

84 A.2. Ma lab code
% OPERATING MODES SELECTION
swi ch op_mode
case ’buck’
pa am.ope a ing_mode = 1;
% Ci cui b eake s s a e
pa am.ga e_b eak_sou ce_h = 1;
pa am.ga e_b eak_sou ce_l = 0;
pa am.ga e_b eak_load_h = 0;
pa am.ga e_b eak_load_l = 1;
pa am.ga e_h _cap = 0;
pa am.ga e_l _cap = 1;
% DC ne wo ks ol age
pa am.Vin = V1;
pa am.Vou = V2;
% Adjus load o nominal powe
pa am.Rload = pa am.Vou ˆ2/pa am.Pnom;
% Capaci o s ini ial ol age
pa am.Chigh_ini ial = 0;
pa am.Clow_ini ial = 0;
pa am.D_nom = (2*pa am.Vou *pa am.N2N1)/pa am.Vin;
case ’boos ’
pa am.ope a ing_mode = 2;
% Ci cui b eake s s a e
pa am.ga e_b eak_sou ce_h = 0;
pa am.ga e_b eak_sou ce_l = 1;
pa am.ga e_b eak_load_h = 1;
pa am.ga e_b eak_load_l = 0;
pa am.ga e_h _cap = 1;
pa am.ga e_l _cap = 0;
% DC ne wo ks ol age
A.2. Ma lab code 85
pa am.Vin = V2;
pa am.Vou = V1;
% Adjus load o nominal powe
pa am.Rload = pa am.Vou ˆ
2/pa am.Pnom;
% Capaci o s ini ial ol age
pa am.Chigh_ini ial = pa am.Vou *0.9;
pa am.Clow_ini ial = 0;
pa am.D_nom = (2*pa am.Vin*pa am.N2N1)/pa am.Vou ;
end
end
A.2.2. Modula o algo i hm
unc ion [p1, p2, p3, p4, p5, p6, D_e ] = cn(u, s, m, D_nom, ope a ing_mode)
Ts = 1/ s; % Hz
i ope a ing_mode==1 % BUCK MODE
D_e = D_nom;
y0 = 1-( m/(Ts/2));
x0 = 1-y0;
y2 = 1-(D_e +( m)*2/Ts);
x2 = 1-y2;
y4 = 1-(D_e );
x4 = 1-y4;
% GATES 1 AND 2
i u >= 0
p2 = 0;
i u>y0
p1 = 0;
else
p1 = 1;
86 A.2. Ma lab code
end
else
p1 = 0;
i u>=-(x0)
p2 = 0;
else
p2 = 1;
end
end
% GATES 3 AND 4
i u>y2 || u<-(x4)
p3 = 0;
i u>y4 || u<=-(x2)
p4 = 1;
else
p4 = 0;
end
else
p3 = 1;
p4 = 0;
end
% GATE 5
i u>=y4 && u<=1
p5 = 0;
else
p5 = 1;
end
% GATE 6
i i u<=0 && u>=-(x4)
p6 = 0;
else
p6 = 1;
end
else % BOOST MODE
A.2. Ma lab code 87
D_e = D_nom;
y0 = 1-( m/(Ts/2));
x0 = 1-y0;
y2 = 1-(D_e +( m)*2/Ts);
x2 = 1-y2;
y4 = 1-(D_e );
x4 = 1-y4;
% GATES 1 AND 2
i u >= 0
p2 = 0;
i u>y0
p1 = 0;
else
p1 = 1;
end
else
p1 = 0;
i u>=-(x0)
p2 = 0;
else
p2 = 1;
end
end
% GATES 3 AND 4
i u>y2 || u<-(x4)
p3 = 0;
i u>y4 || u<=-(x2)
p4 = 1;
else
p4 = 0;
end
else
p3 = 1;
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