Design and Modelling of a Bidirectional DC-DC Converter based on Full Bridge Current Doubler Topology for Aeronautical Applications

Proyecto Fin de Carrera Ingeniería de Telecomunicación Formato de Publicación de la Escuela Técnica Superior de Ingeniería Autor: F. Javier Payán Somet Tutor: Juan José Murillo Fuentes Dep. Teoría de la Señal y Comunicaciones Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2013 Trabajo Fin de Máster Máster en Ingeniería Aeronáutica Design and Modelling of a Bidirectional DC-DC Converter based on Full Bridge Current Doubler Topology for Aeronautical Applications Autor: Álvaro de Jesús Ojeda Rodríguez Tutor: María Ángeles Martín Prats Ingeniería Electrónica Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2019 Trabajo Fin de Máster Máster en Ingeniería Aeronáutica Design and Modelling of a Bidirectional DC-DC Converter based on Full Bridge Current Doubler Topology for Aeronautical Applications Autor: Álvaro de Jesús Ojeda Rodríguez Tutor: María Ángeles Martín Prats Profesora Titular Ingeniería Electrónica Escuela Técnica Superior de Ingeniería Universidad de Sevilla Sevilla, 2019 Trabajo Fin de Máster: Design and Modelling of a Bidirectional DC-DC Converter based on Full Bridge Current Doubler Topology for Aeronautical Applications Autor: Álvaro de Jesús Ojeda Rodríguez Tutor: María Ángeles Martín Prats El tribunal nombrado para juzgar el trabajo arriba indicado, compuesto por los siguientes profesores: Presidente: Vocal/es: Secretario: acuerdan otorgarle la calificación de: El Secretario del Tribunal Fecha: Acknowledgements This project would not exist without the encouragement from a lot of people. I would like to thank my parents, and also my whole family, for their constant support. They always help me to take the best decision. They always help me to be a better person. I would also like to tank my colleague and friend Pablo González for his invaluable collaboration. He knows how to see the best face of Power Electronics. I could not forget to thank professors María Ángeles Martín and Joaquín Bernal, who gave me the opportunity to take part in this study and work with their research group. Finally, I would like to remember all my friends, all my professors, because each one, from his position, have helped me to reach the objective: Aeronautical Engineering. I Abstract This project falls within the framework of the research about More Electric Aircraft (MEA) concept, which is the target of the current designs. In this context, electrical system is being reinforced as one of the main power systems. Electrical power level and voltage level transmission are increasing –the last one is tending to High Voltage Direct Current (HVDC) level– and requirements of generation, distribution, management and control of this kind of power are becoming more and more challenging. Within electrical system, power converters are responsible for electrical power transmission. Moreover, they must fulfil aeronautical standards in respect of on-board electrical and electronic systems. The precise aim of this project is to study suitable topologies for DC-DC bidirectional and isolated power converters within defined framework. Many industries, as aeronautical or automotive, request them with better features –for instance, power density and efficiency are critical KPI in aeronautical industry–. After a review of main power circuits that could fulfil specifications for these applications, a promising topology will be analysed from a numerical point of view. Particularly, Bidirectional Current Doubler is the topology subject of study. Its working principle will be analysed under certain operating range domain. Simulation models will be developed to asses topology performance in such operating domain. By knowing currents and voltages on ideal elements, a more realistic components selection will be carried out, particularly as far as MOSFETs concerns. Finally, regarding a more little bit accurate model, efficiency will be calculated in terms of input and output power. III X Acronyms MEA More Electric Aircraft. PDS Power Distribution System. PSM Phase Shift Modulation. PSPICE Personal Simulation Program with Integrated Circuits Emphasis. R&D Research and Development. RMS Root Mean Square. SESAR Single European Sky ATM Research. SJU SESAR Joint Undertakinhg. SPRC Series-Parallel Resonant Converter. SR Synchronous Rectification. TRU Transformer Rectifier Unit. VDC Volts Direct Current. ZCS Zero Current Switching. ZVS Zero Voltage Switching. Symbols ∆ILDC2a+2b Peak-to-peak total current through LV side inductors. Coss Mosfet output parasitic capacitance. Csnb Snubber capacitance. DDuty cycle. fsSwitching frequency. IAC1 Transformer current at HV side. IAC2 Transformer current at LV side. ILDC2a DC inductor current. LLeakage inductance. LDC DC inductor. LmMagnetizing inductance. nTransformer turn ratio. P2Nominal power at low voltage side. Rdclamped Ohmic resistance clamped diode. RDSon Ohmic switch resistance when it is conducting. RLDC Ohmic resistance DC inductor. XI XII Symbols RmMagnetizing resistance. Rsnb Snubber resistance. T1 Semiconductor HV side 1. T2 Semiconductor HV side 2. T3 Semiconductor HV side 3. T4 Semiconductor HV side 4. T5 Semiconductor LV side 5. T6 Semiconductor LV side 6. TCSwitching time. Tdead Dead time. Tfree Freewheeling time. TSSwitching period. V1High voltage. V2Low voltage. VAC1 Transformer voltage at HV side before leakage inductance. VAC2 Transformer voltage at LV side. Vaux Auxiliary voltage source. Vdclamped Forward voltage drop clamped diode. Vdswitch Voltage drop across switch antiparallel diode. VDS Mosfet drain to source voltage drop. VLVoltage drop through leakage inductor. Chapter 1 Introduction 1.1 General presentation of the study Currently, it is a fact that More Electric Aircraft (MEA) is not the future but the present. So R&D tends to aircraft designs that involve higher power level, [ 1 ]. This affects to power generation, transmission, management and control. A good example could be aircraft Airbus A350 and Boeing B787 Dreamliner . The first one comes with four independent variable frequency generators, each one of 100 kVA, [ 2 ]. The second one is fitted with four variable frequency generators, each one of 250 kVA, [ 3 ], [ 4 ]. From the electrical power generated on-board point of view, Boeing Dreamliner is closer to MEA concept than Airbus A350, since the first one generates more than twice the electrical power than the last one. As far as safety, reliability and technological advances concerned, aeronautics is perhaps one of the most challenging industries. Issues related to weight and size reduction, power density and efficiency are also especially important. Because of this, electrical systems and electrical/electronics devices are required to be: Very efficient. With high power density. Increasing efficiency will help to reduce environmental impact, and also decrease operating cost. International organisations, like SESAR Joint Undertaking (SJU), consider this R&D tasks seriously and therefore they support many research projects 1 2 Chapter 1. Introduction in this field –and in many others that could be relation with improving efficiency, safety, and so on–like Clean Sky programs. Power Electronics is the subject that faces such a challenging task. A good definition of Power Electronics is given by [5] : “Power electronics involves the study of electronics circuit intended to control digitally the flow of electrical energy. These circuits handle power flow at levels much higher than the individual device ratings”. Power electronics basic module is power converter. This electronic circuit contains switches (e.g. semiconductors), energy storage elements (e.g. inductors, capacitors) and transformers. An external control function commands the switches according to the input received from the load and power converter state. Regarding the type of electrical power at input and output of power converter, a number of different kinds of converters exists: AC to DC converter, also called rectifier. DC to AC converter, also called inverter. AC to AC converter. DC to DC converter. In order to improve reliability and safety, electrical power generation has been moved from DC to AC, [ 1 ]. This change in topology increased the power density due to the benefits of AC generators, with the consequent size and weight reduction. However, power distribution in new aircraft designs tends to include a hybrid PDS with DC and AC buses, in order to supply power to all type of loads, [ 3 ]. Figure 1.1 shows an example of MEA electrical power system architecture. 1.1. General presentation of the study 3 Figure 1.1: Generic electrical architecture of MEA concept of aircraft, [6] As first concrete step, present work will be focused on HVDC to LVDC bidirectional power converter. Typical nominal voltage levels are presented in Figure 1.1: 270 VDC at HVDC and 28 VDC at LVDC. More precisely, this research will review isolated and bidirectional power electronic circuits -topologies-. The State-of-the-art revision goal is to select a promising topology that supports HVDC and LVDC ranges mentioned above. Application ranges are described in detail in Chapter 4. This topology will be used to built low power modular bricks, where low power means few kilowatts. If the application requires high power transfer or high voltage levels, bricks can be connected forming a cascaded multi-converter , [ 7 ]. Each brick only handles a fraction of the total power. Converter bricks can be set in different configurations: if the brick terminals are connected in parallel, they will share the DC line current; in the other hand, if brick terminals are connected in series, DC line voltage is distributed among them. The optimum choice depends on the application. Hence, despite of the voltage and power ranges are limited to magnitude order mentioned before, this research keeps utility for applications where high power and input/output voltages are involved. 4 Chapter 1. Introduction 1.2 Document structure At the first place a condensed but fairly complete State-of-the-art has been carried out exploring the main available bidirectional and isolated topologies for DC to DC power conversion at certain HVDC and LVDC nominal levels, Chapter 2. Chapter 3 describes briefly the key theoretical ideas to understanding the performance and physical operation of the power electronics circuit. A detailed explanation of two basic operating modes of converter will be exposed, giving waveform examples and describing the control of switches. Buck mode. This is the most usual working mode for such topology. The objective is power transfer from HVDC to LVDC. Boost mode. CDR is not widely used for this function: transfer power rising output voltage level to high values from low voltage input level. This theoretical approach will be based on the circuit shows in Figure 3.2. Power converter will be connected at LV side either to load that requires LVDC power supply or LVDC network that impose constant voltage level. The same occurs at HV side. Chapter 4 focuses on reviewing the main specifications and criteria design that will constitute the starting point to obtain a first estimation of main magnitudes. Chapter 5, "Design of Components", described the main components of the power circuit and how they have been modelled. A light description of numerical models and commercial software use for the simulation is contained in Chapter 6. Chapter 7 collects the results of the whole study, which will be presented in different formats: graphics, tables, etc. Some of the expected results are:RMS currents through magnetics components and capacitors, and first order estimations of efficiency. All these results will be provided within the operating range provided by specifications. At the end, Chapters 8 "Conclusions" and 9 "Future Work" sum up the main and more interesting ideas of the research and also review those issues that due to lack of time could not be completely solved. Moreover, some suggestions will be proposed as "work guidelines", i.e. parameters optimization and functional prototype manufacturing to compare experimental results with numerical ones. 1.3. Study objectives 5 1.3 Study objectives Main study goals are summed up below. Compare topologies that fulfil essential requirements –high efficiency and high power density– for on-board electric and electronics power systems, as well as operating range defined by aeronautical application in the MEA concept framework. Select a promising topology and analyse it from a theoretical approach and also from a numerical approach. Using a single model with lossless components, estimate voltage and current levels over them. Accomplish an initial realistic components selection with this information, which withstand voltage and current maximum ratings. Finally, elaborate a slightly more advanced simulation model in order to calculate efficiency at certain operating points. Chapter 2 State-of-the-art analysis This chapter is a review on available DC to DC power converters, based on isolated and bidirectional topologies which are able to transfer power within the range of 1-5 kW, [8]. They also support well nominal working HVDC and LVDC ranges. Hence the presented State-of-the-art focuses on some specific power circuits and excludes other ones that do not suit so well those specifications. 2.1 General architecture of DC to DC converter A general configuration of a bidirectional DC to DC converter with galvanic isolation is shown in Figure 2.1. 7 14 Chapter 2. State-of-the-art analysis 2.3.1. Switches For each switch this rating is calculated with Equation 2.1, [8]: Sswi tch =max(Vswitch,peak)·max(Iswi tch)(2.1) Where max( Vswitch,peak ) is the maximum voltage applied to the switch and max(Iswitch) is the maximum RMS current through the switch, [8]. 2.3.2. Transformer For a single-phase transformer with m windings operated with sinusoidal voltages and currents, VA rating is calculated using Equation 2.2, [8]: Str =1 2 m X i=1 ˆ Vtr,i·ˆ Itr,i(2.2) Where ˆ Vtr,i denotes RMS voltage applied to the i -th winding and ˆ Itr,i makes reference to RMS current through the i-th winding, [8]. Nevertheless, discussed DC to DC topologies do not employ purely sinusoidal waveforms. So the suitable modified expression is Equation 2.3, [8]: Str =1 2 m X i=1 ˆ Vtr,i,eq ·ˆ Itr,i,eq (2.3) Where ˆ Vtr,i,eq and ˆ Itr,i,eq are defined as Equations 2.4 and 2.5 state, [8]. ˆ Vtr,i,eq =πD p2V1(2.4) ˆ Itr,i,eq =ˆ Itr,i(2.5) Regarding mathematical definition above, considered items for comparison are going to be enumerated. 2.3. Topologies comparison 15 Number of components. •Active ones. •Magnetic ones. Switches: •VA rating sum of LV side. •VA rating sum of HV side. Transformer: •Maximum RMS current. Inductors: •Maximum DC current. •Maximum RMS current. •Peak energy. Capacitors: •Peak energy. •RMS current. Other considerations: •Pre-charge issues. •Modulation complexity. •Snubber required. Table 2.1 sums up the final comparison between considered topologies. 16 Chapter 2. State-of-the-art analysis Table 2.1: Topologies comparison, [8] Topology Advantages Disadvantages DAB (Conv. Mod.) Lowest component count. Avoids DC inductor. Simple modulation. Limited ZVS range. Transformer large currents. LV DC capacitor: very large RMS current. DAB (Opt. Mod.) Lowest component count. Avoids DC inductor. Reduced circulating current. Reduced capacitor RMS currents. HV side switches: full range ZVS. LV side switches: full range ZCS. achievable. Complex modulation. LV DC capacitor: large RMS current. Three-Phase DAB Comparatively low capacitor RMS currents. Avoids DC inductors. Reduced circulating currents. Limited ZVS range. High component count. LV DC capacitor: rahter large RMS currents. LLC (Conv. Mod.) Slightly reduced component stresses compared to the DAB. Avoids DC inductors. Simple modulation. Large L and C. Limited ZVS range. Transformer: large circulating currents. LV DC capacitor: very large RMS currents. 2.3. Topologies comparison 17 Topology Advantages Disadvantages LLC (Opt. Mod.) Avoids DC inductors. Reduced circulating currents. Reduced capacitor RMS currents. HV side: full range ZVS. LV side switches: full range ZCS achievable. Rather large L and C. LV DC capacitor: large RMS currents. Complex modulation. Full Bridge Converter Current Fed Full Bridge LV side DC capacitor: low RMS currents. HV side: full range ZVS. Large DC inductor required. Snubber may be needed. Limited operating voltage range. Current Doubler Lowest transformer currents: lowest losses in contact resistances (e.g. transf. terminal). Lowest switches currents: better MOSFETs available (lower losses). LV side: no high-side gate drivers. LV side DC capacitor: low RMS currents. HV side: full range ZVS. Increased transformer VA rating. Large DC inductors required. Snubber may be needed. Limited operating voltage range. 18 Chapter 2. State-of-the-art analysis Topology Advantages Disadvantages Current Fed Push Pull LV side: no high-side gate drivers. LV side DC capacitor: low RMS currents. HV side: full range ZVS. Increased transformer VA rating. Large DC inductor required. Snubber may be needed. Limited operating voltage range. Regarding this comparison, a promising power circuit selected for studying is the Full Bridge with Current Doubler. Chapter 3 Working principle description The topology selected for the study is Bidirectional and Isolated DC to DC Phase Shift Converter with Current Doubler Rectifier (CDR) . There are some keywords that contain very important information about this topology. Bidirectional Converter (BDC) . First, the converter is able to transfer power in both directions. A simple way to achieve this feature would be modify conventional topologies by replacing rectifier diodes with bidirectional switches. Therefore, it is possible for the converter to work in buck mode –HVDC to LVDC –; and boost mode –LVDC to HVDC –. Phase Shift Modulation (PSM) . Phase shift modulation is an elementary modulation scheme whose parameter control is duty cycle (D). Current Doubler Rectifier (CDR) . Low voltage side has to withstand high current values. Moreover, the higher power is requested, the higher current is –the voltage level is established by specifications –. 19 20 Chapter 3. Working principle description Full Bridge Current Doubler Figure 3.1: Current doubler rectifier original topology, [8] Figure 3.1 shows the basic topology which meets all those features mentioned above. Nevertheless, a change will be introduced in the topology in order to limit voltage spikes at LV switches (T5 and T6) due to hard turn-off. The resulting topology is shown in Figure 3.2. V aux Figure 3.2: Current doubler rectifier modified topology, [8] It is important to notice that V 1 represents high voltage DC level (HVDC) and V 2 represents low voltage DC level (LVDC). Looking inside the topology, there is a semiconductors full bridge at HV side and a current doubler at LV side. Transistors are needed instead of diodes in order to make a bidirectional power transfer. Transformer, represented by two coupled inductors, provides galvanic isolation between high and low voltage sides. Inductor connected in series with transformer 21 HVDC winding emphasizes the leakage inductance, represented by "L". Regarding the general architecture of bidirectional and isolated DC to DC converter, Figure 2.1, circuit in Figure 3.2 also incorporates a basic filter network consisting of a capacitor connected in parallel with HVDC and LVDC. Some of these elements have to be dimensioned to meet specifications and design criteria. This aspect will be addressed later. As explained below, power transfer is controlled by switches states. A modulator turns on and turns off switches according to the PSM technique and its control parameter. Moreover, some basic ideas must remain as underlying aspects for the current theoretical approach: Switches are considered ideal, so switching will be assumed instantaneous. This simplifies performance description and waveform analysis. Switches on the secondary side (HV or LV side, depends on the operating mode) are intended to act as power rectifiers. This physical behaviour is called Synchronous rectification, SR. Regarding which side is powered, it is possible to distinguish two basic modes of operation: Boost mode. LVDC to HVDC. Buck mode. HVDC to LVDC. These operating modes are explained in detail separately. For both modes, the following relationship between V1, V2and D applies (Equation 3.1), [11]: D=2nV 2 V1(3.1) 22 Chapter 3. Working principle description 3.1 Steady State Analysis The study will be carried out with a fixed duty cycle. A basic physical analysis of the circuit will be exposed. The explanation will be carry out considering a switching period (TS). Four basic states are described during a period. 3.1.1. Buck mode Turning-on and turning-off the right switches at the right time allows the voltage waveform in the transformer shown in Figure 3.7 which is necessary to perform a voltage reduction (from V1to V2). Power delivery mode (t0→t1) During this time T1 is ON, T2 is OFF, T3 is OFF and T4 is ON. The current flows through active semiconductors in HV side, as it is shown in Figure 3.3. To allow power transfer, T5 is OFF and T6 is ON. This time interval is approximately D·TS 2. [12] V aux Figure 3.3: Power Delivery Mode, [13] At this interval of time current through transformer increases. The relation between current and voltage is given by the Equations 3.2 and 3.3. VAC1 =VAC2 ·n+VL(3.2) 3.1. Steady State Analysis 23 VL=L·dIAC1 dt (3.3) This behaviour is verified according to Figure 3.7. The slope of current through transformer is positive. Freewheeling Mode (t1→t2) The next interval of time starts when T4 is turned off. It is characterized by the following HV side semiconductors states: T1 ON, T2 OFF, T3 ON and T4 OFF. In LV side both switches are ON. The current path is drafted in Figure 3.4. [12] V aux V aux Figure 3.4: Freewheeling Mode, [13] In this case, there is not net input current. Moreover, the slope of current through transformer is negative. Secondary voltage (V AC2 ) is closed to zero. This second interval ends at the middle of the cycle, i.e. TS 2. Power Delivery Mode (t2→t3) The third global state of the HV side semiconductor bridge is determined byT1 OFF, T2 ON, T3 ON and T4 OFF. With this configuration input current is allow to flow, as it is shown in Figure 3.5. In this case, T5 is required to be ON and T6 OFF. [12] 30 Chapter 3. Working principle description Fundamental magnitudes illustration -500 -400 -300 -200 -100 0 100 200 300 400 500 VAC1 IAC2 ILDC2a ILDC2b 0 1 T1 T2 0 1 T3 T4 0 1 T5 T6 Ts Freewheeling Power delivery AC 2 n·V t0t1t2t3 Figure 3.13: Transformer and DC inductors magnitudes - Boost mode 3.1. Steady State Analysis 31 In the first place, it is quite apparent that in boost mode diodes allow current to flow during short interval time; this phenomena results in an overvoltage on LV side of the transformer. Overvoltage does not appear in Figure 3.7. The maximum value is limited by active snubber auxiliary circuit, i.e. clamped diodes and V aux which is set to 150 V. Transformer current waveform is also different in boost and buck mode. During power delivery mode, current decreases -regarding absolute valuein boost mode and increases in buck mode. During freewheeling period this magnitude is closed to zero in boost mode, and it is not in buck mode. -20 -10 0 SWITCHES CURRENT - BOOST T 1 T 2 -20 -10 0 T 3 T 4 0 50 100 T 5 T 6 Figure 3.14: Current through switches - Boost mode In boost case, current waveforms of (T1, T2) and (T3, T4) are more similar each other than in buck case. 32 Chapter 3. Working principle description 3.2 Phase-Shifted Modulation In this section modulation technique is outlined briefly. The basic control principles are described: Switches in the same leg never are switched on at the same time. Hence, the duty cycle between them is almost 50%, because it is necessary to keep a delay time, also called dead time , between the switch-on of one and the switch-off of the other -of the same branch-. Switches pairs of the two legs of HVDC full bridge are delay certain time. This time is controlled with a parameter called duty cycle , D, and it depends on operating point. From a physical point of view, power transfer occurs during this time. Switches on LVDC side are controlled according to SR control strategy. The code that implements phase-shifted technique is attached in Appendix A.2.2. There are modulation strategies that can achieve loss reduction in some operating points; two of them are described below. Moreover, there could be some modulation scheme that improve switching process in boost mode. It will be discussed in Chapter 9. 3.2.1. Soft Switching Basic requirements of converters are high efficiencies and small sizes. Increasing switching frequency may allow to reduce size, [ 16 ], but by this way switching losses also raise. A solution for this problem could be use soft switching techniques, [ 16 ], such as Zero Voltage Switching (ZVS) or Zero Current Switching (ZCS). [17]. Switching losses are due to drain current and drain to source voltage overlap and discharge of stored energy in C oss . During ZVS, current at turn on is oriented from source to drain, which discharge MOSFET output capacitance before turning the device on, [ 18 ]. By this way, V DS goes closed to zero before semiconductor begins to conduct, hence switching on losses are nearly eliminated. Notice that switching off losses remain with ZVS. In the HV bridge, ZVS can be achieved when, after a hard 3.2. Phase-Shifted Modulation 33 turn-off, the current in the leakage inductance did not change its sign after dead time. In this manner, at turn-on, leakage inductance is circulating through the off mosfet, and ZVS can be achieved. To allow wide ZVS range, the modulator dead time must be large enough to avoid cross conduction, but short enough to avoid L sign change. 3.2.2. Synchronous Rectification Current MOSFETs technology allow lower voltage drop compared to diodes, so rectification becomes more efficient when current flows through the first ones. This technique require high modulator precision: switches should be open exactly during the time they are not conducting. Moreover this issue, there are some design trade-offs implementing SR, [19], [20]. 3.2.3. Detailed modulation scheme The concrete scheme of PSM implemented is shown in Figure 3.15. 0 1 SWITCHES GATE SIGNAL T 1 T 2 0 1 T 3 T 4 0 1 T 5 T 6 Figure 3.15: Switches logic gate signal 34 Chapter 3. Working principle description Notice that there is a time between the switch turn-off and the turn-on of the other same-branch switch. A fine tune of it, usually called dead time , is crucial because this parameter affects to several aspects of converter performance (avoiding short circuit, achieving ZVS). 0 1 DEAD TIME T 1 T 2 Figure 3.16: Dead time As it appears in Figure 3.16, between T1 turn-off and T2 turn-on there is a time during which both logic gate signals are "OFF" because real switches -for instance, MOSFETsneed to discharge and charge, respectively, gate-source capacitances to reach a real "OFF" or "ON" state. Scheme modulation proposed in Figure 6.5 allows to get, in buck mode: Synchronous rectification. ZVS in almost the whole operating domain. Nevertheless, dead time has to be calculated accurately in order to guarantee ZVS and SR, when it is possible. In boost mode none of these enhancement strategies have been reached with the modulation profile used. Chapter 4 Specifications and criteria design The criteria design has been established based on operating range (Section 4.1 and 4.2) and some design assumptions taken from [8] (Section 4.3). 4.1 Operating points In first place, domain for input variables is specified in Table 4.1. Table 4.1: Design voltage thresholds Magnitude Buck operating mode Boost operating mode V1[V] 235 < V1< 325 250 < V1< 360 V2[V] 22 < V2< 30 22 < V2< 30 P [W] 0 < P < 3000 -3000 < P < 0 35 36 Chapter 4. Specifications and criteria design 4.2 Nominal operating point In second place, nominal operating point is defined in Table 4.2. Table 4.2: Nominal operating point V1[V] V2[V] P [W] 270 28 ±3000 4.3 Additional design criteria In third place, it will be necessary to include some assumptions, taken from [ 8 ]. TCis less or equal than 7.5%TS. Tfree is less or equal than 2.5%TS. ∆ILDC2a+2b is less or equal than 40%P2 V2 Chapter 5 Components design 5.1 Transformer 5.1.1. Simple model Simple model, as discussed below, only considers n and L. Turn ratio In order to estimate n, the next steps have been followed. First of all, a relationship between V 1 , V 2 , n and D has been taken into account, Equation 3.1. Regarding D definition, it is obtained the following expression. D=ton TS=1−2fs(TC+Tfree)(5.1) By replacing T C and T free with their maximum values in Equation 5.1, the maximum achievable value ofD is reached. Then, setting minimum value of V 1 and maximum value of V 2 in Equation 3.1, 37 38 Chapter 5. Components design the maximum value of n that can be used is obtained. n=V1min 2V2max ·[1 −2fs·(TC+Tfree)] (5.2) Maximum admissible value for n results: Table 5.1: Transformer turn ratio results Buck mode Boost mode Design value nminbuck = 3.1333 nminboost = 3.3333 n = 3 Leakage inductance A suitable design criteria for leakage inductance would be to extend as far as possible ZVS condition. It is intended to reduce current variation during switching process. L = 1.5 µH The proposed value has also been set according to [ 12 ], which consider the same basic design criteria and operating conditions closed to nominal operation point, Table 4.2 5.1.2. Advanced model Turn ratio is the only needed parameter for the ideal transformer model. Actually, transformers present losses both in the core and in windings due to multiple effects (hysteresis, ohmic losses, Eddy currents). Moreover, at high frequency transformer model has to be completed with parasitic capacitances. In this research, the only parameter takes into account in a more advanced design is magnetizing inductance, Lm. A typical value of Lmis presented below. Lm= 1 mH Including L m explicitly allows to check that current through transformer core has zero value average and hence the core is unsaturated. 5.2. DC Inductor 39 5.2 DC Inductor 5.2.1. Simple model Inductance of DC inductors is directly related with peak-to-peak value of LV side current. Hence, in order to estimate these inductances, the following assumption has been made. ∆ILDC2a+2b≤40% ·|P2| V2(5.3) Regarding peak-to-peak current definition and assuming an ideal behaviour, ∆ ILDC2a+2b may be expressed as it follows. ∆ILDC2a+2b=max[iLDC2a(t)+iLDC2b(t)] −min[iLDC2a(t)+iLDC2b(t)] =(V1/n−V2)·(D/2) fs·LDC (5.4) Imposing the additional condition: LDC2a =LDC2b =LDC (5.5) Combining 5.3, 5.4 and 5.5, the following expression for DC inductor is obtained. LDC2a=D/2 fs·∆ILDC2a+2b·(V1 n−V2)(5.6) The aim is to find the minimum value that fulfils Equation 5.3 at the worst operating condition. LDC2amin =D/2 fs·40%|P2|/V2·max(V1 n−V2)(5.7) Regarding nominal power (see Chapter 4, Table 4.2) and Equation 3.1, the following numerical results have been obtained: 46 Chapter 6. Simulation models and Software tools subsections of Chapter 5. Modulador 1 2 + + TF M1 g D S M1 g D S M2 M2 g D S M4 M4 g D S M3 M3 + Llk + Ldc2a + Ldc2b g D S M5 g D S M6 + a k a k Vaux 1 Vhigh+ 2 Vlow+ 3 Vhigh- 4 Vlow- M5 M6 + Figure 6.1: Basic MATLAB/Simulink model 6.1.2. Advanced model A more specific Simulink library has been used to develop an accuracy numerical model. In this case, it is Simscape/Electronics Simulink library. Diodes and L DC incorporate ohmic resistances and hence these models include ohmic losses. Transformer magnetizing inductance is also taking into account. But, above all, switches are modelled as real semiconductors -MOSFET in this casewith ohmic losses and also parasitic effects. In this case, listed parameters in Chapter 5, Section 5.5 have been added to the model and realistic effects have been taking into account, such as parasitic inductance due to MOSFETs package and switches layout. Figures 6.2 and 6.3 illustrate it. To see concrete values, go to Chapter 5. 6.1. MATLAB/Simulink Models 47 Figure 6.2: HV MOSFET model with parasitic effects Figure 6.3: LV MOSFET model with parasitic effects Face to results that will be obtained with advanced model, it should be noted that at HV side each switch is compound by one single MOSFET, whereas at LV side each switch is compound by eight MOSFETs connected in parallel. This consideration is also important because results under actual operating conditions will be different to what it will be obtained with simple model. 48 Chapter 6. Simulation models and Software tools Both models, simple one and advanced one, have been implemented so that buck and boost simulations can be programmed. It has been achieved using ideal circuit breakers that activate and deactivate pertinent voltage source and load in each case. Circuit breakers state are preset before simulation calling a parameter function. A programming example is given in Appendix A.2.1. 6.2 Modulator Modulator has the same design for both models. Figure 6.4: Simulink block diagram of Modulator Modulation programming has been carried out time independently. Comparing periodic reference triangular waveform which depends on switching frequency and constant values according to Figure 6.5 is possible to generate switches gate signal. Figure 6.5 clarifies this idea. To certain timed value, e.g. t = 0.5 ·D·TS , corresponds an specific vertical value, regarding relationship between similar triangles. 6.2. Modulator 49 Reference signal Ts x y 0D·Ts 2 x1= y1= 1-D Ts 2 Figure 6.5: Gate signal generation principle Modulator code is attached in Appendix A.2.2. Chapter 7 Results Just as in the previous chapter, the content of this one are divided into two categories: results coming from Simple model and results coming from Advanced model. 7.1 Simple model results Figures from 7.1 to 7.16 have a double objective. On the one hand, they reveal circuit performance patterns when input and output voltage level are modified. On the other hand, by knowing certain magnitudes help to make a preliminary sizing of components and also would allow to do an efficiency estimation. Choosing suitable semiconductors -MOSFET in this case- to carry out switching function is particularly crucial. 51 52 Chapter 7. Results 7.1.1. Switches Max. val. = 16.6 at V1 = 303 , V2 = 22 12 320 20 300 14 280 High voltage range [V] 25 Low voltage range [V] Buck mode 3000 W 16 260 SWITCH T1 RMS current [A] 240 18 30 220 20 Figure 7.1: Current through HV side switches in buck mode operation 8 Max. val. = 11.1 at V1 = 250 , V2 = 22 350 20 10 High voltage range [V] 300 25 Low voltage range [V] Boost mode 3000 W SWITCH T1 RMS current [A] 12 250 30 14 Figure 7.2: Current through HV side switches in boost mode operation 7.1. Simple model results 53 Figures 7.1 and 7.2 show RMS current through respective switches, and they also point maximum values -red ball-. Maximum RMS currents are: 16.6 A in buck mode and 11.1 A in boost mode. Max. val. = 89.8 at V1 = 303 , V2 = 22 320 70 20 300 80 280 High voltage range [V] 25 Low voltage range [V] Buck mode 3000 W 260 SWITCH T5 RMS current [A] 90 240 30 100 220 Figure 7.3: Current through LV side switches in buck mode operation Max. val. = 89 at V1 = 360 , V2 = 22 350 70 20 80 High voltage range [V] 300 25 Low voltage range [V] Boost mode 3000 W SWITCH T5 RMS current [A] 90 250 30 100 Figure 7.4: Current through LV side switches in boost mode operation 54 Chapter 7. Results Figures 7.3 and 7.4 show RMS current through LV switches. Current is much higher than in HV switches clearly. Maximum values are: 89.9 A in buck mode and 89 A in boost mode. Knowing maximum RMS help to select suitable real semiconductors for switches. Moreover, this maximum values, together with voltage drop, would allow to estimate maximum VA ratings for switches. Information obtained from this preliminary results and nominal operating point specifications (Chapter 4) justify MOSFET selection for both HV and LV sides. To see their main characteristics in detail, go to Chapter 5, Section 5.5. 320 20 20 300 22 280 Max. val. = 22 at V1 = 235 , V2 = 22 High voltage range [V] 25 Low voltage range [V] Buck mode 3000 W 260 SWITCH-OFF CURRENT T1 [A] 24 240 30 26 220 Figure 7.5: Current at SWITCH-OFF on HV side switches in buck mode operation 7.1. Simple model results 55 0350 20 High voltage range [V] 300 2 25 Low voltage range [V] Boost mode 3000 W SWITCH-OFF CURRENT T1 [A] Max. val. = 3.72 at V1 = 360 , V2 = 30 250 30 4 Figure 7.6: Current at SWITCH-OFF on HV side switches in boost mode operation Figures 7.5 and 7.6 present current at the switching-off instant for HV switches. In boost mode this current is very low -the maximum value reached is 3.72 A-, whereas un buck mode it is higher, from 20 to 22 A -maximum value reached is 22 A. Max. val. = -62.9 at V1 = 235 , V2 = 22 320 -60 20 300 280 High voltage range [V] 25 Low voltage range [V] Buck mode 3000 W -40 260 SWITCH-OFF CURRENT T5 [A] 240 30 220 -20 Figure 7.7: Current at SWITCH-OFF on LV side switches in buck mode operation 62 Chapter 7. Results It can be seen in Figures 7.13 to 7.16 that RMS currents through capacitors are very similar in both modes and even in both HV and LV side. Nevertheless, this result does not obey to physical reason: if other design criteria for L DC would be considered, those similar values would not have been get. Again, maximum values obtained from this results allow to choose suitable capacitors. 7.2 Advanced model results Information presented in this section try to highlight converter efficiency in certain operating points. Before a brief explanation about numeric results, some definitions are going to be established in order to understand them better. It is important to notice that the only losses considered come from switches mainly. Hence, converter efficiency gives information about switches efficiency. Switch losses can be separated into conduction losses and switching losses, [ 27 ]. They are calculated as indicated in Equations 7.1 to 7.4. ¯ PCOND =¯ PCONDHV +¯ PCONDLV (7.1) ¯ PCONDHV =RDSonHV ·RMS(IHV )(7.2) ¯ PCONDLV =RDSonLV ·RMS(ILV )(7.3) ¯ PSW =(¯ PIN −¯ POUT )−¯ PCOND (7.4) Where P IN denotes input power, P OUT denotes output power, P CONDi denotes conduction losses, P SW denotes switching losses, RMS(I i ) denotes switch RMS current, 7.2. Advanced model results 63 and subindex i makes reference to either HV or LV. Converter efficiency is calculated according to Equation 7.5. η=Pout Pin ·100 (7.5) It is important to note that within switching losses are included passive snubber losses. Table 7.1 summarizes this section results. Table 7.1: Advanced model results V1V2PNOM PIN POUT PCOND PSW η Buck mode 270 22 1500 1344.0 1278.2 28.2 37.6 95.1 270 28 1500 1387.1 1330.1 20.4 36.5 95.9 325 22 1500 1362.7 1282.6 28.0 52.1 94.1 325 28 1500 1404.2 1332.1 21.0 51.0 94.9 270 22 3000 2436.2 2301.0 91.0 44.2 94.5 270 28 3000 2585.2 2477.8 64.9 42.4 95.8 325 22 3000 2466.2 2317.4 89.9 58.9 94.0 325 28 3000 2611.6 2489.4 65.2 57.0 95.3 Boost mode 270 22 1500 1549.2 1434.5 22.2 92.6 92.6 270 28 1500 1568.1 1475.4 16.7 75.9 94.1 325 22 1500 1586.4 1442.5 21.2 122.7 90.9 64 Chapter 7. Results 325 28 1500 1604.8 1483.0 16.1 105.7 92.4 270 22 3000 2989.2 2599.6 86.1 303.5 87.0 270 28 3000 3047.9 2775.3 59.7 212.9 91.1 325 22 3000 3087.4 2625.8 83.2 378.4 85.0 325 28 3000 3133.3 2799.4 56.3 277.6 89.3 An overview of last column shows that efficiency in boost mode is lower than buck mode in any case. Whereas efficiency is equal or higher than 94% in buck mode, maximum value in boost mode is 94.1%. If results at nominal power are compared with half nominal power, the conclusion is that differences in boost are much higher than in buck mode. Differences are percentage tenths in buck mode, whereas they are percentage units in boost mode. Attending to switches losses, conduction losses are approximately similar but in boost mode switching losses grow up enormously. Chapter 8 Conclusions Bidirectional and Isolated Current Doubler Topology with clamped diodes is a promising topology to develop power converters. It also allows modularity implementation, which is important to achieve higher power levels than the optimal operating point of single brick. In contrast with other topologies, important advantages of this one are low RMS currents at both HV and LV side switches and also at transformer, which involves lower conduction losses. Another advantage is low RMS current through DC link capacitors, which involves smaller size of them. From reliability point of view, this topology does not have too many components. The lower number of components, the lower failure probability. Project objective has been to study working principle of this topology and, taking a single modulation technique, perform numerical simulations to obtain a first order estimation results of efficiency. As in real life, it is necessary to follow an iterative process. So with information about current and voltage over ideal switches, real semiconductors have been selected in order to do a more accurate efficiency estimation, since switches are components with higher losses, especially at high frequency. As it can be checked in first section of Chapter 7, switches are not withstand currents too high. In HV side they are specially low, so VA ratings also are low for this components. Essential design parameters to be considered are efficiency and power density. 65 66 Chapter 8. Conclusions This study has been focused on estimating the topology efficiency at certain operating points in order to ensure quantitatively how good is the topology under test. Although power density has not been calculated, parameters which affect it have been taken into account, such as switching frequency –the higher f s is, the smaller magnetics components are but the higher switching losses are– ; voltage and current ratings of DC link capacitors, number of components, and so on. From efficiency point of view, Current Doubler Converter is more efficient working in buck mode than in boost mode, since switching losses are lower -regarding modulation technique programmed-. Consider an enhanced modulation technique would reduce losses in boost mode, by avoiding voltage spikes at LV switches at turn-off. It should not be forget that real power circuits have more losses sources. DC inductors and transformers losses should be taking into account in a deeper efficiency analysis of the converter. Chapter 9 Future Work 9.1 PSpice simulations Currently there are several software based on PSPICE solver. A fine calculation of efficiency and VA ratings should be done with them, since they provide accurate results for power electronics circuits. Moreover, thermal considerations -dynamic thermal model for examplecould be taking into account with this tools. Some manufacturers, as Infineon Technologies , supply PSPICE semiconductor models -MOSFETs, diodes,...- and they also suggest the best solver configuration to make the program run. 9.2 Alternative modulation technique Switches gate signals are driven using Single PSM in this project. There is not any difference between buck and boost mode from gate signals point of view. Nevertheless, as it is proposed in [ 8 ], there is another modulation scheme that improves the implemented one. Alternative modulation would generate differences between operating modes 67 68 Chapter 9. Future Work gate signals, since they are not symmetric (even if they have the same switches gate signals). Basically, it calculates the freewheeling time and switching-on and switchingoff LV side switches are modified -reduced in factaccording to this time. Figures 9.1 and 9.2 illustrate the idea. Figure 9.1: Alternative modulation scheme for buck mode, [8] Figure 9.1 shows that in buck mode, whit the proposed switching scheme for HV side switches, during the freewheeling period T5 and T6 remain ON and they are OFF only during the effective power delivery. Freewheeling period occurs in buck mode at the beginning, i.e. before power transfer period as it can be seen in Figure 9.1. As result, the time during LV swithces are ON is reduced in a time quantity denoted by ∆Tin respect to time during switches of each HV branch are ON simultaneously. 9.2. Alternative modulation technique 69 Figure 9.2: Alternative modulation scheme for boost mode, [8] In boost mode, on the other hand, freewheeling period takes place after power delivery period. However, in the same way as in buck mode, T5 and T6 only are ON during effective power delivery whereas HV switches (T1 to T4) are ON during effective power delivery plus the time interval called ∆T. Moreover, alternative modulation in boost mode adds an additional advantage, because it allows to avoid voltage spikes on LV switches. The main disadvantage of this technique is that, even if ∆T could be calculated accurately in steady state, it would be necessary a complex solver to calculate it during dynamic transient, because if at any switching event the turning-off current was from drain to source, a voltage spike, possibly destructive, would occur. Another possible disadvantage of this modulation scheme are higher RMS currents in LV switches. 70 Chapter 9. Future Work 9.3 Further simulation analysis Advanced model simulations results have permitted to show an estimation of efficiency and its behaviour with the domain variables. Nevertheless, these simulations take too time and only a few operating points have been analysed. It would be desirable to explore more operating points of the whole domain in order to achieve stronger conclusions. As mentioned in Chapter 7, it would be possible to calculate efficiency using presented magnitudes over the whole domain. It would be interesting to make a comparison between efficiency obtained from advanced model simulation results and efficiency calculated regarding operating points from simple model results. Appendices 71 78 A.1. Comparative results between medium power and full power LV SWITCH, P = PN/2= 1500 W V1[V]/V2[V] 22 23 25 26 27 29 30 250 44.26 42.73 39.92 38.67 37.51 35.43 34.48 278 44.11 42.51 39.67 38.41 37.23 35.09 34.12 305 44.32 42.73 39.83 38.57 37.37 35.18 34.19 333 44.96 43.36 40.43 39.14 37.90 35.76 34.72 360 46.04 44.39 41.47 40.13 38.93 36.69 35.71 Table A.11: RMS current [A] on LV switch for PN/2in boost mode LV SWITCH V1[V]/V2[V] 22 23 25 26 27 29 30 250 -47.38 -47.78 -48.00 -48.15 -48.28 -47.61 -48.06 278 -48.23 -48.26 -48.34 -48.11 -48.54 -48.65 -48.58 305 -48.44 -48.32 -48.76 -48.84 -48.70 -48.50 -48.53 333 -48.96 -49.03 -48.87 -48.26 -48.83 -49.28 -49.38 360 -48.86 -48.06 -48.96 -49.46 -49.57 -48.91 -47.88 Table A.12: Percentage change in RMS current on LV switch for PN / 2with regard to PNin boost mode A.1. Comparative results between medium power and full power 79 TRANSFORMER, P = PN/2= 1500 W V1[V]/V2[V] 22 23 25 26 27 29 30 250 8.90 8.82 8.71 8.66 8.62 8.50 8.44 278 8.96 8.96 8.89 8.88 8.86 8.75 8.72 305 9.16 9.27 9.31 9.32 9.32 9.29 9.26 333 9.64 9.81 9.91 9.94 9.95 10.04 10.01 360 10.25 10.36 10.63 10.68 10.77 10.81 10.87 Table A.13: RMS current [A] on transformer for PN/2in boost mode TRANSFORMER V1[V]/V2[V] 22 23 25 26 27 29 30 250 -43.17 -40.23 -36.51 -30.83 -24.22 -42.86 -39.40 278 -34.89 -28.61 -22.16 -42.01 -38.17 -32.74 -25.77 305 -17.83 -41.61 -37.47 -31.79 -24.56 -16.32 -41.16 333 -36.83 -30.95 -23.47 -14.81 -40.55 -36.06 -29.53 360 -21.25 -13.01 -40.30 -35.61 -28.98 -20.74 -12.10 Table A.14: Percentage change in RMS current on transformer for PN / 2with regard to PNin boost mode 80 A.1. Comparative results between medium power and full power LDC2A,P=PN/2= 1500 W V1[V]/V2[V] 22 23 25 26 27 29 30 250 8.90 8.82 8.71 8.66 8.62 8.50 8.44 278 8.96 8.96 8.89 8.88 8.86 8.75 8.72 305 9.16 9.27 9.31 9.32 9.32 9.29 9.26 333 9.64 9.81 9.91 9.94 9.95 10.04 10.01 360 10.25 10.36 10.63 10.68 10.77 10.81 10.87 Table A.15: RMS current [A] on LDC2a for PN/2in boost mode LDC2a V1[V]/V2[V] 22 23 25 26 27 29 30 250 -46.20 -46.63 -47.11 -47.71 -48.86 -46.10 -46.62 278 -47.06 -47.77 -48.77 -45.98 -46.27 -46.82 -47.48 305 -48.48 -45.82 -46.09 -46.47 -47.26 -48.07 -45.53 333 -45.75 -46.19 -46.94 -47.25 -45.04 -45.22 -45.37 360 -45.48 -46.24 -44.72 -44.84 -44.96 -44.94 -45.59 Table A.16: Percentage change in RMS current on LDC2a for PN / 2with regard to PNin boost mode A.2. Matlab code 81 A.2 Matlab code A.2.1. Code for setting a simulation function [param]=current_doubler_parameters(V1, V2, P_act, model_type) % Time parameters param.Tint = 1e-9; % s param.tm = 50e-9; % s param.fs = 100e3; % Hz param.Ts = 1/param.fs; % s % Operating point parameters param.Vhigh = V1; % V param.Vlow = V2; % V param.Pnom = abs(P_act); % W % Operating mode defined by power sign if sign(P_act)>=0 op_mode = ’buck’; else op_mode = ’boost’; end % Components parameters % MOSFET switch model_type case ’simple’ param.Rds_on_lv = 36.25e-3; %Ω param.Ron_d_lv = 0.8/64; %Ω param.Vd_m_lv = 0.8; % V param.Rds_on_hv = 36e-3; %Ω param.Ron_d_hv = 5/30; %Ω 82 A.2. Matlab code param.Vd_m_hv = 5; % V case ’advanced’ param.source_gain_hv = 20; param.source_gain_lv = 15; param.L_par_mos = 2e-9; % H param.C_snb = 20e-9; % F param.R_snb = 5; %Ω % Mosfet HV side param.Rgate_high_on = 6; %Ω param.Rgate_high_off = 12; %Ω param.Rds_on_hv = 36e-3; %Ω param.Ids_hv = 35; % A param.Vgs_hv = 15; % V param.Vth_hv = 1.875; % V param.Rs_hv = 1.42e-3; %Ω param.Rd_hv = 77.52e-6; %Ω param.Ciss_hv = 1750; % nF param.Crss_hv = 9.5; % nF param.Coss_hv = 150; % nF param.Vfd_hv = 5; % V param.Ron_d_hv = 5/30; %Ω param.lambda_hv = 0.01; % Mosfet LV side param.Rgate_low_on = 6; %Ω param.Rgate_low_off = 12; %Ω param.Rds_on_lv = 36.25e-3; %Ω param.Ids_lv = 64; % A param.Vgs_lv = 10; % V param.Vth_lv = 2.2; % V param.Rs_lv = 878e-6; %Ω param.Rd_lv = 50e-6; %Ω param.Ciss_lv = 5340; % nF param.Crss_lv = 4; % nF param.Coss_lv = 240; % nF A.2. Matlab code 83 param.Vfd_lv = 0.8; % V param.Ron_d_lv = 0.8/64; %Ω param.lambda_lv = 0.25; end % TRANSFORMER param.N2N1 = 3; param.L_lk = 1.5e-6; % H switch model_type case ’simple’ param.Rm = 1e7; %Ω case ’advanced’ param.Rm = 1e7; %Ω param.Lm = 1e-3; % H end % DC INDUCTOR param.L_dc = 3.7e-6; % H param.R_ldc = 0; % VAUX AND CLAMPED DIODES param.Rd = 20e-3; %Ω param.Vd = 1.2; %Ω param.Vaux = 150; % V % CAPACITORS param.Chigh = 500e-6; % F param.Clow = 500e-6; % F % CIRCUIT BREAKER RESISTANCE param.Ron_break = 1e-15; %Ω 84 A.2. Matlab code % OPERATING MODES SELECTION switch op_mode case ’buck’ param.operating_mode = 1; % Circuit breakers state param.gate_break_source_hv = 1; param.gate_break_source_lv = 0; param.gate_break_load_hv = 0; param.gate_break_load_lv = 1; param.gate_hv_cap = 0; param.gate_lv_cap = 1; % DC networks voltage param.Vin = V1; param.Vout = V2; % Adjust load for nominal power param.Rload = param.Voutˆ2/param.Pnom; % Capacitors initial voltage param.Chigh_initial = 0; param.Clow_initial = 0; param.D_nom = (2*param.Vout*param.N2N1)/param.Vin; case ’boost’ param.operating_mode = 2; % Circuit breakers state param.gate_break_source_hv = 0; param.gate_break_source_lv = 1; param.gate_break_load_hv = 1; param.gate_break_load_lv = 0; param.gate_hv_cap = 1; param.gate_lv_cap = 0; % DC networks voltage A.2. Matlab code 85 param.Vin = V2; param.Vout = V1; % Adjust load for nominal power param.Rload = param.Voutˆ 2/param.Pnom; % Capacitors initial voltage param.Chigh_initial = param.Vout*0.9; param.Clow_initial = 0; param.D_nom = (2*param.Vin*param.N2N1)/param.Vout; end end A.2.2. Modulator algorithm function [p1, p2, p3, p4, p5, p6, D_eff] = fcn(u, fs, tm, D_nom, operating_mode) Ts = 1/fs; % Hz if operating_mode==1 % BUCK MODE D_eff = D_nom; y0 = 1-(tm/(Ts/2)); x0 = 1-y0; y2 = 1-(D_eff+(tm)*2/Ts); x2 = 1-y2; y4 = 1-(D_eff); x4 = 1-y4; % GATES 1 AND 2 if u >= 0 p2 = 0; if u>y0 p1 = 0; else p1 = 1; 86 A.2. Matlab code end else p1 = 0; if u>=-(x0) p2 = 0; else p2 = 1; end end % GATES 3 AND 4 if u>y2 || u<-(x4) p3 = 0; if u>y4 || u<=-(x2) p4 = 1; else p4 = 0; end else p3 = 1; p4 = 0; end % GATE 5 if u>=y4 && u<=1 p5 = 0; else p5 = 1; end % GATE 6 if if u<=0 && u>=-(x4) p6 = 0; else p6 = 1; end else % BOOST MODE A.2. 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