Citations refer to the original publication, not to a Scieee localized version.
Acosta Jiménez, A. J., Barriga Barros, Á., Valencia Barrero, M., Bellido Díaz, M. J., & Huertas Díaz, J. L. (1993). Modeling of Real Bistables in VHDL. IEEE Computer Society. https://doi.org/10.1109/EURDAC.1993.410677
Acosta Jiménez, Antonio José, et al. Modeling of Real Bistables in VHDL. IEEE Computer Society, 1993. https://doi.org/10.1109/EURDAC.1993.410677.
Acosta Jiménez, Antonio José, Ángel Barriga Barros, Manuel Valencia Barrero, Manuel Jesús Bellido Díaz, and José Luis Huertas Díaz. Modeling of Real Bistables in VHDL. IEEE Computer Society, 1993. https://doi.org/10.1109/EURDAC.1993.410677.
Acosta Jiménez, A. J. et al. (1993) Modeling of Real Bistables in VHDL. IEEE Computer Society. Available at: https://doi.org/10.1109/EURDAC.1993.410677.
A. J. Acosta Jiménez, Á. Barriga Barros, M. Valencia Barrero, M. J. Bellido Díaz, and J. L. Huertas Díaz, “Modeling of Real Bistables in VHDL,” IEEE Computer Society, 1993, doi: 10.1109/EURDAC.1993.410677.
@misc{acostajimenez1993modeling,
author = {Acosta Jiménez, Antonio José and Barriga Barros, Ángel and Valencia Barrero, Manuel and Bellido Díaz, Manuel Jesús and Huertas Díaz, José Luis},
title = {Modeling of Real Bistables in VHDL},
year = {1993},
publisher = {IEEE Computer Society},
doi = {10.1109/EURDAC.1993.410677},
url = {https://doi.org/10.1109/EURDAC.1993.410677}
}
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