Modeling of Real Bistables in VHDL
Abstract
A complete VHDL model of bistables including their metastable operation is presented. An RS-NAND latch has been modelled as a basic structure, orienting its implementation towards its inclusion in a cell library. Two applications are included: description of a more complex latch (D-type) and description of a circuit containing three latches where metastable signals are propagated. Simulation results show that the presented niodel provides very realistic information about the device behavior, which until now had to be obtained through electric simulation.
Full text
Modeling
o
Real Bis ables in
VHDL
Acos a,
A.J.',
Baniga,
A.',
Valencia, M.2, Bellido, M.J2 and Hue as
J.L.'
Dep .
o
Design
o
Analog Ci cui s. Cen o Nacional de Mic oelec 6nica,
Edi icio CICA, A da. Reina Me cedes s/n, 41012-Se illa (Spain)
'
also wi h he Dep . de Elec 6nica
y
Elec omagne ismo, Uni e sidad de Se illa.
also wi h he Dep . de Tecnologia Elec hica, Uni e sidad de Se illa.
Abs ac
A
comple e
VHDL
model o bis ables including hei
me as able ope a ion is p esen ed.
An
RS-NAND
la ch
has
been
modelled as a basic s uc u e, o ien ing i s
implemen a ion owa ds i s inclusion in a cell lib a y.
Two applica ions a e included: desc ip ion o a mo e
complex la ch (D- ype) and desc ip ion o a ci cui con-
aining h ee la ches whe e me as able signals a e p op-
aga ed. Simula ion esul s show ha
he
p esen ed niodel
p o ides e y ealis ic in o ma ion abou
he
de ice
beha io , which un il
now
had o be ob ained h ough
elec ic simula ion.
1:
In oduc ion
P ecise modelling
o
eal digi al sys ems o compo-
nen s h ough VHDL is an in e es ing ask i we wish. on
one hand, o main ain he inhe en ad an ages o high
le el modelling and simula ion, and on he o he , ade-
qua ely desc ibe hese ci cui s. The simplici y o desc ib-
ing digi al ci cui s is se iously a ec ed when hei
pe o mance is no ideal, o simply when, o speci ic
applica ions, hey mus be modelled mos p ecisely. In
many applica ions, he logic abs ac ion le el o ci cui
desc ip ions equi es
a
p ecise beha io model
o
i s
componen s. In ou case, we e e o memo y elemen s
ope a ing in me as abili y.
This communica ion p esen s eal desc ip ions o dig-
i al memo y elemen s like RS- ype asynch onous
la ches, and hei use
o
desc ibe D- ype le el-sensi i e
bis ables. These elemen s a e indispensable
o
pe o m
sequen ial sys ems. The VHDL desc ip ion ound in
li -
e a u e o his ype o elemen s only akes in o accoun
no mal beha io ,
o
in some cases. has implemen ed ou-
ines o de ec abno mal beha io
[
1.21; we encoun e ed
no e e ence in li e a u e ega ding he beha io model-
ling o memo y elemen s when hese ope a e abno mally
o
in me as abili y. The impo ance o his model lies no
only in he de ice i sel , bu also in
he
pe nicious in lu-
ence ha his ci cui may ha e on i s en i onmen , which
can also be modelled. The objec i e o his communica-
ion is he implemen a ion o VHDL ou ines o me as -
able beha io modelling.
This pape is s uc u ed
as
ollows: Sec ion 2 is a b ie
e iew o
he
aspec s ela ed o me as abili y in bis ables;
Sec ion
3
includes VHDL models o gene a ed la ches:
and Sec ion
4
p esen s and discusses wo applica ions o
he model gene a ed. Appendix
A
p esen s g aphic and
nume ical esul s o simula ions made wi h hese models.
2:
Me as able ope a ion in bis ables
When
a
bis able is igge ed by signals iola ing i s
ime es ic ions (se up lime, hold ime,...), i ope a es a
a poin o uns able equilib ium called me as able s a e
[3-5].
These exci a ions. also called ma ginal igge ing,
d i e he bis able om one s able s a e o he me as able
s a e. o esol e one o he logical s able s a es a e
a
ime which depends on he bis able and he ma ginal
ig-
ge ing i sel . The me as able ope a ion may be modelled
assuming ha he logic alue o he bis able ou pu is
inde ini e o an unbounded in e al o ime, a e a ma -
ginal igge ing. Consequen ly, me as abili y is
a
po en-
ial sou ce o e o s, which is
why
we conside mos
in e es ing he con empla ion o simula ion p ocesses o
his phenomenon.
A
a unc ional le el, he main p ob-
lems a e. on one hand, de e mine which ma ginal exci a-
ions lead
o
me as able ope a ion o he bis able, and on
he o he , o a speci ic ma ginal igge ing, wha is he
ime ha
he
ou pu main ain an inde ini e alue and
wha is he inal s a e eached.
The app oach ha
we
conside mos adequa e
is
o
model he basic bis able ( ha p esen basic me as able
ope a ion), and om his, model mo e complex bis ables.
Fo
his eason, ini ially we will only conside he case
o an RS- ype la ch cons uc ed wi h c ossed
NAND
ga es (Figu e la). The case o an
RS
la ch cons uc ed
0-81864350-1193 $3.00
0
1993
IEEE
460
--
4
e)
Figu e
1.
Ma ginal igge ing condi ions o
RS-NAND
la ch.
wi h
NOR
ga es is equi alen and
is
no p esen ed
o
b e i y in he communica ion.
The exci a ions causing me as abili y in he
RS-
NAND
la ch a e:
a) Viola ion o he hold ime (Thold): The ime in e -
al (8) be ween he ise o he
R
signal and he ise o he
S
signal is less han
he
hold ime (Figu e lb).
b) Viola ion o
he
se up ime (Tse up): The ime in e -’
al
(8)
be ween
he
ise o he
S
signal and he ise o he
R
signal is less han he se up ime (Figu e IC).
c)
Viola ion o he minimum pulse wid h: A na ow
pulse (wid h less han Tw il) is il e ed by he la ch due
o i s ine ial e ec , and
a
pulse wide han Twmin makes
he la ch ope a e no mally.
I
i s wid h is in e media e
( un pulse) i may cause me as abili y, when he s a e
imposed by he pulse does no coincide
wi h
he s o ed
s a e (Figu es Id and le).
The pa ame e s ci ed (Tse up. Thold. Tw il, Twmin)
depend on he bis able implemen a ion.
Nume ous wo k o di e en ypes o bis ables and
echnologies ha e been p esen ed o adequa ely model
me as able ope a ion o bis ables.
A
model amply used,
bo h heo e ically
[5]
and expe imen ally
[3]
is he
so-
called exponen ial model, which p o ides a easonably
simple explana ion
o
he me as abili y o any bis able.
This model es ablishes he exis ence o an exponen ial
ela ion be ween he
minimum
esidence ime in me as -
able s a e o
a
bis able
( )
and he ime in e al (AT( ))
in he exci a ion space wi hin he c i ical inpu iming
window. Algeb aically
[51:
1pd.
- /
AT( )
=
6e
e
xpn (1)
whe e
6
is he wid h o he c i ical inpu iming
win-
dow, pn he no mal p opaga ion ime ou side o he c i -
ical inpu iming window, and
‘5
is
a
pa ame e whose
alue depends on each bis able. Usually,
RS-NAND
la ches a e symme ic. Then,
a
g aphic ep esen a ion
o
I’
;:
Tse up
a) c i ical inpu imin
i%;
(1)
Figu e
2.
C iiical
inpu
iming
o
he
RS-NAND
la ch:
a) simul aneous
ansi ion
o
R
and
S;
b)
un
pulses.
he model
is
p esen ed in Figu e .La,
o
hose cases
o
iola ion o se up and hold. and in Figu e 2b, o
he
case
o me as abili y o a un pulse.
In
he
case o nea
o
simul aneous ansi ion o
he
R
and
S
signals (Figu e
2a)
we ep esen on
he
x-axis
he
ime in e al
“g”
exis ing be ween he ansi ions o
bo h
signals, and on
he
y-axis he bis able esolu ion ime
“ ”.
Fo
his ype o ma ginal igge ing, AT@)
=
2g( )
and 6=2*Tse up, since Tse up=Thold o symme ic
bis ables. Wi h his model, we ob ain om exp ession (1)
he ollowing exp ession o en e ing me as abili y due
o he iola ion o se up
o
o hold:
Tse up
8
=
pn+dog
(-)
Thus, he bis able p esen s no mal p opaga ion ime
( pn) ou side o he c i ical inpu iming egion and when
en e ing me as abili y, he no mal p opaga ion ime
inc eases by
a
quan i y ha depends on he
T
pa ame e ,
on he ime in e al
g,
and on
he
ime pa ame e Tse up.
Fo
he case o exci a ion by
a
un pulse, he c i ical
inpu
iming
window is he shown in Figu e 2b. Upon
assuming symme ic bis ables, he window is symme ic
o
>
pn.
This
is
equi alen o assuming ha all pulses
o wid h Tw il<Tw<Twmin p o oke me as abili y. The
cen e o he window coincides wi h he wid h o pulse
T=(Tw il
+
Twmin)/2. In he limi whe e Tw=Twmin,
equals pn. and we can de e mine om Figu e 2b ha
AT( pn)
=
6
=
Twmin-Tw il
and om
(1)
we deduce ha :
=
pn+,‘
ZI
)
(3)
Twmin-Tw il
)I
Tw il+ Twmin
2
slog
I
-‘Tw
-
(
Eqs. (2) and
(3)
a e he co e o he p oposed model.
461
3:
Modelling
in
VHDL
Ou app oxima ion consis s o decla ing he bis able
as
a
componen ,
o which a gumen s a e passed as a
g oup o pa ame e s, depending
on
he echnology and
ype
o
bis ables. These pa ame e s include hose ela -
ing o me as able ope a ion
(7).
When his elemen is
in oked om
a
VDHL
ile,
a
sequen ial algo i hm is exe-
cu ed, in such a way ha i gene a es he ou pu wa e-
o ms
om
changes in he inpu signals.
Wi h he s a egy p esen ed. he use mus know he
7
alue app op ia e o
he
ype
o
bis able used. This may
be incon enien since his da a does no usually appea in
he lib a y ca alogues
o
bis ables. Howe e , his pa am-
e e
can
be measu ed expe imen ally
[3]
o by elec ic
simula ion
[4].
Fi s , le us conside a simple model o his ype
o
la ch (Figu e
3).
Basically, he ile consis s o an en i y
decla a ion and
an
a chi ec u al body. in which all possi-
ble combina ions
o
he inpu and ou pu co esponding
o
each
o
hem
a e co e ed by an i -else clause.
ci y la ch s is
I
gene ic pn: ime); -- pn: no mal p opaga ion delay
po ( R,
S:
in
bi ; QQb: ou bi - ec o
(1
down o
01)
end la ch s;
a chi ec u e logical o la ch s is
begin
p ocess
a iable RS: bi - ec o
(1
down o
0);
begin
wai on R,S;
RS:=RhS;
i
RS='10'
hen
elsi RS='Ol' hen
elsi RS='OO' hen
end i ;
QQb<='10' a e pn;
QQb<=*Ol' a e pn;
QQb<=
'1 1
'
a e pn
;
end p ocess;
-2nd logical;
Figu e
3.
VHDL
desc ip ion
o
a
simple model
o
an
RS
la ch
Some ou ines o de ec iola ions o he ime pa ame-
e s (se up, hold, o pulse wid h) appea
in
[1.2].
imple-
men ed as p ocedu es ha un whene e he e is a change
in he inpu signals. These e i ica ion p ocedu es un
asse - epo s a emen s in he case o ime iola ion and
a e included in ou models. Howe e , hese concu en
ins uc ions only de ec he exis ence o me as able
beha io and do no model he beha io o he de ice
unde hese condi ions. Figu e
4
p esen s he code
ha
e lec s such beha io . The model is ob ained h ough a
p ocess which dis inguishes i e pa s: one
o
no mal
beha io , and he o he ou desc ibe he me as able
beha io o he ou causes men ioned: iola ion
o
hold, se up, S- un pulse and R- un pulse.
5ib a y
WORK;
use WORK. unc ions.al1;
en i y la ch snand
is
gene ic(
pn. se up, au,?* il.Twnin:
ime);
po (
R,
S:
in MVL; QQb: ou MVL ec o
(1
down o
0));
end la ch snandi
a chi ec u e logical o la ch snand is
ype MVL
is
('X','O','l');
ype MVL- ec o
is
a ay (NATVRAL ange
e)
o
H Lj
signal o, lagR, lagS M L:='O'i
begin
p ocess
a iable aux: ime;
a iable RS: MVL- ec o (1 down o
0);
begin
wai on R,S;
RS:=R&S; -- a iable in oduc ed o simplici y
i
RS='10' hen
i
(no S's able) hen
end i ;
o<=
'1
'
;
QQb<='10' a e pn;
i
(no R's able) hen
end
i ;
0<='0';
QQb<='Ol' a e pn;
lagR<='O'; lagS<='O';
0<='l';
QQb<='ll' a e pn;
lagS<='l';
elsi RS='Ol' hen
lagR<='l';
elsi RS='OO' hen
elsi (no R's able and S'las -e en <Tse up) he
*In his space, code o se up iola ion is included (Figu e 5)'
elsi (no S's able and R'las -e en CTse up) he
*In his space, code o hold iola ion is included;+
elsi (no S's able and lagSE'1' and lagS'las.
-e en <nJmin and o'las ~ alue='0'1 hen
+In
his space, code o S- un iola ion
is
included (Figu e
6)'
elsi (no R's able and lagR='l' and lagR'las.
-e en <Min and o'las - alue='l'l hen
+In
his space, code o R- un iola ion is included;+
else
end
i ;
lagR<='O'; lagS<='O';
end p ocess;
2nd logical;
/
Figu e
4.P oposed
VHDL
desc ip ion o he
RS-NAND
la ch.
The i s pa
o
he desc ip ion, called no mal beha -
io . coincides wi h he basic model o an RS bis able
wi hou me as abili y. The signals
"BagS",
" lagR" and
"0"
a e in oduced
as
auxilia y signals ha will be used
la e o desc ibe he me as able beha io . The signal
"0"
s o es he alue o he ou pu signal
"Q,
which. since i
is decla ed
in
ou mode canno
be
ead. The signals
lags
and llagR a e used o de e mine a which ins an he sig-
nals
S
and
R
expe ienced hei las ansi ion. These da a
will
be used o measu e he wid h o pulses
R
and
S.
The de ec ion o me as abili y is e alua ed o each o
he ou las i -else clauses. and he co esponding code
lines
un
i
condi ions a e me . Appendix
A
p esen s sim-
ula ion esul s o he implemen ed model.
Ano he modi ica ion included is he decla a ion o
MVL
(Mul i-Valued Logic) signals in addi ion o logic
le els. The de ini ion o his ype
o
signals (Figu e
4)
462
includes a hi d le el,
'X',
ha we will
use
indis inc ly o
indica e bo h inde e mina e signals and me as able
beha io . This de ini ion is necessa y
o
dis inguish no -
mal ope a ion om me as able ope a ion wi h wo pm ic-
ula in en ions:
a)Re lec he inhe en logic inde e mina ion o me as -
able beha io .
b)Model he ansmission o he me as able s a e om
one bis able o ano he
o
o any o he de ice ha is
in
con ac wi h he la ch.
3.1:
Se up iola ion
Gse S'las -e en < se up epo 'se up iola ion-
se e i y no e;
lagR<='O';
lagS<='O';
i
S'las -e en <=O.O01* se up
hen
else
end i ;
wai
un il
R='O'
o
S='O'
o
pn+ au*ln( se up,aux
i
R='O'
hen
Cx='O'
;
QQix=*Ol'
a e pn;
oc='l';
QQkx=*lO'
a e pn;
O<='O';
QQk
=
-
01
*
;
aux:=O.OOl' se up;
aux:=S'las -e en ;
QQkx='xx';
elsi
S='O'
hen
el se
.
end
i ;
package " unc ions", Figu e
7).
o
be
a ailable in a ma h-
ema ical lib a y.
d) The wai clause p esen s wo b eak condi ions,
(R='O
o
S='O').
ha indica e, i he e is a change in
he
R
o
S
signals du ing me as abili y, new inal s a es a e
eached (QQb="Ol" i
he
ese signal alls.
o
QQb="lO"
i he se signal alls). I he me as able s a e ends na u-
ally, he inal s a e eached is QQb="Ol", since he
an-
si ion p o oking me as abili y was
RS:
00
->
(01)
->
11.
This implies ha we ind ou sel es on he igh -hand side
o he window in Figu e
2a.
3.2:
Hold
iola ion
Basically, he desc ip ion equals ha o se up iola-
ion, wi h he excep ion ha he oles o
he
R
and
S
sig-
nals a e exchanged he e. I he inpu signals do no
change, once me as abili y ends he inal s a e
is
he
opposi e o ha de ined
in
he
case o se up iola ion:
QQb="lO", since he ansi ion p o oking me as abili y
was
RS:
00
->
(10)
->
11.
This is hesame
as
s a ing ha
we ind ou sel es on he le -hand side o he window in
Figu e
2a.
Thus. o symme y
he
hold ime is iden ical
o
ha o se up. o which Thold does no appea
as
a
pa ame e , and Tse up is used ins ead.
~ ~ ~~
Figu e
5.
VHDL
code
o
se up
iola ion.
Basically, wha is e alua ed o he de ec ion o
me as abili y p o oked by se up iola ion is he sepan-
ion exis ing be ween he ise o he
R
signal (a ha
ins an ) and he las ise o he
S
signal. I his sepa a ion
is less han Tse up, me as abili y is en e ed. The ollow-
ing is an explana ion o he code:
a) Line
2
ese s he alue o he signals
lagR
and Hag
S,
indica ing ha he e is no possibili y
o
un pulse.
This implies ha we conside ha he e
is
only one
simul aneous cause o me as abili y.
b) The ollowing i -else clause a oids exac simul a-
neous ansi ion be ween
R
and
S
(g=O).
In
his case.
acco ding o
(1)
he esolu ion ime would be in ini e.
and should be a oided because
i
is no ealis ic. since
p obabilis ically he e is always some cause ha makes
he bis able swi ch owa ds one s a e
o
ano he
in
a ini e
ime. The p oposed solu ion de ia es he cen e
o
he
ma ginal window
a
housand h pa o he
selup
ime.
ob aining ini e esolu ion ime. The auxilia y a iable
"aux" s o es he alue o g.
c) Ou pu s Q and Qb a e loaded
wi h
he indc ini e
alue
X
a e a ze o se ling ime when he ma ginal ig-
ge ing occu s, and emain
in
his s a e du ing he ime:
pn
+ au*ln( se uy/aux);
his is he e ec i e ime in e -
al o me as abili y acco ding o
(2).
The unc ion
In(a,b)=ln(a/b) should
be
implemen ed o his e ec (see
3.3:
S- un pulse iola ion
The de ec ion o me as abili y p o oked by un pulse
is somewha mo e complica ed. To de ec he p esence o
a pulse and measu e i s wid h, an auxilia y signal ( lags
o
lagR) is necessa y o iden i y he las signal ansi-
ion.
A
he same ime, he s a e o he bis able ou pu
mus be known, since only
a
pulse may p o oke me as -
abili y
i
he bis nblc s a e ies
o
change by pulse ac ion.
Me as abili y is only p o oked by pulses whose in e me-
dia e widlhs a e be ween TwIil and Twmin.
Figu e
6
p esen s he
VHDL
code co esponding
o
he
iola ion o S-pulse un . The ollowing is an explana ion
o he code:
a)
The i s i -else clause is in oduced o il e pulses
o wid h lowe han Tw iI. and he inal s a e eached is
exac ly he p e ious one s o ed (QQb="Ol").
b) Conce ning in e media e pulses. le us conside wo
pa s o hc algo i hm. acco ding o pulse wid h --mo e
o
less han (Tw il+Twmin)/2.
I
(Tw il+Twmin)/2
<
Tw
<Twmin. he pulse is wide enough
o
change he s a e,
e en hough
i
causes me as abili y
( i s
pa
o
he
algo-
i hm).
I
Tw iI<Tw<(Tw il+Twmin)/2,
he pulse is na -
ow enough
o
no p o oke
a
change in s a e, e en hough
i
causes me as abili y (second
pa
o he algo i hm).
These wo cases a e included
in
he main i -else clause.
c) Since we ha e conside ed he poin in ime o in i-
ni e esolu ion. once again due
o
symme y, a he poin
463
&sea (no S's able
and
lagS='l' and lagS'las -e en
awnin
and
o'las - alue='O') epo 'S- un iola ion' se
e i y no e;
i
lagS'las -. en <~ il hen
elsi
lagS'las _~~ z=0.5*('Il il+l nnin)
hen
aw~-O.OOO~*(~ il+~in);
aw:= lagS'las -a an -0.5*(Tw il+~in);
QQk-
'01.
lagRc-'O'
;
lag%='O'
;
i
lagS'l~s ~e en ~-0.5005*('I* il+~in~
hen
e1 se
md
i ;
QQa.-xx.
wai un il
R='O'
o
S='O'
o pn+ au+ln(O,5*(l"in
i
R='O'
hen
elsi
S='O'
hen
el ae
end
i ;
i
lagS'las -e en >=0.4995*(Tw il+l nninl
hen
el se
end i ;
QQb<=.XX.;
wai un il
R-'0'
o
S='O'
o pn+ au*ln(O.S* I"in
i
R='O'
hen
elsi
S='O'
hen
el se
end
i ;
Tu il)
,aw);
oc='O';
QQk~s.01'
a e pn;
oc='l';
QQk='lO'
a e pn;
c~='l';
QQb<='lO';
else
aw:=O.O005*('I* il+nmin);
aux:=0.5+('I* il+~in)- lagS'las ~e en ;
n il) ,am)
;
o<='O';
QQk='Ol*
a e pn;
o<='l';
QQbc='lO'
a e pn;
o<='O';
QQb<='Ol';
end
i :
<lagR<='O'; lagS<='O';
/
Figu e
6.
VHDL
code
o
S- un
iola ion.
(Twlil+Twmin)/Z, pulses
o
his exac wid h a e "de i-
a ed" in a housand h o his alue.
so
ha he esolu ion
ime is ini e. The auxilia y a iable "aux" s o es he
alue o he ime in e al, acco ding o
(3).
d) Ou pu s Q and Qb a e loaded wi h he inde ini e
alue
X
a e a ze o se ling ime when he ma ginal ig-
ge ing occu s, and emain in his s a e du ing he ime:
pn
+ au*ln( se uplaux);
his is he e ec i e ime inle -
al o me as abili y acco ding o
(3).
e) The wai clause p esen s wo b eak condi ions,
(R='O'
o
S='O)
indica ing, i he e is a change
in
he
R
o
S
signals du ing me as abili y. new inal s a es a c
eached (QQb="Ol" i he ese signal alls.
o
QQb="lO"
i he se signal alls).
I
he me as able s a e ends na u-
ally,
he
inal s a e eached is QQb="lO".
i
pulse widlh
is
Tw ikTw<(Tw il+Twmin)/2.
This implies ha we
ind
ou sel es on he igh -hand side o he window
in
Figu e
2b. O he wise, i pulse
wid h
is (Tw il+Twmin)/2
c
Tw
<Twmin, he s a e emains (QQb="Ol") i.e. we ind ou -
sel es on he le -hand side o he window
in
Figu e 2b.
3.4:
R- un
pulse iola ion
The case o R- un pulse iola ion is e y simila o
ha de eloped o he S- un pulse iola ion.
Only
he
inal s a e and he me as abili y de ec ion condi ions
change.
Also,
he
R
and
S
signals
a e
in e changed. The
pa ame e s (Twmin and Tw il)
a e
lhe same since he
bis able
is
conside ed symme ic.
The
inal
s a e
eached
is QQb="Ol". i he pulse wid h
is
(Ti il+li min)/
2eTweTwmin. I
he
pulse wid h
is
Ti ila<(Tw-
il+Twmin)/2.
he
inal s a e is
QQb="lO",
ha
is,
he
s a e
does
no change.
I
he
pulse wid h
is
li ibTw, he
pulse
is
il e ed and
he
inal s a e
is
QQb"l0".
3.5:
Package
dckage body unc ions is
unc ion ln(T,J:
TIE)
e um
REAL
is
a iable P:INTECER:=l;
as iable esul
:REAL:
=O
.O
;
a iable 1,Q:
REAL:=l.O;
begin Q:=l.O- eal (J/ns) / eal(T/ns);
1
WP
i
(l.O/I)*(Q**P)
<
O.Ol* esul hen
end i ;
esul
:=
Il.O/I)*(Q**P)
+
esul ;
I:=I+l.O; P:=P+l;
exi ;
end loop;
e u n esul ;
end In;
.end unc ions;
1
Figu e
7.
Package " unc ions".
The package " unc ions" (Figu e
7)
con ains an algo-
i hm capable o calcula ing he na u al loga i hm
o
he
quo ien
o
wo numbe s, wi h less han 1% e o . The
unc ion In(a.b) has wo TIME pa ame e s as a gumen s
and e u ns
a
REAL alue (log(a/b)). Implemen a ion o
his algo i hm is based on an i e a i e cycle which com-
pu es in each cycle one e m o he se ies:
1
2
3
logs=
(y)+T
x-1
1
(?)
x-1
+T
1
(7)
x-1
+
.......
x
2
The equi emen o xW2 is no
a
limi a ion, since we
e alua e he loga i hm o a gumen s la ge han 1.
4:
Applica ions
Two
applica ions ha e been ca ied ou
o
check
he
e ec i eness o he implemen ed model. The i s is he
implcmen a ion o
a
D-la ch con aining an RS-NAND
la ch as he memo y elemen . The second ies o demon-
s a e ha a bis able in me as abili y can
be
he
cause o
emo when i s me as able s a e is ead by wo o he
bis ables and each eads
a
di e en alue.
4.1:
Model
o
a D- ype la ch
We a e going o cons uc
a
D- ype la ch model using
he model o he RS-NAND la ch p esen ed p e iously.
The objec i e is o check i he desc ip i e model o he
me as abili y is alid when we include
he
RS la ch in
ano he ci cui .
Fo
his we will use he s uc u e o he
464
RS-NAND
Lo
zb
,+
1D D
Figu e
8.
D-La ch composed o an RS-La ch.
D-la ch shown in Figu e
8.
The code implemen ed o
desc ibe he D la ch is shown in Figu e
9.
The ope a ion
mode is simple: inpu da a (D) passes
o
ou pu
(Q)
when
condi ion LOAD=l is ue and he e is a a ia ion o any
signal p esen in he wai clause (LOAD. D. Db).
C i y la chd is
end la chd;
a chi ec u e logical o la chd is
componen la ch snand
po (D.LOAD: in MVL; QQb: ou MVL- ec o
(1
down o
0))
;
gene ic( pn, se up, au,Tw il,Twmin:
ime);
po (R,S:in MVL;QQb:ou MVL- ec o
(1
down o
011;
end componen ;
signal Db,R,S:)NL:=’O‘;
o
all: la ch snand use en i y WORK.la ch snand(logi-
cal)
;
begin
C1:la ch snand gene ic map
(4
ns,
4
ns,
1.8
ns,
1
ns,
4
ns) po map (R.S,QQb);
p ocess
begin wai
on
D,Db.LOAD;
Db<=no D a e
1
ns;
R<=LOAD nand Db a e
1
ns;
&=LOAD nand
D
a e
1
ns:
end
p ocess;
end logical;
Figu e
9.
Model o a D-La ch using he p oposed RS-la ch.
Since he inpu in e e makes
R
and
S
appea pe ma-
nen ly complemen ed, he D la ch may only en e me as -
abili y p o oked by a un pulse
in
he RS la ch.
Simula ion esul s a e included
in
Appendix
A
showing
how D-la ch en e s
in
me as abili y and a he same ime.
how he beha io is close
o
ha expec ed.
4.2:
E o
caused
by
me as abili y
A
case p esen ing he me as abili y as a cause o p op-
aga ing e o s is he ci cui o Figu e 10. This shows how
he ou pu
o
an
RS la ch (Ll) d i e he wo synch onous
RS
la ches
(L2
and L3). The p esence o a small skew
be ween he wo load signals
o
he la ches. oge he
wi h
he en y in o me as abili y o la ch Ll may cause la ch
L2 and L3 o cap u e di e en logic alues. This is a
classic example o he undesi ed e ec s o me as abili y.
I.3
5:
Conclusions
A
comple e VHDL model o bis ables has been p e-
sen ed. This model includes no mal beha io and he
so-
called exponen ial model
o
i s mes as able beha io .
I s
applica ion o he analysis
o
ci cui s wi h iming p ob-
lems allows no only o de ec he p oblem i sel (me as -
abili y) bu also o know i s e olu ion depending on he
ime es ic ion iola ions. Thus. he u ili y
o
he p o-
posed model is i s abili y o pe o m ealis ic simula ion
o sys ems. To de elop he model, we ha e aced some
p oblems ela ed o he ea men o TIME, bu ha e been
esol ed ia speci ic solu ions. The co e
o
he imple-
men a ion
is
he model
o
he basic memo y elemen
(RS-NAND la ch). Thus, he modelling o mo e complex
bis ables
is
qui e s aigh o wa d, p esen ing a D-la ch as
an example. In a simila way. we ha e used he p oposed
model o show how a ci cui
wi h
h ee la ches can
be
a
sou ce o a al e o s caused by me as abili y ansmis-
sion
in
one o
i s
la ches.
6:
Re e ences
[
11
Lipse . R.. Schae e . C. and Usse y. C.:
“VHDL:
Ha dwa e
[9]
Be ge. J.M.. Fonkoua, A., Magino .
S.
and Rouilla d, J.:
VHDL Designe s Re e ence”. Kluwe
Acad.
Pubs. 1992.
[
31 Roseinbe g.
F.
and Chaney, T.J.: “Flip-Flop Resol ing
Time Tes Ci cui ”.
IEEE
Joumal
o
Solid-s a e Ci cui s,
[4]
Bellido, e . al.: “A New Fas e Me hod o Calcula ing he
Resolu ion Coe icien o CMOS La ches: Design o an
Op imun La ch”, P oc. o 26 h
ISCAS.pp.2019-2022.1993.
[5]
Mo in. L. and Li.
H.F.:
“Design o Synch onise s: a
Re iew”.
IEE
P oceedings-E, Vol. 136. No.6. pp.
557-564.
No .
1989.
Desc ip ion and Design”, Kluwe Acad. Pubs. 1990.
Vol. SC-17.
NO.
4.
pp. 731-738. Augus 1982.
APPENDIX
A
Simula ion esul s. Pa ame e s o RS-la ch a e:
pn=4ns. se up=4ns. au=
1
Ons.Tw il=l ns.Twmin4ns
nu
I
I
I
4
n
$2
1
RS-NAND la ch unde se up iola ion.
g
=
1 ns,
=
17
ns.
I
J
I
I
I
1
‘7
I
c
TIME
I
D-la ch (R-Run pulse iola ion).
=
7
ns.
Figu e 10. E o induced
in
L2
y
L3 by me as abili y in L1.
465