RAPID
-
Re a ge abili y
o
Reusabili y
o
Appka ian-D i en
Quad a u e
R A
In e ace
Black
Design
J.
F anea'
N.
Ho a'
NI.
Pe ei a'
J.
Vi al'
R.
Cas o-Upez'
M.
Rdgado-Res i u d
F,
Fe nandez'
A.
Rod guez-V&zquez*
J.
Ra nos"
P.
San os3
'Ins i u o Supe io T6cnico
AV. Ro isco Pais,
1,
'Ins i u o de Mic oelec 6nica de Se illa 3ChipIdea Mic oelec onics, L d.
IST Cen e o Mic osys ems Cen o Nacional de Mic oelec hica TAGUSPARK
AV. Reina Me cedes s/n, 41012 Edi icio Ino aGZo
IV
-
Sala 722
1096 Lisboa Codex, Po ugal Se ille, Spain 2780-920 Po o Sal o, Po ugal
Email: anca
@
gcsi.is .u 1 .p Email: [email p o ec ed] Email: j amos @chipidea.com
Abs ac
This pape desc ibes ESPRIT
29648,
conce ning he
de elopmen
o
an ad anced me hodology o he
design o a mixed-signal applica ion-d i en quad a u e
D/A in e ace sub-sys em, aiming a i s eusabili y by a
e a ge ing p ocedu e wi h minimal changes o hei
s uc u al sub-blocks. The me hodology will be
demons a ed, i s , by de eloping a nominal design
pla o m o he implemen a ion in
0.35
pm double-
poly CMOS echnology o a Quad a u e D/A In e ace
Block Design o he GSM s anda d, and, hen, by an
au oma ic e a ge ing in an e olu iona y echnology
h ough he ealiza ion o a silicon p o o ype in
0.25
pm
CMOS.
1.
In oduc ion
Wo ld-wide semiconduc o ma ke ends indica e a
apid inc ease
o
chips con aining bo h analog and
digi al unc ionali y, ob ained a he expense o chips
which con ain pu ely analog unc ionali y and also o
chips which con ain pu ely digi al unc ionali y
[
1-31.
I is gene ally accep ed ha such inc eased
unc ionali y
is
playing a bigge oll in he way
in eg a ed ci cui s a e designed, and he eby making
designe s mo e conce ned wi h in eg a ed sys em
solu ions combining analog and digi al unc ions and
signals. In o de o p o ide such inc eased unc ionali y
and combined use o analog and digi al signals, i is
necessa y o de elop he elec onic ci cui y ha
p o ides he app op ia e analog-digi al in e ace. Thus,
in a no oo dis an u u e, he in eg a ion o comple e
sys ems on a chip will be achie ed by assembling a
a ie y o high unc ionali y blocks, om powe ul
CPU and DSP co es o complex analog-digi al blocks,
as depic ed in ig.
1.
In o de o sa is y he need o educe p oduc
de elopmen cycles and imp o e imely a ailabili y o
he ma ke in a wo ld subjec o
a
as pace o
echnology e olu ion owa ds sys em le el in eg a ion
i
is ine i ably equi ed ha a signi ican inc ease o
p oduc i i y is achie ed in he design
o
complex
mixed-signal in e ace unc ions. This can be p o ided
by e a ge able analog-digi al blocks ha allow easy
e-usabili y o di e en echnology en i onmen s and
applica ion equi emen s. This pape desc ibes he
me hodology o designing such e a ge able
applica ion-d i en analog-digi al blocks, discusses i s
main ing edien s and equi emen s o he suppo ing
compu e -based ools, and illus a es i s applica ion in
p ac ical indus y designs.
i
Fig.
I:
Sys em-le el in eg a ion in mixed-signal
VLSI
chips
will be achie ed using high- unc ionali y analog-digi al
blocks
oge he wi h high-densi y digi al co es.
2.
Analog-Digi al In e ace equi emen s
Analog-digi al blocks ound in complex mixed-signal
VLSI a e needed o in e ace he digi al p ocessing
engines a hei hea o he physical sou ces o analog
signals
[4-61.
This can be he case
o
inpu
and
ou pu
in audio applica ions, senso s and ac ua o s in mic o
sys ems, eading/w i ing channels o s o age
applica ions
-
disk o ape, and e en comple e
anscei e in e aces o adio ansmission. In his
p ojec a quad a u e D/A in e ace was adop ed, in
o de o illus a e he e a ge able me hodology.
In igu e
2,
a mixed-signal in e ace block, p o iding a
wo ully-di e en ial channels in quad a u e phase (90'
phase shi ) be ween he inpu digi al po s and he
ou pu analog po s
[7],
is illus a ed. Each channel is
o med by a digi al p ocessing uni o signal shaping
0-7803-5682-9/99/$10.000
1
999
I
E
E
E.
I679
and in e pola ion, a digi al- o-analog con e sion
unc ion employing cu en -based ci cui echniques
and hen a con inuous- ime il e , which also p o ides
he embedded cu en o ol age con e sion. An
addi ional calib a ion uni is employed o adjus he
una oidable o se s and misma ches be ween he bo h
channels. In o de o con ol he unc ionali y and
calib a ion o he comple e block, a con ol uni is
also
included. Again in his example we can no ice he ue
mul i- unc ional na u e o
a
block design comp ising
digi al signal p ocessing, digi al- o-analog con e sion,
analog con inuous- ime il e ing and e en unc ions o
e o co ec ion and calib a ion.
.-
.,c, il
.','a
am"-
."my
-I"=
-,ll
-"*
dLI"*
0,
ElLh
." nl"
snmin s
.**dl",Z
.I
-01
*Ah
i
Fig.
2:
Block diag am o a mixed-signal block p o iding ull
in e acing unc ionali y be ween a quad a u e digi al po
and a quad a u e analog po .
The abo e example ou lines ha mixed-signal in e ace
blocks a e e y demanding in e ms o he knowledge
ha is needed o hei de elopmen . Fi s ly, i is
impo an o ha e knowledge abou he sys em
applica ion and ele an signals, wi hou which i will
no be possible o de ine he block unc ionali y and
e en i s elec ical equi emen s. Once he sys em is
known, i is also impo an o ha e a knowledge abou
he ci cui s o signa1 p ocessing and con e sion ha
can be used inside hose blocks. These can include
con inuous- ime and sampled-da a il e s
-
bo h analog
and digi al, signal condi ioning ci cui s, again bo h
analog and digi al, and
also
analog- o-digi al and
digi al- o-analog con e sion unc ions. Thi dly, i is
also impo an o ha e he knowledge ha allows he
de elopmen o he ci cui componen s o in eg a ed
ci cui ealiza ion, such as ope a ional ampli ie s,
compa a o s, ol age e e ences and cu en e e ences.
Finally, i is impo an o know how o p o ide he
physical implemen a ion o all hose componen s in a
ully e i ied da abase ha
is
submi ed o ab ica ion.
3
Re a ge able
Block
Design
Re a ge able block model
The undamen al concep o he design
o
e a ge able
blocks is illus a ed in igu e
3.
A e ca ying-ou
a
adi ional op-down design, co esponding o he le
hand side o he illus a ion, he esul s will be in he
o m o sepa a e schema ics and layou cells o he
ci cui componen s and unc ional building blocks.
In
addi ion o his basic ci cui in o ma ion, he e may
also be expe imen al esul s o p o o ype chip
cha ac e iza ion
o
alida e he design solu ions and
possibly es ablishing hei p ac ical limi s o
e ec i eness. We may now conside ha all such
in o ma ion a schema ic, layou and silicon le els can
be embedded in o
a
single block model. A ound each
block model we can de ine
a
ange o speci ica ions
which allow he as e a ge abili y o he model.
The e o e, whene e
a
new se o speci ica ions is
de ined wi hin such ange, he block model p o ides an
impo an cen al pla o m om whe e he new block
design can be quickly accomplished. In
a
CAD
en i onmen o e a ge able block design, adi ional
lib a ies a e now eplaced by "knowledge" lib a ies
con aining objec s ha always need some e uning
design in o de o mee new speci ica ions.
W
Fig.
3:
The concep
o
block model embeds in o ma ion
om elec ic sclzema ics, physical layou s and e en
expe imen al cha ac e iza ion
o
a design.
Design
low
o e a ge abili y
The design
low
o ca you he e a ge ing
o
a
block
is
illus a ed in igu e
4.
Fi s , i conside s he alida ion
o a new se o speci ica ions agains he ange o
speci ica ions o which he block has been p e iously
designed. The design is ca ied-ou only i he
speci ica ions a e alida ed, meaning ha he new se
o speci ica ions alls wi hin he ange o he
e a ge abili y
o
he block. In his case, a se o
p io i ies a e ini ially de ined in o de o de ine he
sequence o speci ica ions ha should be accomplished
i s by he cons i u ing unc ional building blocks
acco ding o hei inhe en adap abili y and sui abili y
o in eg a ed ci cui ealiza ion. Once such sequence
is
de ined, he design p ocess consis s
o
uning he
exis ing designs o he new speci ica ions. Then, a e
uning he unc ional building blocks, he e is
a
p ocess
o uning he ci cui componen cells wi hin each
unc ional block and which consis s also o changing
only he pa s o he ci cui componen s ha need
o
be
changed. Suppose, o example, he e a ge ing o
a
block which is needed o inc ease he d i ing capabili y
I
680
o an ope a ional ampli ie . I
is
clea ha i would no
be necessa y o e-design he whole ope a ional
ampli ie again, bu simply o ca you a much smalle
in e en ion in he ou pu s age, may be by adjus ing i s
biasing le el o e-sizing
he
dimensions o i s
cons i u ing ansis o s. A e he uning o all he
unc ional building blocks and ci cui componen s has
been comple ed,
a
alida ion s ep akes place o e i y
he co ec ness o he new pe o mance cha ac e is ics
and hen p oceed o he inal p ocessing and
e i ica ions.
Block Design Analysis
Specs
A,
1.2~
New
......
~
.................
I
Speci;ii ionj--
Tech File Schema ics Design
Time
New New
I
lmon hs
Fig.
4:
Re a ge able block design
low.
Key ea u es
o
designing o e a ge abili y
The equi ed ea u es o design quali y and
p oduc i i y in he abo e en i onmen a e mul iple.
Fi s ,
i
is necessa y o ensu e ha he ading-o o
speci ica ions
o
he mul iple unc ional blocks inside
he block con e ges and ha in such
a
p ocess he
sys em pa i ioning is op imized
o
implemen a ion.
Second,
i
is necessa y o ensu e ha he block model is
easily adap ed o
a
echnology e olu ion by using
ci cui componen design me hodologies which educe
he echnology dependency. Thi d,
i
is equi ed o
ensu e ha he e a ge ed design achie es an e ec i e
use o silicon a ea because,
in
olume p oduc ion, he
a ea o he chip is pa amoun o de e mining he inal
p oduc ion cos . This can be assu ed by maximizing he
layou egula i y, op imizing he componen aspec
a ios o e en by es ablishing ca e ul loo planning o
he block. Finally, he ou ing densi y and ou ing a ea
o he block should
also
be minimized
as
his
ep esen s an o e head a ea which is no di ec ly
needed o he unc ionali y ha needs o be deli e ed
and, he e o e, he highe he o e all ou ing a ea, he
highe he p oduc ion cos o he ci cui . This can be
assu ed by a de ailed analysis o he ou e-pa h
cha ac e is ics and he use o simpli ying ou ing
echniques.
Design
p oduc i i y
The p oduc i i y gains ha can be achie ed by using a
me hodology based
on
e a ge able block designs is
illus a ed in Table
1,
bo h o di e en echnologies
and o di e en specs.
I
Specs
B,
1.2
I
---
I
---
I
Modi ied
I
3
weeks
1
1
SpecsA,O.7pml
---
I
New
I
Modi ied
I
4
weeks
1
1Specs
C,
0.5~
I
---
1
New
I
Modi ied
I
2
weeks
I
4
Design Au oma ion owa ds Re a ge abili y
The me hodology desc ibed abo e ep esen s he design
low ollowed by expe imen ed designe s in an
indus ial en i onmen . Besides he de ini ion o such
me hodology he
goal
o RAPID (EP-29648) is o
de eloped
a
design au oma ion mechanism, embedded
on
a ailable comme cial ools, o pe o m he
e a ge ing o mixed-signal ICs be ween di e en
echnologies
in
an indus ial design en i onmen . The
a
design au oma ion mechanism
is
being build abo e
Cadence
DF
11,
making use o design acili ies such as
P-Cells s uc u es,
SKILL
language and also some
ex e nal ools, e.g., op imiza ion mechanism. Nex , he
in o ma ion low, illus a ed on igu e
5,
on such
a
design au oma ion mechanism is desc ibed, ou lining,
he knowledge/da a acquisi ion, he e a ge ing
mechanism and he ou pu da a.
1-p
sy*m
,:,2;
..........
Fig.
5:
Design Au oma ion Mechanism (In o ma ion
Flow)
1681
Knowledge Acquisi ion
The i s s ep
on
such a design p ocess co esponds o
he knowledge acquisi ion o suppo he e a ge ing
mechanism, his consis o he o iginal IC design
desc ip ion made o a speci ic echnology, e.g.,
AMs
0.35pm. This desc ip ion should be made ully
hie a chically, including high-le el models o he
comple e sys em, made in SPECTRE HDL, Low-le el
models, made in SPECTRE, sys em design ules and
cons ain s, ha dcoded, and he comple e layou
desc ibed in e ms o P-Cells s uc u es. F om his
ini ial design and echnology desc ip ions new IC
should be au oma ically de i ed.
Inpu Specs
Fo such a p ocess ocusing on he e a ge ing o
di e en echnologies, ha ing e y same high-le el
pe o mance specs, e.g.,
GSM
s anda d, he equi ed
inpu a e mainly he new echnology iles, e.g., AMS
0.25pm.
Re a ge ing Mechanism
Based
on
he o iginal Layou and
on
he new
echnological iles a ci cui ex ac ion is pe o med,
so
ha all sub-blocks pe o mance can be e alua ed a
elec ical le el and he ull sys em can be e alua ed by
beha io al simula ion using, e.g., SPECTRE, HSPICE
and SPECTRE-HDL. Nex , based
on
he pe o mance
e alua ion esul s,
on
he desi ed sys em pe o mance
and
on
he sub-block design cons ain s, he P-Cells
specs and co ec ions equi ed,
on
he new echnology,
o each sub-block a e de ined, wi hin accep able
limi s. Then, based
on
he sys em layou empla e
execu e sub-block e a ge ing ope a ions by ei he
changing componen sizes using SKILL, as illus a ed
in ig.
6,
o pola iza ion sou ces. Finally, eadjus all
sys em layou acco ding o sub-blocks geome y
changes.
-.
bnen Sou ce
Heigh 3ewion
---..
----
--.
ma ic Layou
Re a ge ing%es $ions.
---.
--
-..
4.
-4.
Fig.
6:
Cu en Sou ce Re a ge ing Ope a ion.
Ou pu Da a
The ou pu da a
on
such a p ocess includes he mixed-
signal IC layou on he new echnology,
as
well
as,
he
sys em cha ac e iza ion based on mul i-le el simula ion
as speci ied by he e a ge ing mechanism abo e.
5
Example om Indus y P ac ice
Quad a u e D/A
RF
in e ace
The mixed-signal block discussed ea lie in his pape ,
illus a ed
in
ig. 2, and which is equi ed o p o ide
he in e ace be ween wo digi al signals in quad a u e,
one in-phase and he o he
90"
ou -o -phase, and he
analog signals ha in e ace an RF ansmi e o
wi eless applica ions, was selec ed as an example o
indus y p ac ice.
The abo e block has been e a ge ed o di e en
applica ions, all o wi eless communica ions, and
which ha e di e en equi emen s o he digi al inpu
da a, baseband equency band, sampling equency
and e en ou -o -band image ejec ion. Two examples o
he esul ing layou s o such block wi h e a ge ed
cha ac e is ics a e illus a ed
in
Figu e
7.
Fi s , in
Figu e
7
(a), we can see he
I&Q
D/A in e ace o he
Japanese
PHS
sys em, wi h
25
kHz baseband, and
which equi ed an 8- old in e pola ion o he inpu
digi al signal, an 8-bi s D/A con e e and a 2nd o de
ac i e-RC il e wi h nominal
400
kHz cu -o
equency. In Figu e
7
(b)
we can see he layou o he
same I&Q D/A in e ace a chi ec u e e a ge ed o
a
GSM
applica ion, wi h 100 kHz baseband, and which
employs a 10- old digi al in e pola ion, a 10-bi s D/A
con e e and a 2nd o de ac i e-RC il e wi h
nominal
800
kHz cu -o equency. A ca e ul
inspec ion o he layou s o bo h blocks shows he
di e ences in each one o he cons i u ing block a eas.
Fo example, he ou pu ac i e RC il e s which
co espond o he la ge a eas
on
he igh -hand side o
he layou ; we can also see di e en a eas o he
s ee ing cu en D/A con e sion in he middle o he
blocks and he di e en a eas o he digi al p ocessing
uni jus be o e he D/A con e sion unc ions. In he
i s case, we clea ly see ha signal p ocessing
unc ion. In he second case, his is no included in co e
as he cus ome has decided o implemen ha unc ion
oge he wi h o he digi al signal p ocessing unc ions.
This example illus a es he use o applica ion-d i en
e a ge able analog-digi al blocks o achie e inc eased
design p oduc i i y.
1682
[7]
J.
Goes
e
al.
“Low-Powe O se -Calib a ed CMOS
VQ
T ansmi
In e ace o Po able Communica ions”, Eu opean Solid-s a e
Ci cui s Con e ence, Sou hamp on,
UK,
16-1
8
Sep embe 1997.
“’““I----.
,
......................
!!!::::::::::::::::::::::.::!::::::::::
(a)
(b>
Fig. 7: Re a ge able block layou s.
6 Conclusions
The ma e ial p esen ed and discussed in his pape
makes
i
clea ha mixed-signal in eg a ed ci cui s will
play an inc easingly impo an ole in semiconduc o
ma ke s and ha he a e o echnology and applica ion
de elopmen s will inc ease he p essu e o cope wi h
a g ea e p oduc i i y equi emen s o designing.
Fi s ly, because o hei in insic mul i-disciplina y
na u e and secondly because o he lack o adequa e
ools ha c oss all he hie a chical le els o design,
om a chi ec u al design o layou gene a ion. The
concep o e a ge able, applica ion-d i en analog-
digi al blocks will p o ide he solu ion o hose
equi emen s in e ms o design p oduc i i y and cos
e ec i eness. In o de o achie e his, new
me hodologies and suppo ing ools encapsula ing
hie a chical mul i-le el design in o ma ion mus be
de eloped alongside comp ehensi e beha io al models
embedding bo h unc ional and elec ical pe o mance
in o ma ion. I is clea ha he de elopmen o such
me hodology is s ill in i s in ancy and he e o e
signi ican e o s ha e o be deployed wo ld-wide
so
ha he ools ha
a e
needed o p o ide he equi ed
design suppo become widely a ailable.
Acknowledgemen s
The wo k epo ed on his pape has been suppo ed by
he Eu opean Communi y unde RTD p ojec
29648
(RAPID).
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“Top-down design
o
high-pe , ma e
sigma-del a modula o s‘
”,
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Pub.,
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Beenke ,
e al., “Analog CAD o consume IC’s’’, in
Analog
Ci cui Design,
Huijsing, an de Plassche, and Sansen
Eds.,
Bos on, MA: Kluwe Academic, 1993, ch. 15.
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F anca,
Y.
Tsi idis,
“Design
o
VLSI
Ci cui s o
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and
Signal P ocessing
‘I,
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Johan
J.
J.
Haspeslagh e al. “A 270-kbk 35-mW Modula o IC
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Jou nal
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ol.
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al.
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o
GSM Mobile
Communica ions”, in Analog In eg a ed Ci cui s and Signal
P ocessing
2,
pp. 197-206, Kluwe Academic Pub., 1992.
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“A
3
V
GSM Codec”, in IEEE Jou nal o Solid-
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12, pp. 1411-1420, Dec. 1995.
1683