IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004 47
Highly Linea 2.5-V CMOS
61
Modula o o ADSL
+
Rocío del Río, José M. de la Rosa, Belén Pé ez-Ve dú, Manuel Delgado-Res i u o, Ra ael Domínguez-Cas o,
Fe nando Medei o, and Angel Rod íguez-Vázquez, Fellow, IEEE
Abs ac —We p esen a 90-dB spu ious- ee dynamic ange
sigma–del a modula o
(61
M) o asymme ic digi al subsc ibe
line applica ions (bo h ADSL and ADSL
+
), wi h up o a 4.4-MS/s
digi al ou pu a e. I uses a cascade (MASH) mul ibi a chi ec u e
and has been implemen ed in a 2.5-V supply, 0.25- m CMOS
p ocess wi h me al–insula o –me al capaci o s. The p o o ypes
ea u e 78-dB dynamic ange (DR) in he 30-kHz o 2.2-MHz
band
(
ADSL
+)
and 85-dB DR in he 30-kHz o 1.1-MHz band
(ADSL). In eg al and di e en ial nonlinea i y a e wi hin 0.85
and 0.80 LSB
14
b, espec i ely. The
61
modula o and i s
auxilia y blocks (clock phase and e e ence ol age gene a o s,
and I/O bu e s) dissipa e 65.8 mW. Only 55 mW a e dissipa ed in
he
61
modula o .
Index Te ms—Analog- o-digi al con e e (ADC), asymme ic
digi al subsc ibe line (ADSL), MASH, sigma–del a modula ion,
swi ched-capaci o ci cui s.
I. INTRODUCTION
SUPPORTED by a conside able comme cial success, wi e-
line solu ions o b oad-band access and home ne wo king
a e e ol ing o p o ide e e inc easing da a a es and mo e unc-
ionali y. An asymme ic digi al subsc ibe line (ADSL) is an
example o such applica ions and ex ensions o i like ADSL
(wi h doubled numbe o channels) o e y-high-da a- a e dig-
i al subsc ibe line (VDSL), p o iding ideo- a e ecep ion) a e
jus ound he co ne . As his end goes on, he demand o
highly linea , as analog on -ends challenges mixed-signal de-
signe s o achie e accu acies o 12–15 b o signal bandwid hs
anging om 1.1 o 12 MHz [1].
Al hough hese speci ica ions seem a p io i be e sui ed
o Nyquis a chi ec u es, such as pipeline analog- o-digi al
con e e s (ADCs) [2], hese a chi ec u es do no exhibi
enough linea i y o some elecom applica ions, especially in
low- ol age implemen a ions, unless he powe consump ion
is signi ican ly inc eased. Fo his eason, o e sampled ADCs
ha e gained g ound in his equency ange. Speci ically,
sigma–del a modula o s Ms [3], [4] exhibi high in insic
linea i y, making use o ela i ely simple analog ci cui y,
which ende hem wo h explo ing o b oad-band wi eline
and baseband adio- equency communica ions [5]–[22].
Manusc ip ecei ed Janua y 14, 2003; e ised Augus 31, 2003. This wo k
was suppo ed by he Eu opean Union unde IST P ojec 29261/MIXMODEST
and IST P ojec 2001-34283/TAMES-2 and he Spanish MCyT and he ERDF
unde P ojec TIC2001-0929/ADAVERE. This pape was ecommended by
Gues Edi o O. Feely.
The au ho s a e wi h he Ins i u e o Mic oelec onics o Se ille (IMSE-CNM,
CSIC), 41012 Se ille, Spain (e-mail: [email p o ec ed]).
Digi al Objec Iden i ie 10.1109/TCSI.2003.821308
Gi en he high signal bandwid hs equi ed in wi eline com-
munica ion, only low-o e sampling a io Ms a e ea-
sible. In o de o keep he esolu ion le els wi h hese low alues
o , he well-known o mulas o he dynamic ange DR and
he e ec i e numbe o bi s ENOB [3]
DR
ENOB DR (1)
dic a e ha ei he high-o de loop il e ing (inc easing he
o de ) o mul ibi quan iza ion (inc easing he es-
olu ion o he quan ize ), o bo h mus be used. Howe e ,
hese s a egies aise issues ha jeopa dize obus ness o highly
o e sampled, low-o de single-bi Ms. On he one hand,
high-o de loops a e p one o ins abili y and he s abiliza-
ion me hods p oposed ha e esul ed in complex a chi ec u es
whose DR is deg aded wi h espec o ha in (1) [3].This deg a-
da ion is mo e no o ious o single-bi quan ize s, so ha he
combina ion o high-o de loops wi h single-bi quan iza ion
is no a good choice o high- equency designs [3]. On he
o he hand, mul ibi con e sion en ails ex eme sensi i i y o
he nonlinea i y o he digi al- o-analog con e e (DAC) in
he eedback pa h and o ces he use o co ec ion/calib a ion
echniques [23]–[25]. Un o una ely, since DACs canno be
e icien ly linea ized wi hin an a bi a ily la ge esolu ion, he
use o low-o de mul ibi modula ion may no be enough o
ob ain a gi en DR.
A di ec solu ion o his p oblem is o inc ease bo h he mod-
ula o o de and he in e nal quan ize esolu ion, gi ing ise o
mode a e-o de (3–5), mul ibi a chi ec u es. In ac , he use o
mul ibi quan iza ion ( ypically up o 4 b) in single-loop high-
o de Ms inhe en ly imp o es hei s abili y [3], so ha hese
a e good candida es o ob ain high- esolu ion, high- equency
ope a ion, p o ided ha he nonlinea i y p oblem is sol ed [8],
[9], [13], [21]. Wi h he same objec i e, he combina ion o high-
o de cascade (MASH) a chi ec u es [26] wi h mul ibi quan i-
za ion has been p oposed [18], [27]. These modula o s ga he
he uncondi ional s abili y o cascade modula o s (only second-
and/o i s -o de s ages a e used) and he ad an ages o mul ibi
quan iza ion wi h elaxed equi emen s o he linea i y o he
DAC. The easibili y and e iciency o his app oach, because i
needs no co ec ion/calib a ion mechanisms, has al eady been
p o en [10]–[12], [17]–[20].
In his pape , we p esen he design o a M o ADSL
applica ions in a 2.5-V, 0.25- m CMOS p ocess. Wi h his
1057-7122/04$20.00 © 2004 IEEE
48 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
Fig. 1.
L
h-o de
61
modula o using a
2
0
1
cascade.
goal, a amily o M a chi ec u es capable o achie ing
high esolu ion wi h a low o e sampling a io a e de ised in
Sec ion II. Sec ion III s udies he impac o deep-submic om-
e e ea u es on he a chi ec u e selec ion, p o iding op imized
a chi ec u e pa ame e s o he speci ica ions conside ed.
Ci cui implemen a ion and ela ed design conside a ions a e
explained in Sec ions IV–VI. Finally, Sec ion VII shows ex-
pe imen al esul s o he M and compa es i s pe o mance
wi h s a e-o - he-a designs.
II. LOW-OVERSAMPLING CASCADE MODULATORS
Fig. 1 shows he gene ic block diag am o a amily o
high-o de cascades. I is an h-o de modula o o med by
a second-o de s age ollowed by iden ical i s -o de
s ages M . The alues o he in eg a o weigh s
a e
(2)
As in all cascade Ms [26], he ou pu s o he s ages
a e p ocessed in he digi al domain h ough simple ope a o s
and combined o cancel ou he quan iza-
ion noise gene a ed in each s age bu he las one. Addi ionally,
a pseudomul ibi ope a ion [18], [27] is achie ed by including
mul ibi quan iza ion only in he las s age, while he emaining
a e single bi . Linea ized -domain analysis shows ha he mod-
ula o ou pu can be exp essed as ollows [4]:
(3)
whe e s ands o he inpu signal, which is simply delayed,
is he las -s age quan iza ion e o , which is shaped by
an h -o de unc ion, and ep esen s he nonlinea i y
e o o he las -s age DAC. No e ha , since is gene -
a ed in a -bi quan ize , he modula o esponse equals ha
o an ideal h-o de -bi M, excep o he ac o 2. The
aim o his ac o , ha equals ,is o
Fig. 2. SNDR e sus inpu le el o se e al modula o o de s.
compensa e o he signal scaling equi ed o a oid p ema u e
o e loading o he modula o . By in eg a ing he e o e ms in
(3) o e he signal band, he in-band quan iza ion e o powe is
ob ained [4] as
(4)
whe e
(5)
a e he o al powe associa ed wi h he las -s age quan iza ion
e o and he DAC nonlinea i y e o , espec i ely, wi h INL
being he DAC in eg al nonlinea i y ela i e o he inpu ull
scale .
Since he ac o 2 in (3) quad uples he in-band powe o hese
e o s, a 1-b sys ema ic loss o esolu ion is gene a ed. Howe e ,
his loss is small when compa ed o o he cascade Ms and,
mo e impo an ly, i is cons an , ega dless o he numbe o
s ages. In ac , he mos appealing ea u e o his a chi ec u e
(wi h he se o coe icien s p oposed) is ha i can be easily se
o any o de jus by changing he numbe o iden ical i s -o de
s ages. As shown in Fig. 2, a co ec ope a ion is main ained
wi h cons an o e loading poin , ega dless o he o e all o de .
The coe icien s in (2) also ha e he ollowing in e es ing
p ope ies.
1) The ou pu swing equi ed in all in eg a o s is only he
quan ize ull-scale.
2) By p ope sha ing o he swi ched-capaci o (SC) inpu
s ages, hey can be implemen ed wi h jus wo-b anch
in eg a o s, which minimizes he numbe o uni a y
capaci o s.
3) All i s -o de s ages, bu he las one in case o using
mul ibi quan iza ion, con ain he same coe icien s, so
ha hey can be elec ically iden ical.
This conside ably simpli ies he elec ical and physical imple-
men a ion o he modula o .
A. Nonideal Pe o mance
SC implemen a ions o cascade modula o s su e om ce -
ain nonideal beha io s mo e han hei single-loop coun e -
pa s, namely: ini e (and nonlinea ) ampli ie dc gain and ca-
DEL RIO e al.: HIGHLY LINEAR 2.5-V CMOS MODULATOR FOR ADSL 49
(a)
(b)
Fig. 3. E ec o (a) ini e dc gain and (b) weigh misma ch on he SNDR o
single-bi
2
0
161
Ms o
M
=16
.
paci o misma ch [4]. Bo h nonideali ies modi y he ideal in e-
g a o -domain ans e unc ion, hus al e ing he quan iza ion
e o ans e unc ion. Since his a ia ion is no co ela ed o
changes o he cancella ion logic, misma ch appea s be ween he
analog and digi al p ocessing ha p ecludes pe ec cancella ion
o he low-o de quan iza ion e o . In o i s -o de app oxima-
ion, he in-band powe o he e o leakages is independen o
, because hey a e gene a ed in he modula o i s s age, which
is he same o wha e e [4]
(6)
whe e s ands o he i s -s age ampli ie dc gain, and
is he capaci o a io s anda d de ia ion. I we compa e (4) and
(6) o a gi en , i is clea ha o ce ain alues o , ,
and hese e ec s may domina e he in-band e o powe , hus
imposing an uppe bound o he p ac ical alues o .
In o de o es ima e his limi unde ealis ic ci cui impe -
ec ions, Fig. 3(a) shows he simula ed hal -scale SNDR as a
unc ion o he ampli ie dc gain o . Fig. 3(b) shows
he SNDR his og ams ob ained om Mon e Ca lo simula ion
assuming 0.1% sigma in capaci o a ios—0.05% is cu en ly
ea u ed by me al–insula o –me al (M-i-M) capaci o s in
CMOS p ocesses. Unde hese condi ions, mainly because
o he ma ching sensi i i y, he se en h-o de a chi ec u e
seems no wo h implemen ing o . Ne e heless, he
six h-o de modula o p o ides a 90-dB wo s -case SNDR wi h
dc gain o 2500. Especially obus is he i h-o de cascade
equi ing a dc gain o 1000 o achie e 80-dB wo s -case SNDR
wi h . I is impo an o ema k ha hese gains a e
basically needed o he i s -s age ampli ie s. The dc-gain
equi emen o he in eg a o s in he emaining s ages
Fig. 4. ENOB e sus las -quan ize esolu ion o a
2
0
1 61
M in he
p esence o ci cui impe ec ions.
o he cascade a e much mo e elaxed. This is also applicable
o o he ci cui impe ec ions such as elec onic noise, ini e
dynamics, nonlinea i y, and misma ch. This p ac ice allows us
o use simple ci cui opologies and layou s o hese s ages,
hus sa ing a ea and powe consump ion.
Likewise, in p ac ice, he numbe o bi s in he las -s age
quan ize canno be a bi a ily la ge. As shown in Fig. 4,
o a gi en , he e olu ion o he o e all e ec i e esolu ion
wi h ends o sa u a e due o he p esence o leakage. Ne -
e heless, depending on he signal bandwid h, he educ ion in
o e sampling a io ha can be achie ed by eso ing o mul ibi
quan iza ion may de ine he bo de be ween easible and in ea-
sible implemen a ions. As we will show u he on, p ope se-
lec ion o he h ee main design pa ame e s ( , , and )is
he key o eally e icien implemen a ions.
III. DEEP-SUBMICROMETER DESIGN CONSIDERATIONS
Viabili y o cascade mul ibi Ms in deep-submic ome e
CMOS is ela ed o wo main p ocess ea u es: supply ol age
and capaci o pe o mance. The supply ol age, h ough he se-
lec ion o he e e ence ol ages, de ines he a ailable dynamic
ange, bu also makes an impac on he selec ion o he ampli ie
opology and i s capabili y o ade open-loop dc gain, speed,
and ou pu swing [28]. An empi ical uppe bound o a easible
is gi en by
e e ences a e (7)
whe e is he sa u a ion ol age o he ampli ie ou pu de-
ices and is he numbe o ansis o s in he ou pu b anch,
which again depends on he speci ic ampli ie opology. I a
single-s age ampli ie is used, cascode de ices will be equi ed
o achie e enough dc gain, so ha . This common choice
is no adequa e in low- ol age implemen a ions, whe e an ex-
cessi e alue o will esul in a idiculously small alue
o . Among he al e na i es, we coun on wo-s age ampli-
ie s [28], whose ou pu b anch can con ain only wo ansis o s
s ill p oducing a la ge open-loop dc gain. This al-
lows us o inc ease he alue o up o use ul le els a he
p ice o an inc eased powe dissipa ion. Apa om he am-
pli ie s, he pe o mance o he swi ches wi h supply ol ages
below 2.5 V needs ca e ul con ol, especially o dynamic dis-
o ion conside a ions [29]. Fo b oad-band Ms, solu ions
a e in he clock-boos ing s a egies [30] o in he employmen o
50 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
Fig. 5. Mos e icien cascade
61
M o each egion o he esolu ion-speed
plane.
high- ol age de ices a ailable in double-oxide p ocesses, wi h
he subsequen inc ease in p ice, ci cui complexi y, and powe
dissipa ion.
The second mos ele an echnology ea u e has o do wi h
he quali y o he capaci o s uc u es. Acco ding o he esul s
shown in Sec ion II, ypical capaci o ma ching equi emen s
ange om 0.1% o 0.2% s anda d de ia ion. Low pa asi ics
a e also o ex eme impo ance o an e icien implemen a-
ion o a high- equency modula o , and inally, we ha e he
capaci o linea i y equi emen s, which a e less demanding p o-
ided ha symme ical ully-di e en ial ci cui y is used. Fo -
una ely, M-i-M capaci o s a e now a ailable in CMOS p o-
cesses. They exhibi an excellen ma ching and linea i y, wi h
e y small bo om pa asi ics.
In o de o quan i a i ely e alua e p e ious assump ions,
we ha e de eloped an analy ical p ocedu e o es ima e he
powe consump ion o di e en cascade single-bi and/o
mul ibi Ms. In he unde lying exp essions, de ailed in he
Appendix, bo h a chi ec u e and echnological ea u es a e
con empla ed, oge he wi h simpli ying assump ions inspi ed
in p ac ical design solu ions. The aim he e is no only o d aw
conclusions abou a chi ec u al choices, bu also o ack hei
e olu ion unde echnology changes. To his end, he ollowing
igu e-o -me i (FOM) has been used [31]:
FOM Powe
DOR (8)
whe e DOR s ands o he digi al ou pu a e, i.e., he Nyquis
a e.
In a i s compa ison s ep, he iads desc ibing
speci ic cascades ha e been e alua ed along he cu e in he
esolu ion-speed plane shown in Fig. 5 (dashed line). Al hough
his pa icula esolu ion-speed ela ionship is a bi a y, i i s
he usual equi emen s o wi eline elecom ADCs: in eg a ed
se ices digi al ne wo k (ISDN), ADSL, VDSL, e c., which
ha e been placed in he igu e o illus a ion. Fo each sec-
ion o he esolu ion-speed cu e, he a chi ec u e wi h he
minimum FOM has been no ed. Obse e ha , as he ou pu
a e inc eases, he o e sampling a io dec eases and, simul a-
neously, he inc eased numbe o bi s in he mul ibi quan ize
shows up o compensa e o he o e sampling educ ion. No e
ha he 4.4-MS/s DOR employed in ADSL alls in o he
Fig. 6. Es ima ed e olu ion o he FOM wi h echnology scaling o h ee
cascade a chi ec u es ob aining 14 [email p o ec ed] MS/s.
egion led by he a chi ec u e , i.e., a ou h-o de
2–1-1 cascade wi h 3-b quan iza ion in he las s age and using
a 16 o e sampling a io, which will be ou choice.
In a second s ep, we ake ad an age o he ac ha some
echnology ea u es en e he abo e o mula ion o p edic how
he pe o mance o he cascade Ms is going o e ol e unde
echnology changes. Fig. 6 shows he es ima ed e olu ion
o he FOM o h ee cascade opologies, namely ,
, and , aimed a ob aining 14 b a 4.4
MS/s. These a e ypical speci ica ions o ADSL modems.
Two ac s a e no iceable.
•Despi e he educ ion o he supply ol age, o e all, he
powe dissipa ion does no dec ease below 0.18 m. This
is basically due o he educ ion in supply ol ages, which
imposes a educ ion in he e e ence ol age and, hence, a
compensa ing inc ease in he sampling capaci o s. Since
he incomple e se ling e o powe mus be also kep con-
s an , his mechanism leads o an inc eased cu en abso p-
ion, which makes he o e all powe consump ion inc ease
below 0.18 m. The loca ion o he in lec ion poin de-
pends on he con e e speci ica ions. Fo ins ance, i o
he same speed, he esolu ion is o be inc eased, he in-
lec ion poin mo es o he igh in Fig. 6.
•Ano he aspec illus a ed in Fig. 6 is he dynamic na-
u e o he a chi ec u e selec ion in Fig. 5. No e ha he
M ou pe o ms o 0.25 m and abo e, bu
i does no below 0.18 m.
IV. SC IMPLEMENTATION
Fig. 7 shows he ully di e en ial SC schema ic o he
M. The i s s age o he cascade includes wo in-
eg a o s—wi h one and wo inpu b anches, espec i ely—and
swi ches con olled by he compa a o ou pu s o eed he
quan ized signal back. The second s age uses an in eg a o wi h
only wo inpu b anches o implemen weigh s , , and ,
since he alues in (2) allow dis ibu ion o be ween he
wo b anches. The same applies o in he hi d s age. The
hi d-s age in eg a o d i es he 3-b ADC and he loop is closed
by a 3-b DAC. The 1-o -8 ou pu code o he ADC is con e ed
DEL RIO e al.: HIGHLY LINEAR 2.5-V CMOS MODULATOR FOR ADSL 51
Fig. 7. SC implemen a ion o he
2
0
1
mul ibi
61
modula o .
in o bina y by a ead-only memo y (ROM) ha gene a es he
co esponding bi s eams.
The modula o ope a ion is con olled by wo nono e lapped
clock phases. The in eg a o inpu signals a e sampled du ing
phase . Du ing phase , he algeb aic ope a ions a e pe -
o med and esul s a e accumula ed in he eedback capaci o s.
In o de o a enua e he signal-dependen clock- eed h ough,
delayed e sions o he wo phases ( and ) a e also p o-
ided. This delay is inco po a ed only o he alling edges o he
signals (swi ches u n o ), while he ising edges a e synch o-
nized in o de o inc ease he e ec i e ime-slo o he modu-
la o ope a ions [15]. The compa a o s and he las -s age ADC
a e ac i a ed a he end o —using as s obe— o a oid
any possible in e e ence due o he ansien esponse o he in-
eg a o s a he beginning o sampling.
V. SPECIFICATIONS FOR THE BUILDING BLOCKS
The con e e speci ica ions ha e been mapped on o basic
building block equi emen s by ollowing an op imiza ion
p ocess suppo ed by beha io al simula ions [4]. Table I sum-
ma izes he modula o sizing achie ing 13 [email p o ec ed] MS/s. Fi e
g oups o speci ica ions a e enclosed: modula o , on -end
TABLE I
MODULATOR SIZING
TABLE II
MAIN IN-BAND ERROR CONTRIBUTIONS
in eg a o , ampli ie , compa a o , and A/D/A con e e . In his
p ocedu e, he wo s -case pe o mance has been e alua ed in
he p esence o a ia ions in he p ocess ( o ins ance, changes
in he capaci o absolu e alue), empe a u e, and supply.
Table II shows a summa y o he mos signi ican con ibu ions
o he in-band e o powe . Main conside a ions made o his
sizing a e desc ibed nex .
The i s s ep o he modula o sizing is he selec ion o .
In his selec ion, bo h he o e loading cha ac e is ics o he
modula o and he na u e o he signal being con e ed mus be
conside ed. In ou case, he o e loading poin is nea ly 5dB

52 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
(a)
(b)
Fig. 8. (a) Time-domain ep esen a ion o a
0
15-dB DMT signal. (b) SNDR
o he con e ed DMT signal as a unc ion o he e e ence ol age.
(see Fig. 2), while he la ges inpu is he 15-dB disc e e
mul i one (DMT) signal shown in Fig. 8(a). No e ha , al hough
i s powe is no oo high, la ge peaks appea om ime o
ime, hus yielding he high c es ac o [32] peculia o DMT
signals (5.4 in ou case). Fo una ely, he du a ion o hese
peaks is sho enough no o o e load he modula o . In o de
o illus a e his, Fig. 8(b) shows beha io al simula ion esul s
o he modula o SNDR o such an inpu signal as a unc ion
o he e e ence ol age. In spi e o he p esence o a signal
peak o app oxima ely 1 V, he modula o SNDR is co ec
up o V (no e ha his would ne e be he case o
a 1-V ampli ude inpu sinewa e, since i would be inside he
modula o o e loaded egion wi h 1.3-V e e ence). In o de o
p o ide a sa e y ma gin, V was aken. Re u ning
o (7), his e e ence ol age gi es us a ma gin o 500 mV
pe ou pu ansis o in a wo-s age ully di e en ial ampli ie
supplied wi h 2.5 V. As shown in Fig. 7, is implemen ed
using di e en ial e e ences, so ha .
In Table II, he in-band e o powe o quan iza ion e o has
been spli up in i s ou con ibu ions associa ed o: he ideal
quan iza ion e o [ i s e m in (4)], ini e dc gain [ i s e m
in (6)], capaci o misma ch [second e m in (6)], and las -s age
DAC nonlinea i y [second e m in (4)]. No e ha he quan iza-
ion e o leakage will be domina ed by capaci o misma ch. Al-
hough M-i-M capaci o s exhibi good ma ching—
o 1-pF caps— he use o small uni a y capaci o s (0.66 pF) o
dynamic conside a ions inc eases he sensi i i y o he cascade,
so ha we ha e assumed wice ha alue o . The con ibu-
ion o he 3-b DAC nonlinea i y is 6 dB below he ideal quan-
iza ion noise o INL FS, which is easily achie able
wi hou calib a ion. The noise leakage due o he ampli ie dc
gain is almos negligible o . Howe e , as we ex-
plain u he on, his alue will no be u he elaxed in o de
o a oid excessi e dis o ion due o dc-gain nonlinea i y.
Following he discussion in Sec ion III and in he Appendix,
a small sampling capaci o pF is used in o de
o educe he capaci i e load o he in eg a o s and, hence, hei
powe dissipa ion. So, whi e ci cui noise becomes he dominan
e o sou ce. A mo e exac exp ession ( han he one used in he
Appendix) o i s in-band e o powe is [3]
GB (9)
whe e is he ampli ie inpu - e e ed whi e noise and
GB is he e ec i e ampli ie gain–bandwid h p oduc (in Hz),
which du ing in eg a ion can be app oxima ed o
GB GB
GB
GB
GB (10)
whe e GB is he ampli ie gain–bandwid h p oduc (in Hz),
is he swi ch on- esis ance, and is he pole associa ed wi h
he cons an o he SC b anch du ing in eg a ion.
The i s con ibu ion in (9) yields a wo s -case alue o
86.0 dB— o maximum empe a u e 110 C and 20
ole ance in he capaci o alue. On he o he hand, o GB and
ixed acco ding o se ling conside a ions o 265 MHz and
150 , espec i ely, GB will be 250 MHz. An equi alen
he mal noise a he ampli ie inpu o 6 nV Hz is he e o e
enough o ob ain a noise con ibu ion simila o ha o he
noise 87.5 dB . Besides, he wo s -case ampli ie
whi e noise con ibu ion co esponds o he la ges GB ,
which a ies along he p ocess co ne s. Assuming ha i can
be as la ge as wice i s nominal alue (i.e., 500 MHz), his
wo s -case con ibu ion yields 84.5 dB.
The limi ed ampli ie GB in oduces basically a gain e o in
he in eg a o ans e unc ion. This e o is especially impo -
an in he in eg a o s o he i s s age o he cascade, because
he quan iza ion e o o his s age will leak o he modula o
ou pu . Fo he a chi ec u e conside ed ope a ing wi h ,
he ampli ie mus ul ill GB o a oid deg ada ion o
he modula o pe o mance due o incomple e se ling, being
he sampling equency.
I he ini e on- esis ance o he swi ch is also conside ed,
he e ec i e ampli ie esponse is slowed down, as s a ed in
(10). This e ec is illus a ed in Fig. 9(a) ha shows beha io al
simula ion esul s o he in-band e o powe as a unc ion o he
no malized ampli ie GB, o di e en alues o . The co -
esponding alues o he no malized pole a e also depic ed.
No e ha , as he pole dec eases, he ampli ie GB mus be
inc eased in o de o compensa e o he slowdown. A swi ch e-
sis ance o 150 is ixed o his design. On he one hand, as we
show u he on, his esis ance can be ob ained using s anda d
CMOS ansmission ga es, wi hou clock boos ing. On he o he ,
he ampli ie GB mus be inc eased jus o GB in o de
o main ain he modula o pe o mance. Assuming ha app ox-
ima ely 85% o he clock pe iod is le o he in eg a o ope a-
ion (a e ensu ing nono e lapping and delay in he clock-phase
signals), he equi ed GB is app oxima ely 265 MHz.
DEL RIO e al.: HIGHLY LINEAR 2.5-V CMOS MODULATOR FOR ADSL 53
(a)
(b)
Fig. 9. (a) In-band e o e sus no malized ampli ie GB o di e en swi ch
on- esis ances. (b) In-band e o e sus no malized ampli ie SR o di e en
inpu ampli udes.
The equi ed ampli ie slew a e (SR) is es ablished gua an-
ying ha he slew- a e limi ed e olu ion a he beginning o in-
eg a ion and sampling [33] is as enough o he subsequen
linea dynamic o se le o he desi ed accu acy. Fo his mod-
ula o , a no malized SR SR is su icien o en-
su e co ec pe o mance. Howe e , since he ope a ion o he
on -end in eg a o is pa ially SR limi ed, he dynamic will
be also pa ially nonlinea and app eciable ha monic dis o ion
may a ise. This e ec is illus a ed in Fig. 9(b), whe e beha -
io al simula ion esul s a e shown o he modula o in-band
e o powe e sus he no malized ampli ie SR, o di e en
ampli udes o a sinewa e inpu . No e ha , o he co ec con-
e sion o an inpu sinewa e o maximum ampli ude (0.85 V),
he no malized SR mus be inc eased up o 6.5. Assuming ha
85% o he clock pe iod is le o he in eg a o ope a ion, he
equi ed SR is app oxima ely 800 V s.
Thanks o o e sampling, some speci ica ions in Table I e-
e ing o he on -end in eg a o can be elaxed o he es o
in eg a o s. Speci ically, he alue o he sampling capaci o in
hose in eg a o s can be p og essi ely scaled down, since hei
con ibu ions o he o e all noise a e a enua ed in he
signal band. Ne e heless, ma ching conside a ions and elia-
bili y p eclude using e y small capaci o s. In his design he
scaling o he nominal (0.66 pF) is limi ed o 32%, which
means ha 0.45-pF uni a y capaci o s a e used in he es o in-
TABLE III
SCALING OF THE AMPLIFIER SPECIFICATIONS
eg a o s. On he con a y, he inpu - e e ed whi e noise o he
ampli ie s a he modula o back-end can be conside ably in-
c eased wi hou jeopa dizing pe o mance.
A mo e agg essi e educ ion can be applied o he o he ci -
cui equi emen s. Fo ins ance, he ampli ie dc gain o he
hi d and ou h in eg a o s can be educed o 600, because he
in-band powe s o he espec i e quan iza ion e o leakages a e
p opo ional o and , and he e ec o hei nonlin-
ea i y is negligible when compa ed o ha in he on -end in-
eg a o . Mo eo e , he SR can be elaxed o 350 V s, as hei
se ling beha io s a e no so impo an . Table III summa izes
he speci ica ions o he ou in eg a o s in he cascade a e
scaling.
VI. DESIGN OF THE BUILDING BLOCKS
A. Ampli ie s
The iple adeo among dc gain, dynamics and ou pu
swing, always p esen in an ampli ie [28], becomes igh e
in a low- ol age implemen a ion. We ha e al eady shown
ha he selec ion o he e e ence ol age and he opology
o he on -end ampli ie a e in e ela ed in deep-submic on
cascade Ms, he eason being ha la ge enough
equi es wo-s age ampli ie s in o de o achie e he dc gain
and dynamic equi emen s. Fo una ely, his is no he case o
he ampli ie s a he modula o back-end, whose dc gain can be
la gely elaxed, so ha a single-s age ampli ie may be enough.
The e o e, in o de o a oid o e -sizing and op imize he powe
consump ion, wo di e en ampli ie s ha e been designed: a
high-dc-gain, high-speed ampli ie o he i s s age (OPA),
and a modes dc-gain, high-speed ampli ie o he hi d and
ou h in eg a o s (OPB).
OPA is implemen ed using a wo-s age wo-pa h compen-
sa ed a chi ec u e, shown in Fig. 10(a). I uses a elescopic i s -
s age and bo h Mille and Ahuja compensa ion [34] h ough ca-
paci o s and , espec i ely. The common-mode eedback
ne s (CMFB) employed in he i s and second s ages a e dy-
namic, because hey ha e no s a ic consump ion and help o ci -
cum en ol age ange p oblems. A p- ype inpu scheme has
been p e e ed, he main eason being he possibili y o can-
celling he body e ec in he pMOS de ices—one o he mecha-
nisms o subs a e noise coupling [35]. Ano he eason o his
choice is ha , in he a ge echnology, noise o nMOS de-
ices is conside ably la ge han ha o pMOS ones. Al hough
noise usually plays a seconda y ole in elecom con e e s,
since i no mally does no alias and he low- equency egion o
he spec um is commonly ou o he signal band, he noise
54 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
(a)
(b)
Fig. 10. (a) Two-s age ampli ie (OPA). (b) Single-s age ampli ie (OPB).
powe spec al densi y (PSD) o e y small de ices can be huge
[36] and some imes poo ly modeled, hus dese ing special a -
en ion in deep-submic ome e implemen a ions. This end p e-
cludes using minimal leng h ansis o s, e en mo e no iceably
han i only ma ching conside a ions a e aken in o accoun . In
ou case, he de ices con ibu ing mos o he ampli ie noise
a e , , , and . In o de o make he noise con-
ibu ion negligible, he leng h o hose de ices was inc eased
up o 0.5 m o he pMOS and 2 m o he nMOS. In he
wo s case, he in-band e o powe due o he noise o he
on -end ampli ie is –103.6 dB, low enough no o deg ade he
pe o mance.
OPB is implemen ed using a olded-cascode a chi ec u e,
shown in Fig. 10(b), which is enough o accomplish he
mode a e dc gain equi emen wi h educed powe dissipa ion.
An SC CMFB is also employed.
Table IV shows he ea u es o OPA and OPB ob ained
by elec ical simula ion a e ull sizing. Resul s summa ized
co espond o he wo s -case alue o each pa ame e in a
co ne analysis—conside ing as and slow de ice models,
5 a ia ion in he 2.5-V supply, and empe a u es in he
ange 40 C 110 C .
The ampli ie nonlinea ea u es (mainly nonlinea dc gain
and dynamics) dese e special a en ion in a low- ol age im-
plemen a ion. When he ampli ie ou pu ol age swings, he
d ain- o-sou ce ol age o he ou pu ansis o s changes, and so
does he ou pu impedance. This e ec , illus a ed in Fig. 11 o
OPA, ansla es in o a dependence o he open-loop dc gain on
TABLE IV
WORST-CASE ELECTRICAL SIMULATION RESULTS FOR THE AMPLIFIERS
Fig. 11. DC gain nonlinea i y o OPA a se e al p ocess co ne s.
he ou pu ol age, so ha he dc gain eaches i s maximum a he
cen al poin and dec eases as he ou pu app oaches he ails.
Such a nonlinea i y is adi ionally modeled by a second-o de
polynomial dependence o he gain on he ou pu ol age [4], bu
his is only alid o small ol age excu sions a ound he cen-
al poin . On he con a y, in a 2.5-V implemen a ion, i is ex-
pec ed ha small-gain egions o he dc cu e (shadowed a eas
in Fig. 11) a e o en isi ed du ing no mal ope a ion o he mod-
ula o . In o de o accu a ely accoun o his nonlinea i y in be-
ha io al simula ions, we ha e eso ed o a able look-up p o-
cedu e om ampli ie dc cu es ob ained by elec ical simula-
ion. A simila app oach has been employed o alida ing he
ac ual ansien esponse o he on -end in eg a o . This s ep
is aimed a a oiding inaccu acies o he single-pole SR limi ed
beha io al model employed [33] when applied o he wo-s age
ampli ie wi h noncons an SR in he i s in eg a o .
B. Swi ches
The design o he CMOS swi ches has been ackled wi h wo
main conside a ions in mind. Fi s , he nonze o on- esis ance
hea ily a ec s he in eg a o dynamic, slowing down i s an-
sien esponse. Second, he swi ch on- esis ance can be highly
dependen on ol age in low- ol age implemen a ions. The
sampling p ocess wi h such a nonlinea esis ance causes dy-
namic dis o ion [29] a he M on -end, he mo e e iden
he la ge he signal equency. Among he solu ions o hese
p oblems, eso ing o la ge aspec a ios inc eases pa asi ics
and powe dissipa ion, whe eas including clock-boos ing [30]
inc eases complexi y and leads o a less obus design.
Acco ding o se ling conside a ions, esis ances in he ange
o 150 can be ole a ed in combina ion wi h he ampli ie
dynamics. In ou p ocess, such a alue can be ob ained using
DEL RIO e al.: HIGHLY LINEAR 2.5-V CMOS MODULATOR FOR ADSL 55
Fig. 12. Swi ch on- esis ance e sus he ol age ac oss i .
Fig. 13. Ci cui o he e alua ion o he dis o ion in oduced by he swi ches.
s anda d- h eshold CMOS ansmission ga es, wi h no need o
clock boos e s. The sizes o he pMOS and nMOS de ices we e
selec ed o equalize hei ansconduc ances, keeping he e-
sis ance o he ansmission ga e as linea as possible. Fig. 12
shows i s nominal dc cha ac e is ic.
In o de o e alua e he dis o ion, he nonlinea sampling
has been ex ensi ely simula ed using he di e en ial ci cui y
in Fig. 13. No e ha he dis o ion will be mainly de e mined
by swi ches and (connec ed o he inpu ), whe eas and
a e connec ed o he cen al ol age ha is cons an . Elec-
ical simula ions ha e been pe o med o compu e he i s i e
in-band ha monics o a 0.85-V, 366-kHz inpu sinewa e. Also,
he DMT signal in Fig. 8(a) has been conside ed. Fig. 14 shows
he wo s -case esul s ob ained o bo h ype o inpu s du ing
he co ne analysis: The wo s -case o al ha monic dis o ion
(THD) is 96 dB o he inpu sinewa e and he maximum mul-
i one powe a io (MTPR) [32] o he con e ed DMT signal is
81 dB. Bo h igu es a e small enough o ou applica ion, so
ha clock-boos ing is no equi ed.
C. Quan iza ion Blocks
The esolu ion speci ica ions o he compa a o s in he i s
and second s age a e no e y demanding: o se and hys e esis
smalle han 10 and 20 mV, espec i ely. Howe e , he max-
imum compa ison ime is only 3 ns—a qua e o he wo s -case
clock pe iod. Fo his eason, he la ched compa a o in Fig. 15
has been adop ed. I includes a di e en ial pai inpu anscon-
duc o [37], which a enua es he impac o common-mode in-
e e ences, a egene a i e s age, and an SR la ch. In his ci cui ,
he small ol age imbalance c ea ed ac oss he nMOS swi ch
con olled by du ing he ese phase is ail- o- ail egene -
a ed du ing he posi i e- eedback compa ison phase. The la e
s a s when goes high, hus making he la ch eac be o e he
in eg a o ou pu changes a he beginning o . This s a egy
a oids using an ex a SC s age a he compa a o on -end.
Di e enced supply pa hs a e used o he p eampli ie and he
egene a i e la ch in o de o educe he sensi i i y o digi al
swi ching noise and supply bouncing.
The 3-b A/D/A con e e in he las s age has been imple-
men ed wi h a lash ADC and a esis i e-ladde DAC, as shown
in Fig. 16 [18]. The esis i e-ladde is also used o gene a e
he ol age e e ences o he ADC. The la e has a ully di -
e en ial lash a chi ec u e, whe e he he mome e ou pu code
is ansla ed in o a 1-o -8 code using AND ga es. Fo imp o ing
obus ness agains common-mode in e e ences, se en di e en-
ial compa a o s, simila o hose in he i s and second s age
o he cascade, o m he ADC on -end, each o hem wi h wo
inpu pai s o pe o m he sub ac ion o he wo di e en ial sig-
nals being compa ed. Apa om his, he only di e ence wi h
hose in he i s - and second-s age compa a o s is ha he inpu
ansis o s ha e been educed in size in o de o dec ease he ca-
paci i e load o he ou h in eg a o .
The DAC consis s o 14 segmen s o 50- poly esis o s,
he mos impo an sou ce o INL being esis o misma ch,
which imp o es wi h de ice a ea. Thus, in o de o gua an ee
ha INL FS, each o he 50- esis o s is ob ained by
connec ing la ge de ices in pa allel.
D. Auxilia y Blocks
Fig. 17 shows he clock d i e ha gene a es he nono e -
lapped clock phases—,— om an ex e nal clock signal.
Delayed e sions o he phases—,—a e also gene a ed
o a oid signal-dependen clock- eed h ough. As shown in
Fig. 7, he delay is inco po a ed only o he u n-o o he
swi ches ( alling edges o he signals) in o de o inc ease
he ime slo a ailable o sampling and in eg a ion [15].
Complemen a y e sions o he phases a e also gene a ed o
con ol he CMOS swi ches. All signals a e p ope ly d i en a
he ou pu using a bu e ee ha equalizes he di e ences in
capaci i e load om phase o phase. A e ensu ing eliable
nono e lapping ime and phase delay, he wo s -case e ec i e
phase eye is 6 ns, which means ha app oxima ely 85% o he
clock pe iod is le o he modula o ope a ion.
The e e ence ol ages equi ed o he modula o ope a ion,
namely V and V, oge he wi h he cen-
al ol age a e on-chip gene a ed by he ci cui shown in
Fig. 18. I s main design conside a ions a e as se ling and ha
he ou pu impedance o he and lines mus be low
enough o a oid dynamic dis o ion a he in eg a o s [38]. In
ou case, 7- maximum ou pu impedance is ob ained along
he signal band h ough he combined use o an on-chip esis-
i e ampli ie and wo big ex e nal capaci o s. An ex a ex e nal
capaci o is connec ed be ween he e e ence ol ages, alued
acco ding o he pad wi e lead pin pa asi ics, so ha he
spu ious componen s a ound hal he sampling equency a e e-
mo ed om he di e en ial e e ence ol age.
A second-o de passi e an ialiasing il e is also included
on-chip. I s bandwid h can be p og ammed o accomplish
62 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 51, NO. 1, JANUARY 2004
JoséM. de la Rosa ecei ed he “Licenciado en
Física Elec ínica”(elec onics physics) deg ee and
he Ph.D. deg ee om he Uni e si y o Se ille,
Se ille, Spain, in 1993 and 2000, espec i ely.
Since 1994, he has been wo king a he Ins i u e
o Mic oelec onics o Se ille (IMSE-CNM, CSIC).
He is also wi h he Depa men o Elec onics and
Elec omagne ism a he Uni e si y o Se ille, whe e
he is an Associa e P o esso . His main esea ch in e -
es s a e in he ield o swi ched-cu en sigma–del a
analog- o-digi al con e e s including analysis,
beha io al modeling, and design au oma ion o such ci cui s. In his opic,
he has coau ho ed he book Sys ema ic Design o CMOS Swi ched-Cu en
Bandpass Sigma-Del a Modula o s o Digi al Communica ion Chips (Bos on,
MA: Kluwe , 2002).
BelénPé ez-Vé dú ecei ed he Liceniado en
Físcia Elec ónica and he Ph.D. deg ees om he
Uni e si y o Se ille, Se ille, Spain, in 1979 and
1985, espec i ely.
She has been an Associa e P o esso a he
Uni e si y o Se ille since 1987. She is also
wi h he Ins i u e o Mic oelec onics o Se ille
(IMSE-CNM, CSIC). He esea ch ac i i ies a e in
he ield o mixed-signal in eg a ed ci cui design, in
pa icula , sigma–del a modula o s, compu e -aided
design, and modeling o analog in eg a ed ci cui s.
She has published wo books and mo e han 70 pape s, including jou nal and
con e ence pape s. She has pa icipa ed in se e al Eu opean ESPRIT p ojec s
and Spanish CICYT p ojec s.
Manuel Delgado-Res i u o ecei ed he Ph.D.
deg ee in physics om he Uni e si y o Se ille,
Se ille, Spain in 1996.
In 1990, he joined he esea ch s a o he Ins i u e
o Mic oelec onics o Se ille (IMSE-CNM, CSIC).
Since 1998, he has occupied a pe manen posi ion as
a enu ed Scien is o he Spanish Council o Scien-
i ic Resea ch (CSIC). He has esea ch in e es s in he
design o analog and mixed-signal VLSI ci cui s o
nonlinea signal p ocessing, including ision chips,
neu o- uzzy con olle s, and chao ic ci cui s o com-
munica ions. His wo k in hese a eas has esul ed in sys ema ic design me hod-
ologies o hese kinds o ci cui s. He is also in e es ed in he design and mod-
eling o in eg a ed ci cui s o wi eless and powe line communica ion sys ems
and he design o eusabili y o analog and mixed-signal ci cui blocks. He au-
ho ed o coau ho ed mo e han 80 in e na ional scien i ic publica ions and has
been in ol ed in di e en na ional and Eu opean R&D p ojec s.
Ra ael Domínguez-Cas o ecei ed he “Licenciado
en Física Elec ínica”deg ee and he Ph.D. deg ee
om he Uni e si y o Se ille, Se ille, Spain, in 1987
and 1993, espec i ely.
Since 1987, he has been wi h he Depa men o
Elec onics and Elec omagne ism a he Uni e si y
o Se ille, whe e he is cu en ly an Associa e
P o esso . He is also wi h he Ins i u e o Mic o-
elec onics o Se ille (IMSE-CNM, CSIC), whe e
he is a membe o a esea ch g oup on Analog and
Mixed-Signal VLSI. His esea ch in e es s a e in he
design o embedded analog in e aces o mixed-signal VLSI ci cui s, design
o CMOS image s and CMOS ocal plane a ay p ocesso s, and de elopmen
on CAD o au oma ion o analog design.
D . Domínguez-Cas o was a co- ecipien o he 1995 Guillemin–Caue
Awa d o he IEEE Ci cui s and Sys ems Socie y and he Bes Pape Awa d o
he 1995 Eu opean Con e ence on Ci cui Theo y and Design.
Fe nando Medei o ecei ed he “Licenciado en
Física Elec ínica”deg ee and he Ph.D. deg ee om
he Uni e si y o Se ille, Se ille, Spain, in 1990 and
1997, espec i ely.
Since 1991, he has been wi h he Ins i u e o
Mic oelec onics o Se ille (IMSE-CNM, CSIC). He
is also wi h he Depa men o Elec onics and Elec-
omagne ism, Uni e si y o Se ille, whe e he is an
Associa e P o esso . His esea ch in e es s a e in he
ield o sigma–del a con e e s, including modeling,
beha io al simula ion, and design au oma ion. On
his opic, he has pa icipa ed as a Lec u e in se e al in e na ional cou ses and
has coau ho ed he book Top-Down Design o High-Pe o mance Sigma-Del a
Modula o s (Bos on, MA: Kluwe , 1998).
Angel Rod íguez-Vázquez (M’80–SM’95–F’96)
ecei ed he Liceniado en Físcia Elec ónica and
he Ph.D. deg ees om he Uni e si y o Se ille,
Se ille, Spain, in 1977 and 1983, espec i ely.
He is a P o esso o Elec onics in he Depa men
o Elec onics and Elec omagne ism, Uni e si y
o Se ille. He is also a Membe o he Resea ch
S a o he Ins i u e o Mic oelec onics o Se ille
(IMSE-CNM, CSIC), whe e he is heading a esea ch
g oup on Analog and Mixed-Signal VLSI. His e-
sea ch in e es s a e in he design o analog in e aces
o mixed-signal VLSI ci cui s, CMOS image s and ision chips, neu o- uzzy
con olle s, symbolic analysis o analog in eg a ed ci cui s, and op imiza ion o
analog in eg a ed ci cui s.
D . Rod íguez-Vázquez se ed as an Associa e Edi o o he IEEE
TRANSACTIONS ON CIRCUITS AND SYSTEMS I (IEEE TCAS-I) om 1993 o
1995, as a Gues Edi o o he IEEE TCAS-I Special Issue on “Low-Vol age
and Low-Powe Analog and Mixed-Signal Ci cui s and Sys ems”(1995), as
Gues Edi o o he IEEE TCAS-II Special Issue on “Ad ances in Nonlinea
Elec onic Ci cui s”(1999), and as chai o he IEEE-CAS Analog Signal P o-
cessing Commi ee (1996). He was a co- ecipien o he 1995 Guillemin-Caue
awa d o he IEEE Ci cui s and Sys ems Socie y and he Bes Pape Awa d
o he 1995 Eu opean Con e ence on Ci cui Theo y and Design. In 1992, he
ecei ed he Young Scien is Awa d o he Se ille Academy o Science.