FINAL DEGREE THESIS
Bachelo ’s Deg ee in Elec ic Enginee ing
DEVELOPMENT OF A ROBUST THREE-PHASE INVERTER FOR
MICROGRID (MG) AND ELECTRIC TRACTION
EXPERIMENTATION: CONTROL SUBSYSTEM
Repo and Annex
Au ho s: Pau No oa Pé ez
Co-supe iso s: He minio Ma ínez Ga cía
Xa ie Jo dà Sa uny
Depa men : Depa men o Elec onics Enginee ing
Call: 2025, Janua y
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
i
Abs ac
This hesis p esen s he app oach, design, implemen a ion and manu ac u e o he con ol o a h ee-
phase in e e , de eloped o expe imen a ion in mic og ids and ac ion o elec ical machines.
Th oughou his wo k, he h ee-phase in e e and i s design will be b ie ly explained o in oduce
some o he mos widesp ead con ol s a egies in he con ol and powe elec onics sec o o hese
ype o con e e s.
Nex , he de elopmen o he con ol subsys em o a h ee-phase in e e o labo a o y
expe imen a ion will be shown, om he app oach and design o he manu ac u e and es ing o i .
This sec ion will aim o show he ollowing design s a egies, selec ion o componen s, sys ems and
de ices chosen and so wa e implemen a ion o ca y ou he con ol o he in e e heo e ically
desc ibed while mee ing he speci ic equi emen s o he p ojec .
The aim o he wo k is o deepen he design aspec s o he con ol o a h ee-phase in e e , p esen ing
di e en al e na i es, o inally implemen he design o a obus con ol wi h speci ic equi emen s.
Finally, he pe o mance o he de eloped sys em will be es ed along he powe subsys em o mee
he equi emen s and expec a ions se by bo h he bases o hese con e e s and he objec i es se by
he p ojec .
Memo y
ii
Resum
Aques a esi p esen a l'ap oximació, disseny, implemen ació i ab icació del con ol d'un in e so
i àsic, desen olupa pe a l'expe imen ació en mic oxa xes i acció de màquines elèc iques.
Al lla g d'aques eball s'explica à b eumen l'in e so i àsic i el seu disseny pe in odui algunes de
les es a ègies de con ol més es eses en el sec o de l'elec ònica de con ol i po ència pe a aques
ipus de con e ido s.
A con inuació, es mos a à el desen olupamen del subsis ema de con ol d'un in e so i àsic pe a
l'expe imen ació en labo a o i, des de l'ap oximació i el disseny ins a la ab icació i p o a d'aques .
En aques apa a , es p e én mos a les següen s es a ègies de disseny, selecció de componen s,
sis emes i disposi ius escolli s i implemen ació de p og ama i pe du a e me el con ol de l'in e so
eò icamen desc i complin els equisi s especí ics del p ojec e.
L'objec iu del eball és ap o undi en els aspec es de disseny del con ol d'un in e so i àsic,
p esen an di e en s al e na i es, pe inalmen implemen a el disseny d'un con ol obus amb
eque imen s especí ics.
Finalmen , el endimen del sis ema desen olupa es p o a à al lla g del subsis ema de po ència pe
compli els equisi s i expec a i es es able s an pe les bases d'aques s con e ido s com pels
objec ius ixa s pel p ojec e.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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Resumen
Es a esis p esen a el en oque, diseño, implemen ación y ab icación del con ol de un in e so
i ásico, desa ollado pa a la expe imen ación en mic o edes y la acción de máquinas eléc icas.
A lo la go de es e abajo, se explica á b e emen e el in e so i ásico y su diseño, con el in de
in oduci algunas de las es a egias de con ol más ex endidas en el sec o de la elec ónica de
po encia y con ol pa a es e ipo de con e ido es.
A con inuación, se mos a á el desa ollo del subsis ema de con ol de un in e so i ásico pa a
expe imen ación en labo a o io, desde el plan eamien o y diseño has a su ab icación y p ueba. Es a
sección iene como obje i o mos a las es a egias de diseño empleadas, la selección de
componen es, los sis emas y disposi i os escogidos, así como la implemen ación del so wa e
necesa io pa a lle a a cabo el con ol del in e so desc i o eó icamen e, cumpliendo con los
equisi os especí icos del p oyec o.
El p opósi o de es e abajo es p o undiza en los aspec os del diseño del con ol de un in e so
i ásico, p esen ando di e en es al e na i as pa a, inalmen e, implemen a un diseño de con ol
obus o que sa is aga los equisi os plan eados.
Po úl imo, se e alua á el endimien o del sis ema desa ollado jun o con el subsis ema de po encia,
e i icando que cumpla con los equisi os y expec a i as es ablecidos an o po las bases de es os
con e ido es como po los obje i os de inidos en el p oyec o.
Memo y
i
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
App ecia ions
I would like o exp ess my since e g a i ude o my TFE co-coo dina o s, Xa ie Jo dà Sa uny and
He minio Ma inez Ga cia, o hei in aluable guidance and suppo h oughou his wo k.
I would also like o hank IMB-CNM(CSIC) o g aciously allowing me o use hei acili ies and
esou ces, which we e c ucial o he de elopmen o his hesis.
My hea el hanks go o ePowe ed RACING, wi hou my ime in he associa ion his would no ha e
been possible as I could no ha e ound my passion o enginee ing.
To Ad ià A oca, my p ojec colleague, wi h whom I ha e wo ked nail o oe o be able o de elop his
p ojec .
Finally, I would like o hank my amily and iends o hei suppo , encou agemen , and pa ience
du ing he cou se o his p ojec .
Memo y
i
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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2. In oduc ion
2.1. Objec i e
As men ioned be o e, his documen aims o be a guide on how o design he con ol o a h ee-phase
in e e om sc a ch, de ining he basics o he implemen a ion o a obus ci cui and algo i hm ha
makes he powe subsys em wo k wi h a high pe o mance.
Fi s , con ex will be gi en on h ee-phase in e e ’s design and he con ol o his ype o con e e s
will be deeply explained. This will include explaining he p inciples o DC-AC con e sion o elec ic
ene gy, main powe swi ching con ol ypes used in mos applica ions digging dip in o PWM and space
ec o con ol, he used con ol me hod will be p esen ed and explained in de ail and inally he
implemen a ion o his con ol along he ci cui designed o i will be explained.
Nex , i will be de ailed how o design, de elop, and alida e a con ol o h ee-phase in e e sys em
ha egula es powe deli e y h ough Space Vec o Pulse Wid h Modula ion. The p ojec de ails he
comple e p ocess o designing an in eg a ed ci cui and implemen ing he equi ed ha dwa e and
so wa e o ensu e co ec unc ionali y.
The PCB design includes a mic ocon olle , le el shi e s, dead- ime ci cui s, and signal condi ioning
ci cui s necessa y o communica ing wi h a powe subsys em. In addi ion, i includes This sys em aims
o p o ide p ecise swi ching signals o powe ansis o s, ensu ing eliable ope a ion unde di e en
load condi ions.
The p ojec also in ol es p og amming con ol algo i hms, ocusing on SVPWM, o maximize in e e
pe o mance and imp o ing he o e all e iciency o powe con e sion. To achie e his, eal- ime da a
acquisi ion om senso s h ough Analog- o-Digi al Con e e s is inco po a ed, allowing he sys em o
moni o pa ame e s such as DC bus ol age used o adjus modula ion and swi ching imes.
Tes ing and alida ion o he subsys em and he whole h ee-phase in e e will be ca ied, ocusing
on e i ying he shape o he PWM signals, analyzing he in e e ’s pe o mance unde load condi ions,
and e icien elec ic powe con e sion. The main objec i e is o make su e he con ol subsys em
wo ks along he powe subsys em and adds up o a unc ional h ee-phase in e e .
Memo ia
6
2.2. Scope
Scope o he p ojec includes he ollowing poin s:
- In oduc ion o he h ee-phase in e e : In oduc ion o he con e e ’s ope a ion and
scheme / design.
- Con ol s a egies o h ee-phase in e e s: In oduc ion o mos used con ol s a egies o
he h ee-phase DC-AC con e e s and selec ion o desi ed s a egy o he p ojec .
- Ha dwa e design: Design o he di e en elec ical ci cui s o he con ol subsys em and
implemen a ion in p in ed ci cui boa d.
- Con ol scheme design o a h ee-phase in e e : Re iew o he con ol scheme designed o
he con e e , so wa e selec ion and code implemen a ion.
- Resul s and alida ion o inal p o o ype: P esen a ion o inal de ice, wi h esul s o di e en
es s made in labo a o y expe imen a ion and alida ion o pe o mance.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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3. Theo e ical in oduc ion
In his sec ion, heo e ical in oduc ion on h ee-phase in e e s and con ol s a egies will be
explained and de ailed o gi e a base o he de eloped wo k in his p ojec .
3.1. DC-AC con e sion
An in e e is a con e e ha allows o make a DC-AC elec ic ene gy con e sion, his is a con e sion
ha ans o ms di ec cu en (DC) in al e na e cu en (AC) o en e e ed as “in e sion”, which
de i es in he name in e e o he de ice ha ealizes his ope a ion.
As shown in Figu e 3.1.1, di ec signals like DC ol ages o cu en s, a e signals whose mean alue is
cons an and di e en o ze o o e ime, while AC signals a e known o ha e a mean alue equal o
ze o o e ime. In elec ici y, di ec cu en also has he cha ac e is ic o ha ing a single low di ec ion,
while al e na e cu en can low in bo h posi i e and nega i e di ec ions depending on he ins an .
Figu e 3.1.1. DC and AC signals.
DC-AC con e sion is used in a wide ange o applica ions including enewable ene gy sys ems (sola
pho o ol aic gene a ion), elec ic ac ion, elec ic ehicles, unin e up ible powe sou ces, e c.
So, being used in so many di e en ields and applica ions, he e ha e been loads o e o s o e ol e
his ype o con e e s and hei pe o mance. In addi ion, di e en ypes o hese kind o con e e s
ha e been de eloped o co e all hese applica ions, hey may need di e en ypes o con ol, powe ,
equencies…
A basic DC-AC con e sion s uc u e, o in e e s uc u e, ha allows he DC ol age (u) and cu en (i)
wi h e e ence in he sou ce (poin s M and N) o low in wo di ec ions o gene a e an al e na ing
Memo ia
8
cu en in he load (poin s O and O’), being u’ and I’ he co esponding AC ol age and cu en [1], is
shown in Figu e 3.1.2:
Figu e 3.1.2. Basic DC-AC con e e s uc u e [1].
K1 and K1’ a e complemen a y swi ches, as K2 and K2’ also a e. When K1 is closed K1’ is opened and ice
e sa, same happens wi h K2 and K2’.
Di iding he ime in small pe iods T, al e na ing cu en om he di ec cu en sou ce is gene a ed
wi h an easy algo i hm o con ol he opening and closu e o he 4 swi ches:
- 0 < < T/2
K1 and K2’ a e closed while K1’ and K2 a e opened, applying a posi i e DC ol age be ween O and O’ and
making he di ec cu en low om O o O’ du ing T/2.
- T/2 < < T
K1’ and K2 a e closed while K1 and K2’ a e opened, applying a nega i e DC ol age be ween O and O’
and making he di ec cu en low om O’ o O du ing T/2. This can be seen in a.
Figu e 3.1.3. Basic DC-AC con e sion. F om op o bo om, di ec cu en u ha ing a cons an alue U, al e na e cu en u’
ha ing a alue o U du ing T/2 and -U du ing T/2 [1].
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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As i can be seen in Figu e 3.1.3., ol age in he load is an al e na ing signal which will lead o an
al e na ing cu en when a ce ain impedance is connec ed be ween O and O’. This al e na ing ol age
was gene a ed om a DC ol age om he sou ce simply by applying a simple algo i hm o he
opening and closu e o he 4 swi ches.
Applying di e en algo i hms, he AC ol age and cu en in he load can be o med in mul iple ways,
such as sinusoidal al e na ing signals, iangula signals… Jus my modi ying he imes in which DC
ol age is applied in posi i e / nega i e di ec ions, mean alues inside he swi ching pe iod can be lowe
o highe o o m an AC ol age and cu en , wi h lowe equency han he swi ching equency bu
di e en shape and cha ac e is ics.
𝑓𝑠=1
𝑇
(1)
Memo ia
10
3.2. Th ee-phase in e e s
Ha ing e iewed how DC-AC con e sion is pe o med wi h he use o a ci cui made wi h ou swi ches
and a simple con ol algo i hm, a single-phase in e e , he s uc u e o a h ee-phase in e e can be
easily explained by jus making h ee b anches made up o a single-phase in e e each, all h ee
connec ed o he DC sou ce, and each one connec ed o each phase o he load, as illus a ed in Figu e
3.2.1.
Figu e 3.2.1. Th ee -phase in e e basic ci cui , wi h del a and s a connec ions [22].
As i can be depic ed in he p e ious image, he DC sou ce E is eeding h ee b anches, wi h wo
complemen a y swi ches each QX, and e e y swi ch QX is placed wi h an an ipa allel diode which allows
e u n cu en s om he load.
F om he cen e poin o each b anch, each line o he h ee-phase load is connec ed and ed wi h
posi i e o nega i e ol age om he DC sou ce, depending on which swi ch o each b anch is closed
and which is open.
A ansis o wi h an an ipa allel diode is he mos used solu ion o his g oup o swi ches, and i allows
he in e e o be a ou -quad an con e e , which allows bo h ol age and cu en in bo h di ec ions.
I is impo an o accoun o e u n cu en s, as no mally induc i e loads a e ed (elec ic mo o s o
d i es, coils…) wi h his ype o con e e s, and hese e u n high amoun s o ene gy when nega i e
cu en s a e applied o hem, which is he case o AC loads.
The mos common ol age and cu en s gene a ed wi h in e e s is h ee-phase sinusoidal al e na ing
cu en . To be able o gene a e his ype o cu en , swi ches mus be con olled in o de hey gene a e
h ee al e na ing cu en s om he DC sou ce, wi h sinusoidal wa e o ms displaced 120º be ween
each o he .
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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So, knowing one each pai o complemen a y swi ches will be conduc ing e e y 180º, and ha a h ee
AC cu en s displaced 120º be ween each o he mus be gene a ed, i is ob ious ha h ee ou o he
six swi ches will be conduc ing a any momen . This leads o 6 di e en possibili ies o connec ion o
he h ee-phase in e e , seen in Figu e 3.2.2.
Figu e 3.2.2. Six di e en connec ion possibili ies [8].
Phase and line ol ages will depend on he connec ion o he phases, hence hey will depend on which
swi ches a e conduc ing. So, con olling he opening and closu e o he swi ches, i will be possible o
con ol he ol ages applied on he h ee-phase side, always keeping a ixed e e ence in he DC sou ce.
Memo ia
12
3.3. Th ee-phase in e e con ol
The con ol o a h ee-phase in e e plays a pi o al ole in ensu ing he powe e iciency o he
con e e i sel . These me hods con ol he commu a ion o he ansis o s based on di e en
s a egies wi h he objec i e o educing losses, ha monic educ ion, p ecise con ol, simplici y e c.
The me hods discussed in his chap e a e based in pulse wid h modula ion (PWM) an ex ended
s a egy. In speci ic sinusoidal PWM (SPWM) and space ec o PWM (SVPWM) a e e iewed.
3.3.1. Pulse Wid h Modula ion (PWM)
Pulse Wid h Modula ion (PWM) is a echnique used o con ol he elec ical powe deli e ed o some
de ices in which, in a ixed pe iod, he wid h o he pulses om he o iginal sou ce is a ied. This
modula ion echnique is commonly used in powe elec onics in DC-DC, AC-DC, o DC-AC con e e s
such as boos s, bucks, ec i ie s o in e e s.
The idea is o connec he o iginal sou ce o he connec ed de ice h ough a con olled swi ch such as
a ansis o . This ansis o is hen ga e-con olled by he PWM signal, so i will connec sou ce and
load when he PWM signal gi es a logic high alue (logic 1) and disconnec hem when he signal has a
logic low alue (logic 0).
This modula ion echnique allows in con e e s wi h a DC sou ce o educe he mean alue o e he
pe iod be ween 0 and Vdc. In in e e s i allows ep oducing di e en wa e o ms o ge AC ol ages in
he load om a DC sou ce.
The wo mos impo an pa ame e s in a PWM a e he pe iod (T), which dic a es he equency a
which he ampli ude o he signal will change and also he ange in which he swi ch will ope a e, and
he du y cycle ha is he ampli ude o he signal wi hin he ime pe iod. The du y cycle is calcula ed as
ollows:
𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒(%)= 𝜏
𝑇∗100
(2)
Whe e T is he o al pe iod and τ he semi pe iod in which he pulse is in logic 1. Figu e 3.3.1 illus a es
h ee di e en PWM wi h 10%, 50% and 90% du y cycle.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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Figu e 3.3.1. Th ee PWM wi h di e en du y cycles.
So, in con e e s wi h DC sou ces such as in e e s, he mean alue o e a pe iod o he ou pu ol age
will be, conside ing he sou ce ol age has a alue o Vdc:
𝑉𝑚𝑒𝑎𝑛 =𝑉𝑑𝑐∗𝑑𝑢𝑡𝑦 𝑐𝑦𝑐𝑙𝑒
100 =𝑉𝑑𝑐∗𝜏
𝑇
(3)
So, in a h ee-phase in e e , h ee PWM can be modi ied o ha e a du y cycle ha c ea es h ee
ol age wa e o ms om he DC sou ce one ha ha e a mean alue o 0 o e a bigge pe iod han he
PWM one, hus gene a ing an AC ol age.
Memo ia
20
3.3.3.3. SVPWM: applica ion o ec o ial modula ion
As men ioned be o e, SVPWM is a p ac ical applica ion o ec o ial modula ion. As i is used o ope a e
in e e s usually in mo o con ol, i s main goal is o p oduce sinusoidal al e na ing ol ages o p oduce
s a o cu en s ha gene a e a o a ing ield. In h ee-phase in e e s, h ee sinusoidal cu en s wi h a
120º o se in be ween hem.
To achie e his, a o a ing ol age ec o mus be p oduced in α-𝛽 e e ence wi h he desi ed
ampli ude and equency eques ed by he con ol. Knowing he e e ence ampli ude (V e ) and
e e ence equency desi ed ( e ), he h ee ol ages desi ed in abc e e ence a e:
𝑣𝑎(𝑡)=𝑉𝑟𝑒𝑓·sin(2𝜋𝑓𝑡)
(11)
𝑣𝑏(𝑡)=𝑉𝑟𝑒𝑓·sin(2𝜋𝑓𝑡+𝜋
3)
(12)
𝑣𝑐(𝑡)=𝑉𝑟𝑒𝑓·sin (2𝜋𝑓𝑡−𝜋
3)
(13)
Re e ence α-𝛽 ol ages can be ex ac ed om Cla ke’s ans o ma ion:
[𝑣𝛼
𝑣𝛽]=2
3
[
1 −1
2−1
2
0√3
2−√3
2
]
[𝑣𝑎
𝑣𝑏
𝑣𝑐]
(14)
As explained in sec ion 3.3.3.2, α-𝛽 ol ages o m a e e ence ol age ec o , and his can be gene a ed
using he eigh di e en disc e e ol age ec o s om he eigh di e en swi ching s a es. This come
om he opening and closu e o he swi ches o he h ee b anches o he in e e , being Q1, Q3 and
Q5 he uppe swi ches connec ed o Vdc and Q2, Q4 and Q6 he lowe swi ches connec ed o g ound.
Knowing he swi ches o he same b anch can’ be in he same s a e a he same ime, he e a e 8
possible di e en ol age ec o s ha can be applied. The ollowing able summa izes hese ec o s,
he line- o-line ol ages applied based on DC e e ence ol age Vdc and he α-𝛽 ol ages p oduced.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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Table 3.3.1: Disc e e ol age ec o s, in unc ion o he ansis o s combina ion, line- o-line ol ages and al a-be a
componen s. 0: Open, 1: Closed.
Vec o
name
Q1
Q3
Q5
an
bn
cn
α
β
e
𝒗𝟎
0
0
0
0
0
0
0
0
0
𝒗𝟏
1
0
0
2𝑉𝐷𝐶
3
−𝑉𝐷𝐶
3
−𝑉𝐷𝐶
3
𝑉𝐷𝐶
3
𝑉𝐷𝐶
√3
2
3𝑉𝑏𝑎𝑡
𝒗𝟐
1
1
0
𝑉𝐷𝐶
3
𝑉𝐷𝐶
3
−2𝑉𝐷𝐶
3
−𝑉𝐷𝐶
3
𝑉𝐷𝐶
√3
2
3𝑉𝑏𝑎𝑡𝑒𝑗1𝜋
3
𝒗𝟑
0
1
0
−𝑉𝐷𝐶
3
2𝑉𝐷𝐶
3
−𝑉𝐷𝐶
3
−2𝑉𝐷𝐶
3
0
2
3𝑉𝑏𝑎𝑡𝑒𝑗2𝜋
3
𝒗𝟒
0
1
1
−2𝑉𝐷𝐶
3
𝑉𝐷𝐶
3
𝑉𝐷𝐶
3
−𝑉𝐷𝐶
3
−𝑉𝐷𝐶
√3
2
3𝑉𝑏𝑎𝑡𝑒𝑗𝜋
𝒗𝟓
0
0
1
−𝑉𝐷𝐶
3
−𝑉𝐷𝐶
3
2𝑉𝐷𝐶
3
𝑉𝐷𝐶
3
−𝑉𝐷𝐶
√3
2
3𝑉𝑏𝑎𝑡𝑒𝑗4𝜋
3
𝒗𝟔
1
0
1
𝑉𝐷𝐶
3
−2𝑉𝐷𝐶
3
𝑉𝐷𝐶
3
2𝑉𝐷𝐶
3
0
2
3𝑉𝑏𝑎𝑡𝑒𝑗5𝜋
3
𝒗𝟕
1
1
1
0
0
0
0
0
0
I can be seen ha he e a e six ac i e ec o s (1 o 6) wi h a 60º o se be ween hem and wo null
ec o s 𝑣0
,
𝑣7
which apply no ol age o he h ee phases.
These 6 sec o s sepa a ed 60º be ween hem a e delimi ed by wo ec o s each one which can be
ex ac ed om:
𝑣 𝑖=2
3𝑉𝑏𝑎𝑡𝑒𝑗(𝑖𝜋
3)
(15)
𝑣 𝑖+1 =2
3𝑉𝑏𝑎𝑡𝑒𝑗(𝑖𝜋
3+𝜋
3)
(16)
These six ec o s delimi ing he six sec o s o m a hexagon shown in Figu e 3.3.4, he o a ing ec o
in α-𝛽 e e ence will be no mally inside a ci cula ajec o y, bu i can each he alues ou side his
ange i i espec s he hexagon pe ime e .
Memo ia
22
Figu e 3.3.4. Vol age limi hexagon and e e ence ec o in α-
𝛽
plane [13].
In his hexagon in he α-𝛽 plane, he dis ance be ween he cen e o he axis and one o he hexagon
e ices is 2
√3∗𝑉𝑑𝑐, while he dis ance be ween he axis cen e and he cen e o e e y side o he
hexagon, which is he ci cle adius is Vdc.
To gene a e a sinusoidal ol age, as in he ‘abc’ h ee-phase e e ence, a e e ence ol age ec o in α-
𝛽 plane mus be o a ing along he axis and inside hese delimi ed pe ime e s. The angula eloci y and
ampli ude o his ec o will e lec on he ou pu ol age, which will ha e he same equency and
line- o-line ampli ude.
E e y wo ec o s delimi a sec o (i) numbe ed om 1 o 6, sec o s a e used in con ol o unde s and
which ec o s ha e o be applied in e e y poin o o a ion o he ec o . In e e y sec o , he wo
adjacen ec o s and he null ec o s ( 0 and 7) can be used o inc ease he ampli ude o modi y he
angle o he ol age ec o .
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
23
3.3.3.4. Opening and closing imes calcula ion
Fo his p ojec , an open loop SVPWM is going o be designed in o de o con ol he h ee-phase
in e e ’s ene gy p ocessing subsys em o which he con ol is designed [7]. This means e e ence
ol age ampli ude and equency will be gi en by he con ol, so V e , α and 𝛽 will be gene a ed and
calcula ed by he con ol i sel ins ead o being gi en by any o he ype o con ol such as FOC o DTC.
E e y ins an , acco ding o he e e ence ampli ude and equency, he ol age ec o magni ude and
angle will be gene a ed om hese and applied as a e e ence o he con ol, ha ing o gene a e h ee
120º o se PWM ha will make o a sinusoidal ou pu in he h ee-phase in e e .
To implemen his algo i hm, i will jus ake o calcula e o how much ime each one o he wo
adjacen ol age ec o s o e e y sec o is applied in e e y momen depending on he e e ence ec o
gi en, and how much ime he null ec o s a e applied inside e e y pe iod. The pe iod will be gi en by
he commu a ion equency ( com), which will be 15.625 kH, hence he e e y pe iod Tcom will be 64 μs.
Fi s , he e e ence ec o is decomposed in a linea addi ion o alpha and be a axis ec o s. This is
made by simply ep esen ing he e e ence ec o as a ec o ial sum o bo h ec o s, in which be a is
ep esen ed as he imagina y pa and alpha as he eal pa o he ec o [23].
𝑣 𝑠∗=𝑣𝑠𝛼
∗+ 𝑗𝑣𝑠𝛽
∗
(17)
Then, he ec o can be done easily decomposed as a sum o he wo e e ence ec o s adjacen o he
sec o in which i is a e e y ins an . Taking a look a an example in which he ec o is in sec o one in
Figu e 3.3.5, i can be easily seen how he e e ence ec o s in α-𝛽 plane can be decomposed as a
sum o he wo uni a y ec o s 1 and 2 mul iplied by he ime in which hey a e applied.
Memo ia
24
Figu e 3.3.5. Vol age ec o decomposi ion in sec o 1, α-
𝛽
plane. [23]
Gene alizing o e e y sec o , he e e ence ec o can be sepa a ed in he sum o he i s ec o o
he sec o i and he second i+1 mul iplied by he semi pe iods in which hey a e applied (τi and τi+1)
and added o he ime he null ec o s a e applied also mul iplied by hei semi pe iods (τ0 and τ7).
𝑣 𝑠∗=𝑣𝑠𝛼
∗+ 𝑗𝑣𝑠𝛽
∗=𝜏0𝑣 0+ 𝜏7𝑣 7+𝜏𝑖𝑣 𝑖+ 𝜏𝑖+1𝑣 𝑖+1
(18)
The e e ence ec o will esul in a linea combina ion o he uni a y ec o s, which di ec ly ep esen
a conc e e swi ching s a e o he in e e , and he null ec o s which also ep esen ixed swi ching
s a es o he in e e .
All he uppe ansis o s Q1, Q3 and Q5 will ecei e a PWM ha will change in e e y pe iod Tcom based
on he semi pe iods in which e e y uni a y ec o is applied, which can be seen in Table 3.3.1.
Combining equa ions 17 and 18 he eal imes in which e e y non-null ec o is applied a e calcula ed
[23]:
𝑇𝑖=(𝑠𝑖𝑛(𝑖𝜋
3)𝑣𝑠𝛼
∗−𝑐𝑜𝑠(𝑖𝜋
3)𝑣𝑠𝛽
∗)√3·𝑇𝑐𝑜𝑚
𝑉𝑏𝑎𝑡
(19)
𝑇𝑖+1=(−𝑠𝑖𝑛((𝑖−1)𝜋
3)𝑣𝑠𝛼
∗+𝑐𝑜𝑠((𝑖−1)𝜋
3)𝑣𝑠𝛽
∗)√3·𝑇𝑐𝑜𝑚
𝑉𝑏𝑎𝑡
(20)
Subs i u ing o e e y sec o , hese a e he imes in which e e y uni a y ec o is used depending on
he e e ence alpha and be a ol ages:
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
25
Table 3.3.2: Commu a ion imes o each sec o , o a s a load [23].
𝑖=1
𝑖=2
𝑖=3
𝑇1=√3
2𝑉𝑏𝑎𝑡(√3𝑣𝑠𝛼
∗
−𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇2=√3
𝑉𝑏𝑎𝑡(+𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇2=√3
2𝑉𝑏𝑎𝑡(√3𝑣𝑠𝛼
∗
+𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇3=√3
2𝑉𝑏𝑎𝑡(−√3𝑣𝑠𝛼
∗
+𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇3=√3
𝑉𝑏𝑎𝑡(𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇4=√3
2𝑉𝑏𝑎𝑡(−√3𝑣𝑠𝛼
∗
−𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑖=4
𝑖=5
𝑖=6
𝑇4=√3
2𝑉𝑏𝑎𝑡(−√3𝑣𝑠𝛼
∗
+𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇5=√3
𝑉𝑏𝑎𝑡(−𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇5=√3
2𝑉𝑏𝑎𝑡(−√3𝑣𝑠𝛼
∗
−𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇6=√3
2𝑉𝑏𝑎𝑡(√3𝑣𝑠𝛼
∗
−𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇6=√3
𝑉𝑏𝑎𝑡(−𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
𝑇1=√3
2𝑉𝑏𝑎𝑡(√3𝑣𝑠𝛼
∗
+𝑣𝑠𝛽
∗)𝑇𝑐𝑜𝑚
Wi h hese imes and Tcom, e e y o he ime as T0 and T7 can be calcula ed in o de o gi e he
ins uc ions o he du y cycle o he PWM o e e y ansis o .
The h ee PWM will be cen e aligned, which means he hal o he pe iod will also be he hal o he
semi pe iods in which e e y PWM is on high-le el.
Figu e 3.3.6. Vol age ec o decomposi ion in sec o 1, α-
𝛽
plane.
This will help educe ha monic dis o ion as i minimizes low equency ha monics in he ou pu ol age
making he wa e o ms smoo he . I will also dis ibu e swi ching losses as i dis ibu es swi ching
e en s e enly be ween he h ee b anches; In addi ion i will gi e symme ic ou pu wa e o ms and
imp o e ol age u iliza ion allowing be e usage o he DC sou ce.
Memo ia
26
So, o calcula e he du y cycles o e e y ansis o (TQ1, TQ3 and TQ5), i will jus be needed o ake a look
a Table 3.3.1 and he ec o s used in e e y sec o . Fo example i e e ence ec o is in sec o 1
(be ween angles 0 and π/3), only 1 (1,0,0) and ec o 2 (1,1,0) along wi h he null ec o s will be used.
Which means Q1 will be used in T1, T2 and T7, while Q3 will be used in T2 and T7 and Q5 will jus be used
in T7. In T0 all h ee PWM a e in low s a e.
Figu e 3.3.7. Th ee cen e aligned PWM in sec o 2, including which ec o 0, 1, 2, 7 is used o gene a e hem (R=Q1, S=Q3,
T=Q5). [6]
So, ha ing ec o imes T1 and T2, T0 is easily calcula ed as:
𝑇0=𝑇𝑐𝑜𝑚−𝑇1−𝑇2
(21)
𝑇7=𝑇0
2
(22)
Du y cycles will be calcula ed as:
𝑇𝑄1=𝑇1+𝑇2+𝑇0
2
(23)
𝑇𝑄3=𝑇2+𝑇0
2
(24)
𝑇𝑄5=𝑇0
2
(25)
T0 and T7 (T0/2) a e always calcula ed in he same way, he only hing ha will change o e e y sec o
is he ec o s used and hei imes (Ti and Ti+1) and which ansis o (Q1, Q3 and Q5) con ibu es o each
ec o . Fo example, looking a sec o 3 which is be ween angles 2π/3 and π o he αβ plane and
delimi ed by ec o s 3 and 4:
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
27
So, ha ing ec o imes T3 and T4, T0 is easily calcula ed as:
𝑇0=𝑇𝑐𝑜𝑚−𝑇3−𝑇4
(26)
𝑇7=𝑇0
2
(27)
Du y cycles will be calcula ed as:
𝑇𝑄1=𝑇0
2
(28)
𝑇𝑄3=𝑇3+𝑇4+𝑇0
2
(29)
𝑇𝑄5=𝑇4+𝑇0
2
(30)
Sec o 2 be ween π/3 and 2π/3:
𝑇0=𝑇𝑐𝑜𝑚−𝑇2−𝑇3
(31)
𝑇7=𝑇0
2
(32)
Du y cycles will be calcula ed as:
𝑇𝑄1=𝑇2+𝑇0
2
(33)
𝑇𝑄3=𝑇3+𝑇4+𝑇0
2
(34)
𝑇𝑄5=𝑇0
2
(35)
Sec o 4 be ween π and 4π/3:
𝑇0=𝑇𝑐𝑜𝑚−𝑇4−𝑇5
(36)
𝑇7=𝑇0
2
(37)
Du y cycles will be calcula ed as:
Memo ia
28
𝑇𝑄1=𝑇0
2
(38)
𝑇𝑄3=𝑇4+𝑇0
2
(39)
𝑇𝑄5=𝑇4+𝑇5+𝑇0
2
(40)
Sec o 5 be ween 4π/3 and 5π/3:
𝑇0=𝑇𝑐𝑜𝑚−𝑇5−𝑇6
(41)
𝑇7=𝑇0
2
(42)
Du y cycles will be calcula ed as:
𝑇𝑄1=𝑇6+𝑇0
2
(43)
𝑇𝑄3=𝑇0
2
(44)
𝑇𝑄5=𝑇5+𝑇6+𝑇0
2
(45)
Sec o 6 be ween 5π/3 and 2π:
𝑇0=𝑇𝑐𝑜𝑚−𝑇6−𝑇1
(46)
𝑇7=𝑇0
2
(47)
Du y cycles will be calcula ed as:
𝑇𝑄1=𝑇6+𝑇1+𝑇0
2
(48)
𝑇𝑄3=𝑇0
2
(49)
𝑇𝑄5=𝑇6+𝑇0
2
(50)
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
29
3.4. Mic ocon olle
To design a h ee-phase in e e con ol subsys em i is capi al o choose a sui able op ion o manage
all he compu ing, I/O signals and all he p ocesses. The e is a huge a ie y o di e en de ices such as
digi al signal p ocesso s (DSPs), ield-p og ammable ga e a ays (FPGAs) and mic ocon olle s (MCU).
Fo his p ojec , an MCU has been chosen o play he ole o con olling and compu ing all he o de s
and p ocesses ela ed o he in e e con ol. This choice has been made hinking in a o dabili y,
lexibili y, and he acili y MCU ha e because hey ha e mul iple pe iphe als in eg a ed like PWM
ime s, analog- o-digi al con e e s (ADCs) and communica ion in e aces which simpli y eal- ime
con ol asks, o example SVPWM in e e con ol.
Mic ocon olle s a e chips designed as compac compu ing sys ems and hey a e used o speci ic
asks. They combine a Cen al P ocessing Uni (CPU), memo y, and pe iphe als in a single de ice. They
can be used in a wide ange o applica ions such as au oma ion, powe elec onics and in e e con ol.
“Today, mic ocon olle p oduc ion coun s a e in he billions pe yea , and he con olle s a e in eg a ed
in o many appliances we ha e g own used o” [10].
Selec ing a mic ocon olle depends on p ocessing powe , pe iphe als, cos , and ene gy e iciency. The
op ion o his p ojec was he STM32F767 mic ocon olle in eg a ed in he STM32F767ZI lea ning
boa d o ‘nucleo’ ab ica ed and dis ibu ed by STMic oelec onics® shown in Figu e 3.4.1. The STM32
se ies was chosen o his p ojec o i s ad anced ime s, high-speed ADCs, easy and adap able
de elopmen sys em, and numbe o en ies. In addi ion, he au ho had some expe ience wi h he
STM32 se ies MCU and a lo o in o ma ion abou hem a ailable.
Figu e 3.4.1. STM32F767ZI boa d wi h STM32F767 MCU [19].
Memo ia
36
4. Design
Inside his chap e he design o he ha dwa e o he h ee-phase in e e con ol sys em will be shown
and explained in de ail. I is a c ucial pa o he p ojec as i ma e ializes all he heo e ical s udy ha
has been de eloped and i shows i in a eal and pa icula applica ion.
Fi s , he di e en elec ical ci cui s o he sys em will be analysed and desc ibed in o de o unde s and
he di e en unc ionali ies o he whole de ice. The di e en componen s used will be e iewed and
hei main unc ionali ies and cha ac e is ics men ioned.
Then, he physical ma e ializa ion o he p ojec will be e iewed, ocusing on he ab ica ion o he
elec ical ci cui as a p in ed ci cui boa d (PCB). All s eps, cha ac e is ics, es ic ions, echniques, and
conside a ions in ol ed in he manu ac u ing p ocess will be de ailed, e lec ing he comple e sys em.
4.1. Elec ical ci cui
The design o he elec ical ci cui o he h ee-phase in e e con ol sys em is c i ical o ensu e
unc ionali y and op imal pe o mance. I has o be concep ualized in a way all he di e en ci cui s
comp ising he sys em a e co ec ly in e connec ed and hei elec ical speci ica ions a e consis en ly
adhe ed o.
Fo he op imal ope a ion o he whole sys em, e e y componen mus ha e i s own ci cui in e ms o
powe sou ce, high equency il e ing and ol age ipple il e ing. In addi ion, e e y in o ou pin o he
in eg a ed ci cui componen s has o be connec ed in a ce ain way whe he i is connec ed o no .
No sho -ci cui s can be possible in any ci cui con igu a ion and all he necessa y componen s and
lines ha e o be designed in o de o compel wi h he sys em’s pu pose and speci ica ions. Finally, all
componen s ha mus be g ounded ha e o be connec ed be ween hem a he same ol age le el
(0).
Finally, all he inpu s o he sys em mus be connec ed h ough an en y po o hei des ina ion and
he ou pu signals om he sys em mus ha e a co ec exi po o access o he sys ems o he in e e
such as he ene gy p ocessing subsys em’s d i e s ha ha e o be connec ed o he ou pu PWM o
he con ol sys em.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
37
4.1.1. STM32F767ZI
The mic ocon olle is he cen al pa o he whole sys em, is he componen ha will ou pu he aw
signals om he SVPWM con ol and will ecei e he ea ed signals o he inpu e e ence con ol o
he AC ol age and equency and eed o wa d con ol o he DC ol age as well as he AC cu en s
moni o ing.
In Figu e 4.1.1 i is shown how he STM32F767ZI will be connec ed o he elec ical ci cui h ough ou
su ace-moun ed (SMD) 36 pin double ow connec o s wi h 2.54 mm spaced pins, he HLE-118-02-L-
DV-K model om SAMTEC, ha will be connec ed o he 144 ou pu pins o he MCU boa d.
Figu e 4.1.1: STM32F767ZI elec ical ci cui in in e e con ol sys em.
As seen in Figu e 4.1.1, he boa d will be ed a he common 5 V o he whole sys em h ough pin E5V
(pin 6 in STM32F767ZI, pin 5 in le -side smd connec o ), wi h an in e nal egula o ha educes om
5 V o 3.3 V i will eed he mic ocon olle and all he ea u es o he boa d. The ol age sou ce will be
gi en h ough wo ce amic capaci o s 10 μF and 100 nF ha will il e high equencies and ol age
ipple o he sou ce.
Memo ia
38
Figu e 4.1.1 akes a look a he wo se s o wo po en iome e s each: PTV09A-4020F-A503 wi h a 0-51
kΩ alue ange and PTV09A-4020F-A502 wi h a 0-5 kΩ ange will be connec ed in se ies o con ol bo h
e e ence AC ol age ampli ude and equency.
Figu e 4.1.2: Po en iome e elec ical ci cui o e e ence gene a ion .
Bo h po en iome e s a e ed wi h a 3.3 V sou ce ha comes om he ol age egula o o he
STM32F767ZI, ed h ough wo ce amic capaci o s 10 μF and 100 nF ha will il e high equencies
and ol age ipple o he sou ce.
The posi i e ol age will be connec ed o he posi i e pin o he 51 kΩ po en iome e , i s egula ed
esis ance pin (cen e pin) will be connec ed o he posi i e pin o he 5 kΩ po en iome e and o he
MCU’s ADC (pins 35 and 37 o STM32F767ZI) and i s egula ed esis ance pin (cen e pin) will be
connec ed o g ound. This way, a 0-55 kΩ egula ed esis ance will be made in which he ol age can
be egula ed om 3.3 V (0-51 kΩ po en iome e se o 0Ω) o 0 V (0-5 kΩ po en iome e se o 0Ω),
which will be bo h minimum and maximum e e ence alues o AC ol age ampli ude (0-300 V) and
equency (0-100 Hz).
Finally, six PWM (IGBT_Q1 o IGBT_Q6) will be ou pu ed om he MCU’s boa d h ough he
connec o s o he ollowing ci cui s (dead- ime and condi ioning 3.3 V o 5 V ci cui s); 3 AC cu en s
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
39
and DC ol age eedback will be inpu ed o he STM32F767ZI h ough hei condi ioning and il e ing
ci cui s de ailed in sec ion 4.1.4.
4.1.2. Dead ime ci cui
As explained in sec ion 3.5, he dead ime consis s in a sho delay in he signal o each o he PWM
signal, delaying he s a e swi ch. Six ci cui s ha e been designed like he one shown in Figu e 4.1.3, one
o each ansis o ’s con ol signals, all consis ing in he same ci cui model and componen s.
Figu e 4.1.3: Dead ime ci cui .
The ci cui is inpu ed he al eady le el-shi ed o 5 V PWM om he MCU (and h ough he le el-
shi e ci cui ). The ci cui consis s o a low-pass RC il e buil wi h a ix 1 kΩ esis ance and a a iable
0-51 kΩ SMD po en iome e (PVG5A503C03R00 se ies) connec ed in se ies wi h a 100 pF capaci o
and an an ipa allel high equency SMD diode (1N4148W-G se ies) ha allows o apidly discha ge he
capaci o .
The SVPWM ou pu om he MCU will ha e a equency o 15.625 kHz., so he low-pass il e o med
by he RC associa ion mus no il e he PWM ou pu bu be able o con ol he ising-up pulses o he
signal in o de o ha e dead- ime in he closing o he swi ches. The ange o equencies il e ed
depending on he R and C alues a e:
𝑓𝑐=1
2𝜋(𝑅+𝑅𝑝𝑜𝑡)𝐶
(52)
So, wi h po en iome e se o 0Ω, maximum equency ( c) allowed will be:
𝑓𝑐=1
2𝜋∗1000∗100∗10−12=1.591 𝑀𝐻𝑧
(53)
Memo ia
40
So, wi h po en iome e se o 51 kΩ, maximum equency allowed will be:
𝑓𝑐=1
2𝜋∗51000∗100∗10−12=31.2 𝑘𝐻𝑧
(54)
Wi h he bigges alue o he po en iome e he PWM pe iod equencies would be il e ed, so in o de
o he sys em o wo k co ec ly, a ixed alue o he po en iome e will be se o he dead- ime ci cui
o pe o m co ec ly and limi he minimum ime in he closing o he ansis o s.
A e a heo e ical i s app oach, he po en iome e alue will be adjus ed by hand in
expe imen a ion.
4.1.3. Bu e s, le el shi e s and igge Schmi ci cui s
The condi ioning ci cui s o he SVPWM MCU’s ou pu s a e c i ical o he pe o mance o he whole
sys em, including he ene gy p ocessing sys em ha ea s he HV signals. The eason behind i is ha
he whole con ol sys em has been s anda dized o a 5 V common ol age o all logic ci cui s, and he
op ocouple d i e wo ks wi h a cu en o 10 mA, which he MCU can no p o ide h ough he Gene al
Pu pose Inpu /Ou pu po s used o ou pu ing he six PWM.
Le el-shi e
As shown in chap e 3.6, he i s ci cui o in e ac wi h he ou pu signals a e he le el-shi e s ha
ele a e he logic high alue o he six PWM o 5 V ins ead o 3.3 V. The le el-shi e s used o his
pu pose a e he SN74HCT125N, wi h ou possible inpu /ou pu s ha can li he ol age o he high
equency digi al signals as i can wo k wi h ise/ alling imes o 500 ns o less.
Two le el-shi e s will be used o he six ansis o s’ PWM signals, h ee signals will be ope a ed in
each o he SN74HCT125N se ies chips. To be able o ou pu he signals a a ce ain ol age alue, he
componen s mus be ed a ha exac same alue. In his case, SN74HCT125N ha e o be gi en a supply
ol age be ween 3.5 V and 3.5 V [14], o his p ojec he supply ol age will be he common 5 V bus o
he sys em.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
41
Figu e 4.1.4: Le el-shi e ci cui s.
As seen in Figu e 4.1.4, U1 and U2 a e he co esponding le el-shi e ci cui symbols. The 5 V ol age
sou ce is ed h ough wo capaci o s o 1 μF and 100 nF as ecommended by Texas Ins umen s in he
componen ’s da ashee [14]. In addi ion, e e y pai inpu /ou pu po s ha e also a logic no po ha
ac i a es/deac i a es i s ou pu i i is g ounded (1-OE o 1A/1Y pai o inpu /ou pu pins). Any no
used pai o pins mus ha e inpu and logic ga e g ounded o he p ope unc ionali y o he chip.
Figu e 4.1.5: Le el-shi e unc ional block diag am. [14]
The U1 le el-shi e ecei es 3.3 V ansis o ’s 1 o 3 ou pu s om he MCU (IGBT_Q1 o IGBT_Q3) and
ou pu s he 5 V signal o he dead- ime ci cui (IGBT_1_5V o IGBT_3_5V), while U2 le el-shi e
ecei es 3.3 V ansis o ’s 4 o 6 ou pu s om he MCU (IGBT_Q4 o IGBT_Q6) and ou pu s he 5 V
signal o he dead- ime ci cui (IGBT_4_5V o IGBT_6_5V), dis ibu ing his way he powe and pins
usage o bo h chips.
Schmi igge
The in e ed igge Schmi used is he HEF40106BT-Q100J se ies om Nexpe ia, chosen because i s
wide ange o supply ol age 3 V-15 V [15] and he numbe o pins a ailable in each chip. A a 5 V supply
Memo ia
42
ol age i has go a minimum and maximum posi i e-going h eshold ol age o 2 V and 3.5 V
espec i ely and i s pe ec o co ec ly shaping and il e ing he modi ied PWM ou pu ed by he
dead- ime ci cui , gi ing a 5 V co ec ly shaped PWM bu al eady wi h he dead- ime delays.
Figu e 4.1.6 shows he ci cui s o he wo HEF40106BT-Q100J used in he con ol sys em ci cui , which
ecei e he signals om he dead- ime ci cui (al eady a 5 V as hey ha e been ou pu ed om he
le el-shi e s) as an inpu a A pins, and ou pu he il e ed bu in e ed PWM a 5 V wi h dead- imes:
Figu e 4.1.6: T igge Schmi ’s elec ical ci cui .
5 V ol age supply is il e ed by wo ce amic capaci o s o 10 μF and 100 nF as ecommended by he
da ashee [15], and he logic g ound o he chips is connec ed o he g ound e e ence o all he sys em.
Delayed signals o IGBTs 1 and 2 a e co ec ed and il e ed wi h IC1 and ou pu ed as in e ed 5 V
signals (IGBT_Q1_INV, IGBT_Q2_INV), while delayed signals o IGBTs 3 o 6 a e co ec ed and il e ed
wi h IC2 and ou pu ed as in e ed 5 V signals (IGBT_Q3_INV o IGBT_Q6_INV). Pins ha e been selec ed
o space and physical posi ioning o he chips as i will be shown in chap e 4.2.
Bu e
The in e ed bu e s used in he con ol sys em o he six ou pu PWM ha will eed he op o-d i e s
in he ene gy p ocessing sys em a e he MC14049UB hex bu e s om Onsemi. These allow a supply
ol age ange (VDD) o 3 V-18 V, can ou pu ol ages up o VDD + 0.5 V being able o ou pu a 45 mA
cu en [16] which is mo e han enough o he 10 mA needed by he op ocouple d i e s.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
43
Figu e 4.1.7: In e ed bu e s elec ical ci cui .
As illus a ed in Figu e 4.1.7, IC3 and IC4 a e he MC14049UB in e ed bu e s esponsible o
ou pu ing he six 5 V, dead- ime, il e ed and bu e ed PWMs adap ed o he op o-d i e s used in he
ene gy p ocessing subsys em ha will be esponsible o he ansis o s swi ching.
In e ed signals om Schmi igge s (IGBT_QX_INV) a e ed o he IN pins o he bu e s while
condi ioned signals o he d i e s (DI_IGBT_X) a e ou pu ed h ough OUT pins o bo h IC3 and IC4. As
i happened wi h IC1 and IC2, ansis o s 1 and 2 signals a e ea ed by IC3 and ansis o s 3 o 6 signals
a e ea ed by IC4 due o space and physical dis ibu ion in he PCB.
Memo ia
44
4.1.4. Analog- o-digi al con e e s and il e ing
As men ioned in chap e 3.7, he h ee AC ou pu cu en s and inpu DC ol age a e sensed and hei
alues sen in eal ime o he MCU’s ADC pe iphe als o be able o moni o and apply a eed o wa d
con ol o e he SVPWM ou pu .
Fo he co ec p ocessing o he signals, hese ha e o be adap ed o he 3.3 V ol age con ol ha he
ADCs make in o de o be able o ead hem p ope ly. S a ing wi h he AC cu en s, hese al eady a e
ol age signals egula ed a 3.3 V, so hey don’ ha e o be ea ed by any means in o de o he ADC
o ead hem co ec ly. Howe e , a low-pass il e has been designed o each signal o hem o a oid
high- equency noises ha could dis u b he signals, as illus a ed in Figu e 4.1.8:
Figu e 4.1.8: AC cu en s sensed signal il e s.
E e y AC cu en RST sensed signal is il e ed wi h a low-pass il e composed by a 1 kΩ esis ance and
a 100 nF ce amic capaci o ha cu equencies o e 1.6 kHz. AC cu en s should no ha e a equency
o e 100 Hz so his alue will cu equencies o e 16 imes hei undamen al. In addi ion, he 1 kΩ
esis ance limi s he cu en alue ou pu ed by he senso s o 3.3 mA.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
45
Fo he eed o wa d con ol o he DC ol age sou ce o he in e e a ol age ansduce LV 25-P is
used o sense he DC inpu ol age alue [7]. This ol age ansduce , when ecei ing he nominal inpu
cu en om he p ima y ci cui o 10 mA will ou pu 25 mA h ough he seconda y winding [17].
Wi h a 25 mA signal sen o he con ol subsys em, i mus be adap ed o be an analogue ol age signal
om 0 V o 3.3 V. To make Vdc senso ou pu becomes a ol age signal a 133 Ω esis ance has been
placed in he ci cui and he ol age o he ADC is measu ed in he esis ance e minals, so he
maximum ol age d op in he esis ance will be:
𝑉=𝑅𝐼=133Ω∗0.025𝐴=3.325𝐴
(55)
This way, he ADC will be able o ead all he ol age in he ange om 0-25 mA in he seconda y o he
ol age ansduce , which co esponds o 10 mA in he p ima y ha , conside ing i comes om a 55
kΩ esis ance connec ed be ween DC powe sou ce and ea h i can measu e up o 550 V. This ci cui
will be sui able o he whole sys em as he maximum Vdc applied will be 300A.
Figu e 4.1.9: Ci cui o Vdc sensing ia ADC.
As i can be seen in Figu e 4.1.9, sensed signal comes om he ene gy p ocessing subsys em and i s
cu en lows h ough R12 gene a ing a ol age d op be ween he i s e minal o R12 and g ound.
Then his ol age d op is sensed by he MCU’s ADC co esponding o he SENSOR_V_IN en y.
Memo ia
52
4.2.2. Dis ibu ion o he ci cui s and PCB design
The dis ibu ion o he ci cui s has been hough aking in o accoun ha he mos impo an aces
a e he ones co esponding o he 6 PWM and hey can’ c oss loads o powe lines.
Figu e 4.2.3 shows he di e en ci cui s o componen s dis ibu ed along he PCB layou . I can be seen
ha he 6 PWM ou pu s om he MCU connec o s (da k blue) a e connec ed o he le el-shi e s
(pu ple) which swi ch he logic high alues om 3.3 V o 5 V.
Then, ou pu s o he le el-shi e s go h ough he 6 dead- ime ci cui s o each PWM (ligh yellow) ha
apply a dead ime o he ising edges o he PWM and hey a e la e co ec ed and il e ed by he
Schmi igge s (ligh g een). Then, signals a e bu e ed a he in e ed bu e s ci cui s (ligh blue) o
inally be ou pu ed in he connec o s (da k yellow). Uppe igh connec o s inpu and ou pu ol age
sou ce o all logic ci cui s o he boa d and he ol age senso in he ene gy p ocessing boa d.
Po en iome e s (da k g een) a e si ua ed in he le op and down co ne s o adjus ing e e ence
inpu s in he MCU and inally low-pass il e s (g ey) ea he cu en senso s signals ha come om
he connec o s.
Figu e 4.2.3: PCB layou ci cui s dis ibu ion.
This dis ibu ion o ci cui s allows o he six SVPWM ou pu s o be inpu ed om he MCU, ea ed by
he di e en condi ioning ci cui s and be ou pu ed h ough he boa d connec o s wi hou being
excessi ely c ossed by powe lines o o he analogic o digi al signals such as senso signals.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
53
Due o space limi a ions, connec o s ha e been dis ibu ed op and below he boa d o space
op imiza ion and o keep he ou pu PWM aces as sho as possible o a oid inc easing line
impedance, hence dis u bing he ou pu signal.
As seen in Figu e 4.2.4, he common +5 V powe line o all logic ci cui s has been aced almos in i s
o ali y in he bo om ace (blue) o he boa d o a oid i being nea he analogic and digi al signals and
possibly pe u bing hem.
Figu e 4.2.3: +5 V powe line in PCB layou .
To eed he di e en ci cui s loca ed in he op ace, ias we e used o b ing he powe line om one
laye o he o he , as i can be seen in Figu e 4.2.4 in which one o he Schmi igge s (IC2) is ed om
a ia ha anspo s +5 V line.
Figu e 4.2.4: IC2 Schmi igge ed om +5 V ne ia.
Memo ia
54
All ia holes used we e 0.3 mm diame e d ill holes o espec and p o ide ma gin om he
manu ac u e ’s es ic ion in sec ion 4.2.1. All ias a e a leas 0.7 mm diame e which esul s in a 0.2
mm minimum spacing be ween hole and end o he ia, espec ing he es ic ion o 0.1 mm minimum
alue and 0.15 mm ecommended alue.
Minimum ace wid hs a e 0.5 mm and ace- o- ace dis ances placed in he boa d a e a leas 0.6
mm, clea ly espec ing 0.1 mm limi and ensu ing less line impedance. Clea example o his shown in
Figu e 4.2.5 a e lines o MCU 3.3 V PWM ou pu co esponding o ansis o s Q1 and Q3, which a e
0.5 mm wid h each and ha e a 0.6 mm spacing.
Figu e 4.2.5: Minimum ace wid h and spacing in PCB layou .
All he di e en ci cui s and componen s sha e he same e e ence 0 V poin , co esponding o he
g ound o he ol age sou ce, his ne in he PCB layou is no ed as Ea h. All ci cui s mus be connec ed
o his same g ound o he cu en o low h ough hem and e u n o he powe sou ce.
The p oblem wi h he GND ne is ha loads o lines should be aced o all poin s o he boa d and i
would be a mess o no c oss hem wi h o he ne aces. Fo his pu pose and also ying o a oid high
line impedances, a mass plane o g ound plane is designed all o e he wo laye s o he PCB. This way,
e e y space no illed wi h any ace o ia co esponding o o he ne s, is connec ed o he GND ne .
Figu e 4.2.6 shows he PCB layou wi h he Ea h ne mass plane highligh ed o show he design o i .
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
55
Figu e 4.2.6: Ea h ne , mass plane designed in he PCB.
The clea ance, minimum spacing be ween mass plane and o he ne s’ aces o ias, is 0.3 mm
espec ing he manu ac u e ’s es ic ions. This design allows o he cu en o ha e a big pa h (low
impedance) o i o e u n o he nega i e pole o he ol age sou ce, and also sa ed ime and e o
in he PCB design.
Taking a look in o he di e en componen s powe ed a +5 V, mos o all o hem a e ed he ol age
om a capaci o il e ing he ol age and main aining i cons an . This capaci o o capaci o s mus be
connec ed be ween +5 V and Ea h, and si ua ed nea he +5 V and GND pins o he di e en
componen s.
Some o he componen s don’ ha e hei +5 V and GND pins nea o a e sepa a ed by ano he ne ’s
ace, which doesn’ allow o he GND o he capaci o s o be nea he GND o he componen . In
Figu e 4.2.7 i is shown how his p oblem has been sol ed o IC2 placing a ia ha allows o he
cu en o low ou o he componen h ough he capaci o GND, making su e elec ons a e lowing
co ec ly h ough hei pa h and a oiding noise in he sou ce.
Memo ia
56
Figu e 4.2.7: Ea h ia o IC2.
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57
4.2.3. Fab ica ion and componen solde ing
Once he PCB is ab ica ed by he manu ac u e , including aces, ias and insula ion es ing o all he
boa d, all he componen s o he boa d ha e o be placed and welded in hei speci ic posi ion and
pads o he sys em o wo k co ec ly and pe o m all i s ea u es.
All componen s a e inned manually wi h a welding ool, in and wi h he help o lux o ensu e he in
is in con ac wi h he coppe pads o he boa d and he pins and pads o e e y componen . As illus a ed
in Figu e 4.2.8, i s he MCU su ace-moun ed connec o s we e inned o check he co ec spacing
and design o he boa d, he PCB is held in o de o ease he solde ing wo k.
Figu e 4.2.8: PCB wi h jus wo connec o s inned.
Almos all componen s o he boa d a e su ace-moun ed, which allows o he connec ion o be made
in jus one o he laye s o he PCB, excep o he e e ence se ing po en iome e s which a e h ough-
hole componen s ha a e connec ed o bo h laye s.
In Figu e 4.2.9 i can be seen he PCB wi h all componen s hand- inned excep o he inpu /ou pu
connec o s o he PCB, bu wi h he MCU connec o s placed.
Memo ia
58
Figu e 4.2.9: PCB wi h jus all componen s inned excep o I/O connec o s.
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59
5. So wa e
The implemen a ion o he SVPWM algo i hm in he MCU is a c i ical pa o he p ojec , as i se s he
base o he sys em’s unc ionali y and pe o mance. This chap e p o ides a comp ehensi e e iew o
he so wa e design and p og amming, ocusing on i s in eg a ion wi hin he in e e con ol sys em.
The STM32F767ZI is p og ammed using STM32CubeIDE ool, which suppo s C de elopmen . The
p og amming p ocess in ol es w i ing code, compiling i in o a bina y ile, and lashing i on o he MCU
ia SWD (Se ial Wi e Debug) in e ace, using he ST-Link debugge /p og amme .
Figu e 5.0.1 shows he block diag am ha explains he so wa e ope a ion and implemen ed SVPWM
algo i hm di ided in he di e en sec ions o he p og am. Fi s , he analog- o-digi al con e ed signals
a e used as inpu s o sys em key signals such as e e ence ol age (V*), e e ence equency ( *) and
DC bus ol age (VDC).
Using he inpu s om he ADC equi ed o SVPWM pa ame e s, he p og am calcula es he ol age
ec o componen s ( α*, β*) in he αβ plane. This p ocess is execu ed in a ime 2 (TIM2) in e up ion
Mo eo e , he angle (θ) is depic ed om he ADC inpu s, and i is la e used o sec o in e p e a ion,
de ining which sec o (1 o 6) is he ol age ec o in SVPWM algo i hm. This sec o will de e mine
which swi ching s a es will be ac i e. Based on he sec o , he algo i hm calcula es he swi ching imes
(Ti, Ti+1) o he ac i e ec o s, hence de e mining how long each swi ching s a e is applied du ing he
PWM cycle. Then, he swi ching imes a e con e ed in o PWM du y cycles (TQ1, TQ3, TQ5), all his is
pe o med in he main loop o he p og am.
Finally, du y-cycles a e applied in o m o clock icks (NQ1, NQ3, NQ5) in he ime 1 (TIM1) egis e s ha
will ou pu hem in o m o PWM signals, oge he wi h hei complemen a y channels (NQ2, NQ4, NQ6).
This ac ualiza ion o he TIM1 egis e s is also pe o med in he TIM2 in e up ion.
Memo ia
60
Figu e 5.0.1: SVPWM p og ammed algo i hm block diag am.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
61
5.1. Main code
The main code o p og am main.c is whe e he SVPWM algo i hm is execu ed, by calcula ing e e ence
ol age ec o and angle, selec ing he sec o o he SVPWM in which he ec o is o apply he co ec
swi ching s a es.
Then, imes o he applica ion o e e y ec o a e calcula ed o compu e he du y cycle o he PWM
o e e y ansis o , inally hese du y cycles a e ou pu ed o he TIM1 egis e s in cha ge i gene a ing
he PWM signals.
This main p og am can be sepa a ed in wo di e en pa s, he main loop in cha ge o he calcula ions
and he in e up ion ha upda es he di e en inpu and ou pu alues.
5.1.1. Main loop: Opening and closing imes calcula ion
The main loop is he pa o he main p og am whe e, depending on he inpu ed alues, he SVPWM
sec o is selec ed (1 o 6), o decide which ol age ec o s a e used and calcula e he imes in which
hey a e applica ed inside he PWM pe iod (Ti, Ti+1). Finally, du y cycles o each ansis o ’s PWM (TQ1,
TQ3, TQ5) a e compu ed om hese imes.
Figu e 5.1.1 shows how his p ocess is done o sec o 1, be ween angles 0 and π/3, calcula ing T1, T2,
T0 and he h ee du y cycles (TQ1, TQ3, TQ5), which a e compa ed o he minimum swi ching ime ha
he ansis o s ha e (Tmin). The sec o selec ion is done wi h an IF ins uc ion, and he calcula ions o
each IF o sec o a e inside a main loop WHILE(1), which is epea ed o e e .
Figu e 5.1.1: Main loop, i s sec o (IF).
Memo ia
68
5.2.2. Analog- o-digi al con e e s (ADC)
To p og am he ADCs used o inpu in o ma ion in he p og am, a simila p ocedu e has been ca ied
in o de o con igu e hem.
Six ADC channels ha e been used o he h ee AC cu en measu emen , ol age and equency
e e ence alues po en iome e s and one o DC ol age measu emen .
The p ocedu e ollowed o p og amming he ADC is he ollowing:
Fi s , all GPIO and ADC clocks a e enabled using he Rese and Clock Con ol (RCC), hen GPIO pins used
(PA2, PA3, PB0, PC2, PC3, PF9) a e con igu ed in analog mode. When hese a e enabled, i is necessa y
o con igu e hem using he sequence egis e s (SQR), se ing he sampling ime o each channel and
hen con igu ing he ADC p e-scale and esolu ion (12-bi ) in he common con ol egis e (CCR).
Finally, he con igu a ion o he di e en ADC channels is done, con igu ing hei con e sion mode in
he s a us egis e (SR) o scan mode o e e y ADC o be able o check he alues in di e en channels.
The las s ep is o ini ialize he ADC con e sion wi h he con ol egis e 2 (CR2) o se he channels o
a wo king mode.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
69
6. Tes ing and alida ion o he in e e
This hesis has e iewed in he p e ious chap e s heo e ical concep s abou h ee-phase in e e
con ol, he design and ab ica ion o he elec ical ci cui o he con ol sys em and he de elopmen
o he so wa e implemen a ion o he SVPWM algo i hm o he in e e con ol.
This chap e will now show he esul s ob ained when es ing he de eloped in e e con ol sys em
unde di e en ci cums ances. Fi s , he ope a ion o he sys em alone will be es ed, ocusing in he
di e en PWM ou pu s depending on he e e ence alues inpu ed o he sys em and he signal
ea men and condi ioning pe o med in he di e en sys em’s ci cui s.
The goal o he i s pa is o check i he ou pu s o he con ol sys em ha e he expec ed shape and
unc ionali ies. A e ha , he con ol sys em is inco po a ed o he whole h ee-phase in e e
de eloped along he ene gy p ocessing sys em de eloped in pa allel [7]. These las es s will ha e he
objec i e o demons a ing bo h he sys em’s pe o mance in a eal applica ion and how he con ol
a ec s he ou pu unde load condi ions.
One hing o conside is, du ing he es s, he ADC p og amming is no ully de eloped and
implemen ed, so he e e ence alues o VDC, V* and * a e manually se o he sys em by so wa e.
6.1. SVPWM ou pu es ing
As men ioned abo e, he i s es s pe o med o he sys em a e o check i s ope a ion s and alone,
es ing i he e e ence alues change a ec s he ou pu and o e i y all he signal ea men is
pe o med co ec ly by he di e en ci cui s in eg a ed in he con ol boa d de eloped.
Fi s , he PWM ou pu s om he STM32F767ZI a e measu ed unde di e en inpu e e ence alues
o ampli ude and equency, he PWM ou pu and il e ed ou pu ( undamen al sinusoidal alue) a e
cap u ed o check ha he di e en unc ionali ies o he con ol algo i hm a e wo king.
Then, he six di e en PWM ou pu s condi ioned o he op o-d i e s cha ac e is ics (5 V, il e ing) and
ansis o s necessi ies (dead- ime) a e cap u ed, he objec i e o hese measu es is o check he co ec
design, manu ac u e, moun ing and ope a ion o all he di e en ci cui s ha comp ehend he con ol
sys em.
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70
6.1.1. MCU PWM ou pu (3.3 V)
As al eady men ioned, i s ly he MCU PWM ou pu s a e measu ed, checking he algo i hm
pe o mance when di e en inpu e e ence alues a e applied. By measu ing he ou pu in he pins
o he MCU, and also applying an RC il e o be able o obse e he undamen al sinusoidal wa e ha
is o be eplied by he SVPWM he di e en cha ac e is ics can be obse ed when he e e ence is
changed.
The RC il e applied is a low-pass il e wi h a cu -o equency lowe han he PWM equency so he
pulses o he digi al signal a e no obse ed bu he undamen al wa e o be eplica ed by he signal is
obse ed. The il e was designed o cu -o app oxima ely a one en h o he PWM equency:
𝑓𝑅𝐶 =𝑓𝑃𝑊𝑀
10 =15.625𝑘𝐻𝑧
10 =1.562𝑘𝐻𝑧
(56)
To choose he R and C alues o he il e , i s he esis ance alue is selec ed wi h a high enough alue
no o consume a big cu en o he 3.3 V o he ou pu , hen in he low-pass RC il e equa ion is
sol ed o he C alue.
𝐶= 1
2𝜋𝑓𝑅𝐶𝑅
(57)
Common componen s alues o 4.7 kΩ and 22 nF a e selec ed o make a low-pass il e o 1.539 kHz.
Figu e 6.1.1 shows STM32F767ZI wi h ou pu signals connec ed o he RC il e s moun ed in he
p o oboa d o il e SVPWM ou pu s.
Figu e 6.1.2: STM32F767ZI and RC il e s connec ed.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
71
In Figu e 6.1.2 he ou pu o he PWM which con ols Q5 op o-d i e (hence Q5 i sel ) ou o he MCU
is obse ed, wi h (blue) and wi hou ( ed) RC il e o obse e PWM ampli ude and sinusoidal
undamen al wa e cha ac e is ics. The e e ence alues used a e VDC=300 V, V* (line- o-line, peak
alue) = 230 V and *=50 Hz. So, he sys em is ope a ing o ou pu a 230 V peak alue sinusoidal ou pu
a 50 Hz wi h a 300 V DC sou ce.
Figu e 6.1.2: Q5 MCU PWM ou pu . 5 ms/di , 1V/di .
As obse ed in Figu e 6.1.2, he aw PWM ou pu ( ed) has an ampli ude o 3.3 V, and he il e ed signal
is a pseudo sinusoidal signal wi h a pe iod o 20 ms, which co esponds o a 50 Hz equency. This
measu e se es he pu pose o check he ac ual ou pu o he MCU and he equency o he
undamen al sinusoidal signal being gene a ed by he STMF767ZI SVPWM ou pu s.
The ollowing measu e done is he il e ed measu e o PWM ou pu s o Q3 and Q5 il e ed o check
he o se o he wo undamen al sinusoidal signals and hei ou pu equency. As shown in Figu e
6.1.3, bo h il e ed signals a e ou pu ed wi h hei undamen al sinusoidal componen s ha ing a 6.39
ms o se co esponding almos o a 120º o se in he 20 ms pe iod. In addi ion, hei peak- o-peak
alue is 1.5 V. The e e ence alues used a e VDC=300 V, V* (line- o-line, peak alue) = 100 V and *=50
Hz. So he sys em is ope a ing o ou pu a 100 V peak alue sinusoidal ou pu a 50 Hz wi h a 300 V DC
sou ce.
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72
Figu e 6.1.3: Q3 and Q5 MCU SVPWM il e ed ou pu . 10 ms/di , 1 V/di .
A e ha , he same measu e is done bu changing he e e ence equency o double he one used in
he es be o e, 100 Hz. In Figu e 6.1.4 he same wo signals a e cap u ed, bu he pe iod o he signals
is now 10 ms co esponding o he 100 Hz e e ence equency applied o he con ol sys em. The peak-
o-peak alue is 1.5 V. The e e ence alues used a e VDC=300 V, V* (line- o-line, peak alue) = 100 V
and *=100 Hz. So he sys em is ope a ing o ou pu a 100 V peak alue sinusoidal ou pu a 100 Hz
wi h a 300 V DC sou ce.
Figu e 6.1.4: Q3 and Q5 MCU SVPWM il e ed ou pu . 10 ms/di , 1 V/di .
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
73
Finally, a las es is pe o med measu ing hese wo signals, going back o he 50 Hz e e ence
equency alue and inc easing he e e ence peak ol age o 230 V. In Figu e6.1.5, he signals pe iod
is 20 ms again co esponding o he 50 Hz, he peak- o-peak alue is 2.7 V. The e e ence alues used
a e VDC=300 V, V* (line- o-line, peak alue) = 230 V and *=50 Hz. So he sys em is ope a ing o ou pu
a 100 V peak alue sinusoidal ou pu a 100 Hz wi h a 300 V DC sou ce.
Figu e 6.1.5: Q3 and Q5 MCU SVPWM il e ed ou pu . 10 ms/di , 1 V/di .
Table 6.1.1 shows compa a i e alues be ween he MCU ou pu signals depending on hei inpu
e e ence alues.
Table 6.1.1: Compa a i e alues be ween ou pu il e ed signals depending on e e ence alues.
VDC
VLL* (peak)
*
Vpeak
Vpeak/V1peak
/ 1
300 V
100 V
50 Hz
1.5 V
50 Hz
1
1
300 V
100 V
100 Hz
1.5 V
100 Hz
1
2
300 V
230 V
50 Hz
2.7 V
50 Hz
1.8
1
As illus a ed in Table 6.1.1, equency e e ence alue is di ec ly a ec ing he equency ou pu alue
being he same as he il e ed sinusoidal alue. Inpu e e ence ol age ampli ude is also a ec ing he
ampli ude o he il e ed signals, bu i s ela ion is no as di ec as wi h he equency. The ou pu
ol age o he sinusoidal il e ed signals is ela ed o he inpu e e ence alue, bu o see i he sys em
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74
is co ec ly egula ing he ol age, a measu e wi h he comple e in e e sys em is needed and i can
be ound in chap e 6.2.
6.1.2. Con ol sys em PWM ou pu (5 V)
A e checking he di e en ou pu s om he MCU, he 5 V co ec ed signals ou o he con ol sys em’s
PCB a e measu ed o ensu e co ec ope a ion o he sys em and he di e en ci cui s. Figu e 6.1.6
shows he whole con ol sys em wi h he STM32F767ZI connec ed o he PCB, and he sys em’s
ou pu s connec ed o he RC il e s moun ed.
Figu e 6.1.6: Con ol sys em moun ed and connec ed o he RC il e s.
In Figu e 6.1.7 i is obse ed how he ou pu PWM signal ha con ols he opening and closu e o he
Q1 ansis o is measu ed wi h and wi hou il e . The ou pu aw PWM has a 5 V ampli ude, and he
il e ed sinusoidal signal has a 20 ms pe iod and 4.01 V peak- o-peak alue. The e e ence alues used
a e VDC=300 V, V* (line- o-line, peak alue) = 230 V and *=50 Hz. So he sys em is ope a ing o ou pu
a 100 V peak alue sinusoidal ou pu a 100 Hz wi h a 300 V DC sou ce.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
75
Figu e 6.1.7: Q1 con ol sys em PWM non- il e ed (blue) and il e ed ( ed) ou pu . 20 ms/di , 2 V/di .
The signal ea men is in cha ge o he condi ioning o he PWM signal, inc easing he high logic alue
o he PWM o 5 V (3.5 V minimum), applying a dead ime and co ec ing he signal o make i an almos
pe ec squa e signal wi h a iable du y cycle. In Figu e 6.1.5 i is obse ed how he signal is inc eased
o 5 V main aining he same cha ac e is ics in he undamen al sinusoidal componen ( equency and
ampli ude a iabili y).
In Figu e 6.1.8, Q1 and Q2 ou pu 5 V signals a e obse ed wi h de ail on he ising/ alling edges, o
obse e he dead- ime ci cui pe o mance. In he es cap u ed in Figu e 6.1.6, dead- ime is adjus ed
o 1.5 μs, i is obse ed how be ween he alling edge o Q2 PWM ( ed) and he ising edge o Q1 PWM
(blue) he e’s a 1.58 μs o se , con i ming he co ec pe o mance o he dead- ime and condi ioning
ci cui s designed.
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76
Figu e 6.1.8: Q1 PWM (blue) and Q2 PWM ( ed) o se measu emen . 400 ns/di , 2.5 V/di .
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
77
6.2. Load condi ion alida ion
A e es ing he con ol sys em s and-alone, he whole h ee-phase in e e sys em is es ed along
wi h he ene gy p ocessing sys em de eloped in pa allel [7]. The whole sys em is wi ed and connec ed
o e e y powe sou ce necessa y o make i wo k.
Figu e 6.2.1 shows he comple e h ee-phase in e e sys em connec ed o he powe sou ce, he
con ol sys em in on is wi ed wi h he ene gy p ocessing sys em and he powe dis ibu ion boa d
(back). Vol age p obes a e connec ed o an RC il e and measu emen poin s in he ansis o s boa d
[7]. These ol age p obes a e connec ed o an oscilloscope ( igh ) used o cap u ing he signals. Ou pu
lines a e connec ed o a ans o me , which has a h ee-phase load connec ed in he seconda y coil.
Figu e 6.2.1: Full in e e sys em in es labo a o y.
The ans o me used has wo s a -connec ed windings, he cha ac e is ics o he windings a e
summed up in Table 6.2.1.
Table 6.2.1: T ans o me cha ac e is ics.
Winding
Nominal ol age
Nominal cu en
P ima y
400 V
1.6 A
Seconda y
58 V
9.8 A
Wi h he in e e connec ed in he p ima y, and h ee 200W iangle-connec ed loads o he seconda y
he in e e ou pu was measu ed in o de o check he co ec pe o mance o he con ol sys em and
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84
managemen o elec onic was e. Such no ms encou age p ope disposal and eco e y p ac ices o
minimize en i onmen al ha m.
The esou ces used in his p ojec , bo h ma e ial and ene gy, a e de ailed in he economic chap e .
These include he PCB componen s, solde ing de ices, and measu emen ools like oscilloscopes. The
sys em i sel is ene gy-e icien , consuming a maximum o only 2.11W du ing ope a ion. I has been
ho oughly es ed o 20 hou s o ensu e eliabili y while main aining low ene gy consump ion.
In conclusion, his p ojec has been de eloped wi h a s ong emphasis on sus ainabili y, om e hical
sou cing o ma e ials o ene gy-e icien ope a ion. While he e a e challenges in ecycling ce ain
ma e ials like FR4 PCBs, e o s ha e been made o use componen s esponsibly and minimize was e.
The p ojec ’s ocus on enewable ene gy and esou ce-conscious de elopmen unde sco es i s
con ibu ion o a mo e sus ainable u u e.
To calcula e he CO2 oo p in , i is necessa y o calcula e he equi alen emissions o he di e en
aspec s o he p ojec .
Acco ding o he Minis e io pa a la T ansición Ecológica (MITECO) [20], he equi alen emissions om
elec ici y consump ion a e 0.166 kg o CO₂ pe kWh.
A compu e was u ilized h oughou his p ojec o ca y ou he necessa y asks. The equi alen
emissions p oduced we e es ima ed based on 600 hou s o ope a ion du ing he p ojec and a powe
consump ion o 58 W by he compu e .
𝐶𝑂2𝑐𝑜𝑚𝑝𝑢𝑡𝑒𝑟 =600ℎ∗58𝑊∗0.166𝑘𝑔𝐶𝑂2
1𝑊ℎ =5.7 𝑘𝑔𝐶𝑂2
(58)
In addi ion, he PCB was anspo ed om Hong Kong o Ba celona by plane. Es ima ing a 0.2 kg o he
package, a lying dis ance o 10301 km and a 0.6 kgCO2/ ·km ac o [21].
𝐶𝑂2𝑃𝐶𝐵=10300𝑘𝑚·0.0002𝑡·0.6𝑘𝑔𝐶𝑂2
1𝑡·𝑘𝑚 =1.24 𝑘𝑔𝐶𝑂2
(59)
The sys em’s consump ion is abou 2.11W, aking in o accoun i was used o 20 H o es ing, i
consumed:
𝐶𝑂2𝑇𝑒𝑠𝑡 =20ℎ∗2.11𝑊∗0.166𝑘𝑔𝐶𝑂2
1𝑊ℎ =0.007 𝑘𝑔𝐶𝑂2
(60)
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
85
8.2. Social impac
The de elopmen o a h ee-phase in e e con ol sys em has b ough many bene i s o di e en
people and o ganiza ions. I has also made a posi i e impac on impo an p ojec s ela ed o
enewable ene gy and sus ainable echnology. This p ojec shows how enginee ing can help sol e
p oblems, c ea e new ools, and con ibu e o a be e u u e.
Fi s , he mic oelec onics ins i u e o Ba celona now has an in e e o es hei chips and ansis o s.
This is e y impo an o hem because hei esea ch ocuses on designing and imp o ing
mic oelec onic de ices. Wi h he h ee-phase in e e , hey can connec hei chips and ansis o s o
a eal sys em and see how hey pe o m. This helps hem de elop be e echnology and push he
limi s o wha is possible. The in e e gi es hem a p ac ical ool o es hei ideas and imp o e hei
wo k.
Second, he uni e si y UPC now has an open-sou ce in e e o es mic og ids. Mic og ids a e small,
independen ene gy sys ems ha can use enewable ene gy like sola panels o wind u bines. By
ha ing an open-sou ce in e e , s uden s and esea che s a UPC can expe imen wi h new ideas o
managing ene gy and imp o ing mic og id pe o mance. This makes he uni e si y a leade in
enewable ene gy esea ch and educa ion. The open-sou ce design also allows o he people ou side
he uni e si y o use he in e e and lea n om i , c ea ing a wide impac .
Fo he au ho o his hesis, wo king on his p ojec has been a jou ney o pe sonal and p o essional
g ow h. Designing a complex sys em like a h ee-phase in e e equi ed lea ning new skills, sol ing
p oblems, and being e y c ea i e. I also equi ed using eamwo k and communica ion o make su e
e e y hing wo ked oge he . This expe ience has made he au ho a be e enginee and p epa ed
hem o u u e challenges in hei ca ee . I has been a big s ep o wa d in hei educa ion and hei
li e.
All he ma e ials and componen s used in his p ojec we e pu chased om dis ibu o s ha ollow
e hical codes. This means ha he companies p o iding he ma e ials ca e abou doing business
esponsibly. They make su e hei wo ke s a e ea ed ai ly and ha hey espec he en i onmen .
This was an impo an decision o he p ojec because i e lec s he alues o he people in ol ed.
Choosing e hical supplie s shows a commi men o doing wha is igh , no jus wha is easy.
Th ee-phase in e e sys ems also play a e y impo an ole in enewable ene gy sys ems and g ids.
Renewable ene gy sou ces like sola panels and wind u bines p oduce elec ici y in a way ha is no
always s eady. In e e s help con e his elec ici y in o a s able o m ha can be used in homes,
ac o ies, o sen o he g id. This makes enewable ene gy mo e eliable and easie o use. By
Memo ia
86
imp o ing in e e echnology, we can make enewable ene gy sys ems mo e e icien and accessible
o mo e people. This helps educe pollu ion and suppo s he ansi ion o cleane ene gy o e e yone.
In summa y, he de elopmen o he h ee-phase in e e con ol sys em has p o ided he
mic oelec onics ins i u e wi h a es ing ool, he uni e si y wi h an open-sou ce pla o m o
inno a ion, and he au ho wi h aluable pe sonal and p o essional g ow h. The p ojec also showed
he impo ance o using e hical ma e ials and highligh ed he ole o in e e echnology in enewable
ene gy. I is a g ea example o how enginee ing can make a posi i e di e ence in many a eas.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
87
9. Conclusions
The de elopmen o a obus h ee-phase in e e con ol sys em o mic og id expe imen a ion and
elec ic ac ion applica ions has been a p ojec ha has e iewed all he aspec s o de eloping a powe
elec onics con ol sys em o hese cha ac e is ics. This hesis has explained he design,
implemen a ion, and alida ion o a comp ehensi e con ol subsys em designed o labo a o y use.
The p ojec adop ed a holis ic app oach, explaining heo e ical analysis, ha dwa e design, so wa e
implemen a ion, and igo ous es ing, o deli e a e sa ile and high-pe o mance in e e .
The heo e ical in oduc ion p o ided a basis o unde s and he p inciples o DC-AC con e sion, h ee-
phase in e e a chi ec u es, and ad anced modula ion echniques like Space Vec o Pulse Wid h
Modula ion (SVPWM). The esea ch explo ed e icien p ac ices in con ol algo i hms, ocusing on
minimizing ha monic dis o ion, op imizing swi ching sequences, and ensu ing e icien ene gy
con e sion. These aspec s we e c ucial o he design o a obus and adap able con ol subsys em,
being able o ou pu he con ol signals o he ansis o s o he h ee-phase in e e ensu ing a good
con ol and pe o mance o he con e e .
In e ms o ha dwa e design, he p ojec achie ed signi ican p og ess by ca e ully selec ing and
in eg a ing essen ial componen s such as mic ocon olle s, le el shi e s, dead- ime ci cui s, and signal
condi ioning elemen s. Complex elec ical ci cui s ha e been designed o ea and adap he SVPWM
ou pu signals om he mic ocon olle and make hem compa ible o wo k wi h he op o-d i e s o
which hey we e sen o con ol.
A whole schema ic has been designed in o de o ul il all he di e en unc ionali ies o he sys em,
making i able o ecei e di e en inpu s om o he sys ems o human in e aces such as
po en iome e s o egula e di e en aspec s and c i ical elemen s in he con ol algo i hm and sys em
The PCB layou was me iculously c a ed o ensu e low noise le els, e ec i e signal ansmission, and
scalabili y o u u e enhancemen s. The sys em’s modula design suppo s upg ades and adap abili y
o di e se expe imen al se ups, ein o cing i s u ili y in esea ch and de elopmen con ex s. The PCB
was ca e ully designed o ensu e e icien dis ibu ion and main aining low impedance lines ha could
a ec he signals o ms.
All he manu ac u ing and moun ing p ocess o he PCB was shown as he di e en pa s o he sys em
we e de eloped, ocusing on componen solde ing and he assembly o he di e en pa s o he
sys em.
The so wa e implemen a ion elied on STM32CubeIDE, showing he lexibili y and p ecision o
mode n mic ocon olle pla o ms. Real- ime p ocessing o eedback signals, including ol age and
Memo ia
88
cu en measu emen s, enabled adap i e con ol and ensu ed sys em eliabili y unde a ying load
condi ions. Pe iphe als p og amming and SVPWM algo i hm we e designed o op imize ene gy
deli e y and educe powe losses, demons a ing he p ojec 's po en ial o scalable indus ial
applica ions and ensu ing good pe o mance o he labo a o y applica ions i was designed o .
The so wa e was designed hinking on adap abili y and a po en ial u u e imp o emen in e ms o
implemen a ion o di e en inpu s, possibili y o adding eedback con ol o he di e en elec ical
ou pu s such as AC cu en s, making i adap able o add a mo o con ol algo i hm such as Field
O ien ed Con ol o Di ec To que Con ol.
Tes ing and alida ion con i med he in e e 's abili y o mee p ede ined pe o mance s anda ds,
including s able PWM gene a ion, accu a e ol age con ol, and eliable ope a ion unde load
condi ions. These esul s unde sco e he obus ness o he design and i s eadiness o in eg a ion in o
expe imen al mic og id se ups and elec ic ac ion sys ems.
Di e en es s we e pe o med o he sys em, ones wi h he s and-alone ope a ion, checking MCU
ou pu s in on o di e en e e ence inpu s, showcasing he good design o he so wa e and con ol
algo i hm. Tes s we e pe o med whe e ou pu wa e o ms om he PCB we e obse ed o ensu e
co ec unc ionali y o he di e en ci cui s o he PCB and a co ec manu ac u e and moun ing
p ocess. In addi ion, measu es we e aken o check he co ec ope a ion o he dead- ime ci cui
designed c ucial o sa e y and good ope a ion o he h ee-phase in e e .
Finally, a es unde load condi ions was pe o med wi h he whole h ee-phase in e e sys em, which
showed no only ha he di e en de eloped sys ems could wo k oge he as a obus uni bu ha
he con ol sys em was pe ec ly designed o mee he o iginal expec a ions, measu ing ou pu
wa e o ms om he in e e exac ly as hey we e inpu ed as a e e ence in he con ol sys em.
To conclude, his p ojec has eached all he o iginal expec a ions o he de elopmen o a con ol o
h ee-phase in e e sys em o labo a o y uses, adap able o many ci cums ances, loads, componen s
and di e en con ol s a egies ha a e o be applied in he u u e o he de eloped sys em.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
89
10. Re e ences
[1] SÉGUIER, Guy; LABRIQUE, F ancis. Powe elec onic con e e s: DC-AC con e sion. Sp inge Science
& Business Media, 2012.
[2] GÓMEZ GÓMEZ, Alexis Anselmo; Diseño y desa ollo de un in e so de co ien e i ásico de 5 kW
conec ado a la ed. Uni e sidad de Can ab ia, 2021.
[3] MEERSMAN, Ba ; O he s. O e iew o h ee-phase in e e opologies o dis ibu ed gene a ion
pu poses. Ghen Uni e si y Academic Bibliog aphy, 2010.
[4] F. Benchabane, A. Ti aouine, O. Bennis, K. Yahia, and D. Taibi, "Di ec ield o ien ed con ol scheme
o space ec o modula ed AC/DC/AC con e e ed induc ion mo o ," F on ie s in Ene gy, Jun. 2012.
[5] R. G assmann, A. Senyk, and J. Bu gne -Kah s, "Cla ke T ans o m – A Fundamen al Tool o
Con inuum Robo ics," p esen ed a he IEEE/RSJ In e na ional Con e ence on In elligen Robo s and
Sys ems (IROS), Sep. 2024. [6] ALTINTAS, Gokhan; KOCABAS, D. A. Ex ended O e modula ion
Ope a ion o Space Vec o PWM o T ac ion Mo o Con ol a Low Swi ching F equency. Janua y 2022,
IEEE.
[7] AROCA, Ad ià. De elopmen o a obus h ee-phase in e e o mic og id (mg) and elec ic
ac ion expe imen a ion ene gy p ocessing subsys em. Janua y 2025, Uni e si a Poli ècnica de
Ca alunya.
[8] SPEED's Elec ic Mo o s, TJE Mille , Uni e si y o Glasgow, 2002
[9] N. Mohan, Ad anced Elec ic D i es: Analysis, Con ol, and Modeling Using MATLAB/Simulink.
Hoboken, NJ, USA: Wiley, 2014.
[10] G. G idling and B. Weiss, In oduc ion o Mic ocon olle s. Vienna, Aus ia: Vienna Uni e si y o
Technology, Ins i u e o Compu e Enginee ing, Embedded Compu ing Sys ems G oup, Feb. 2007
[11] M. Yousse , F. Aloui, C. Boubah i, and S. Fe ni, "Simula ion and Design o a Single Phase In e e
wi h Digi al PWM Issued by an A duino Boa d," In e na ional Jou nal o Enginee ing Resea ch and
Technology, Aug. 2020
[12] D. Fewson, In oduc ion o Powe Elec onics. Ox o d, U.K.: Bu e wo h-Heinemann, Sep. 1999
[13] Q. Kabashi, M. Limani, N. Caka, and M. Zabeli, "The impac o sampling equency and ampli ude
modula ion index on low o de ha monics in a 3-phase SV-PWM ol age sou ce in e e ," Tu kish
Jou nal o Elec ical Enginee ing and Compu e Sciences, Jan. 2017.
Memo ia
90
[14] Texas Ins umen s, "SN74HCT125: Quad uple Bus Bu e Ga es Wi h 3-S a e Ou pu s," Da ashee ,
Oc . 2022. [Online]. A ailable: h ps://www. i.com/li /ds/symlink/sn74hc 125.pd
[15] Nexpe ia, "HEF40106B-Q100: In e ing Schmi igge ," Da ashee , [Online]. A ailable:
h ps://asse s.nexpe ia.com/documen s/da a-shee /HEF40106B_Q100.pd .
[16] Onsemi, "MC14049UB: Hex In e e Bu e ," Da ashee , [Online]. A ailable:
h ps://www.onsemi.com/pd /da ashee /mc14049ub-d.pd .
[17] LEM, "Vol age T ansduce LV 25-P," Da ashee , [Online]. A ailable:
h ps://www.lem.com/si es/de aul / iles/p oduc s_da ashee s/l _25-p_sp5_ 12.pd .
[18] STMic oelec onics, "STM32F765BI: A m Co ex-M7 32-bi MCU," Da ashee , Re . 9, Jan. 2021.
[Online]. A ailable: h ps://www.s .com/ esou ce/en/da ashee /s m32 765bi.pd .
[19] STMic oelec onics, STM32F75xxx and STM32F74xxx ad anced ARM-based 32-bi MCUs e e ence
manual, RM0385, Re . 7, Dec. 2022. [Online]. A ailable:
h ps://www.s .com/ esou ce/en/ e e ence_manual/ m0385-s m32 75xxx-and-s m32 74xxx-
ad anced-a mbased-32bi -mcus-s mic oelec onics.pd .
[20] Minis e io pa a la T ansición Ecológica y el Re o Demog á ico (MITECO), "Cálculo de emisiones."
[Online]. A ailable: h ps://www.mi eco.gob.es/con en /dam/mi eco/es/ceneam/p og amas-de-
educacion-ambien al/hoga es- e des/2011%20-%2016%20Calculo%20de%20emisiones%20
HV2011_ cm30-171463.pd
[21] In e na ional Ai T anspo Associa ion (IATA), "En i onmen al sus ainabili y." [Online]. A ailable:
h ps://www.ia a.o g.
[22] Sunye de Ga izabal, Ignacio. Con ol's Op imiza ion o a PMAC Mo o o Mo os uden
Compe i ion. May 2019. Uni e si a Poli ècnica de Ca alunya.
[23] JORDÀ I SANUY, Xa ie . Concep ion e Réalisa ion d’une Commande Economique de Couple d’une
Machine Asynch one pou la T ac ion Elec ique. Uni e si a Au ònoma de Ba celona, 1995.
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
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De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
93
Annex A: Elec ical scheme (KiCad)
Annexos
100
Tq1 = T0/2;
Tq3 = T4+(T0/2);
Tq5 = T4+T5+(T0/2);
Tq1 = LT(Tq1 , Tmin) ? 0 : Tq1;
Tq3 = LT(Tq3 , Tmin) ? 0 : Tq3;
Tq5 = LT(Tq5 , Tmin) ? 0 : Tq5;
}
else i ((GT(angle,PI*4/3) || EQ(angle,PI*4/3)) &&
LT(angle, PI*5/3))// (GT(angle,PI*4/3) || EQ(angle,PI*4/3)) &&
LT(angle, PI*5/3)
{
//Calcula ions o he applica ion imes o he
non-null ec o s
T5 =SQRT3/(2* ba )*(-SQRT3* al a- be a)*Tcom;
T6 = SQRT3/(2* ba )*(SQRT3* al a- be a)*Tcom;
//Calcula ions o he opening imes o he
ansis o s
T0 = Tcom-T5-T6;
Tq1 = T6+(T0/2);
Tq3 = T0/2;
Tq5 = T5+T6+(T0/2);
Tq1 = LT(Tq1 , Tmin) ? 0 : Tq1;
Tq3 = LT(Tq3 , Tmin) ? 0 : Tq3;
Tq5 = LT(Tq5 , Tmin) ? 0 : Tq5;
}
else{
//Calcula ions o he applica ion imes o he
non-null ec o s
T6 = SQRT3/( ba )*(- be a)*Tcom;
T1 =SQRT3/(2* ba )*(SQRT3* al a+ be a)*Tcom;
//Calcula ions o he opening imes o he
ansis o s
T0 = Tcom-T6-T1;
Tq1 = T1+T6+(T0/2);
Tq3 = T0/2;
Tq5 = T6+(T0/2);
Tq1 = LT(Tq1 , Tmin) ? 0 : Tq1;
Tq3 = LT(Tq3 , Tmin) ? 0 : Tq3;
Tq5 = LT(Tq5 , Tmin) ? 0 : Tq5;
}
// Nq1 = (Tq1/Tcom)*Ncom;
// Nq3 = (Tq3/Tcom)*Ncom;
// Nq5 = (Tq5/Tcom)*Ncom;
}
}
s a ic oid im2_callback( oid){
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
101
//Du y cycle assigna ion o co esponding PWM
Nq1 = 256 - (Tq1/Tcom)*Ncom;
Nq3 = 256 - (Tq3/Tcom)*Ncom;
Nq5 = 256 - (Tq5/Tcom)*Ncom;
i (++coun e > 127)coun e =0;
TIM1->CCR1 = Nq1;
TIM1->CCR2 = Nq3;
TIM1->CCR3 = Nq5;
//Speed disc e e in eg a ion o ob ain cu en angle, 0( n)=0( n-
1)+w*d
angle = angle+w*Tcom;
//i (angle>= PI2) angle =0;
angle = mod (angle, PI2); // his no malizes he angle be ween 0
and 2PI co ec ly (ci cula ly)
//dq o al a be a wi h ol age and angle
//The index o he look up ables is compu ed om he calcula ion
o he angle and escala ed wi h N o /PI2
al a = cos_ able[(in )(angle*N o /PI2)]* ol age;
be a = sin_ able[(in )(angle*N o /PI2)]* ol age;
}
oid TIM2_IRQHandle ( oid){
//Clea he upda e in e up lag
TIM2->SR &= ~SR_UIF;
//Execu e con ol o de s
im2_callback();
}
Annexos
102
TIMER_CONFIG.C
#include "s m32 767xx.h"
#de ine DIER_UIE (1U<<0)
oid im1_PWM_ou pu ( oid){
//Con ig pins o al e na e unc ion as TIM1 channels//
//Clock access o AHB1 (GPIOA, GPIOE)
RCC->AHB1ENR |= (1U<<0);
RCC->AHB1ENR |= (1U<<4);
//PA8 TIM1/1 Q1 AF
GPIOA->MODER &=~ (1U<<16);
GPIOA->MODER |= (1U<<17);
//PA9 TIM1/2 Q3 AF
GPIOA->MODER &=~ (1U<<18);
GPIOA->MODER |= (1U<<19);
//PA10 TIM1/3 Q5 AF
GPIOA->MODER &=~ (1U<<20);
GPIOA->MODER |= (1U<<21);
//PE14 TIM1/4 Q7 AF
GPIOE->MODER &=~ (1U<<28);
GPIOE->MODER |= (1U<<29);
//PA7 TIM1/1N Q2 AF
GPIOA->MODER &=~ (1U<<14);
GPIOA->MODER |= (1U<<15);
//PE10 TIM1/2N Q4 AF
GPIOE->MODER &=~ (1U<<20);
GPIOE->MODER |= (1U<<21);
//PE12 TIM1/3N Q6 AF
GPIOE->MODER &=~ (1U<<24);
GPIOE->MODER |= (1U<<25);
//Se pins o co esponding AF ype (TIMX_CHX(N))--> hey a e
all AF1
//PA8 --> AFR8 --> AF1
GPIOA->AFR[1] |= (1U<<0);
GPIOA->AFR[1] &=~ (1U<<1);
GPIOA->AFR[1] &=~ (1U<<2);
GPIOA->AFR[1] &=~ (1U<<3);
//PA9 --> AFR9 --> AF1
GPIOA->AFR[1] |= (1U<<4);
GPIOA->AFR[1] &=~ (1U<<5);
GPIOA->AFR[1] &=~ (1U<<6);
GPIOA->AFR[1] &=~ (1U<<7);
//PA10 --> AFR10 --> AF1
GPIOA->AFR[1] |= (1U<<8);
GPIOA->AFR[1] &=~ (1U<<9);
GPIOA->AFR[1] &=~ (1U<<10);
GPIOA->AFR[1] &=~ (1U<<11);
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
103
//PE14 --> AFR14 --> AF1
GPIOE->AFR[1] |= (1U<<24);
GPIOE->AFR[1] &=~ (1U<<25);
GPIOE->AFR[1] &=~ (1U<<26);
GPIOE->AFR[1] &=~ (1U<<27);
//PA7 --> AFR7 --> AF1
GPIOA->AFR[0] |= (1U<<28);
GPIOA->AFR[0] &=~ (1U<<29);
GPIOA->AFR[0] &=~ (1U<<30);
GPIOA->AFR[0] &=~ (1U<<31);
//PE10 --> AFR10 --> AF1
GPIOE->AFR[1] |= (1U<<8);
GPIOE->AFR[1] &=~ (1U<<9);
GPIOE->AFR[1] &=~ (1U<<10);
GPIOE->AFR[1] &=~ (1U<<11);
//PE12 --> AFR12 --> AF1
GPIOE->AFR[1] |= (1U<<16);
GPIOE->AFR[1] &=~ (1U<<17);
GPIOE->AFR[1] &=~ (1U<<18);
GPIOE->AFR[1] &=~ (1U<<19);
//Clock access enable APB2 (TIM1)
RCC->APB2ENR |= (1U<<0);
//Se p e-scale alue
TIM1->PSC = 2 - 1; // 16.000.000 / 2 = 8.000.000 Hz
//Se au o- eload alue
TIM1->ARR = 256 - 1; // 8.000.000 / 256 = 31.250 Hz = 31.25
kH
TIM1->CCR1 = 255;
TIM1->CCR2 = 255;
TIM1->CCR3 = 255;
TIM1->CCR4 = 255;
//Enable cen e-aligned mode 1
TIM1->CR1 |= (1U<<5);
TIM1->CR1 &=~ (1U<<6);
//Enable MOE
TIM1->BDTR |= (1U<<15);
//Enable TIM1_CH1 ou pu compa e
TIM1->CCMR1 &=~(1U<<0);
TIM1->CCMR1 &=~(1U<<1);
//Enable TIM1_CH2 ou pu compa e
TIM1->CCMR1 &=~(1U<<8);
TIM1->CCMR1 &=~(1U<<9);
//Enable TIM1_CH3 ou pu compa e
TIM1->CCMR2 &=~(1U<<0);
TIM1->CCMR2 &=~(1U<<1);
//Enable TIM1_CH4 ou pu compa e
TIM1->CCMR2 &=~(1U<<8);
Annexos
104
TIM1->CCMR2 &=~(1U<<9);
//We se he Ou pu compa e mode o PWM Mode 2
//TIM1_CH1 Q1
TIM1->CCMR1 |= (1U<<5) | (1U<<6)|(1U<<4);
TIM1->CCMR1 &= ~(1U<<16);
//TIM1_CH2 Q3
TIM1->CCMR1 |= (1U<<12) | (1U<<13) | (1U<<14);
TIM1->CCMR1 &= ~(1U<<24);
//TIM1_CH3 Q5
TIM1->CCMR2 |= (1U<<5) | (1U<<6)|(1U<<4);
TIM1->CCMR2 &= ~(1U<<16);
//TIM1_CH4 Q7
TIM1->CCMR2 |= (1U<<12) | (1U<<13) | (1U<<14);
TIM1->CCMR2 &= ~(1U<<24);
//Cap u e/Compa e enable wo ks o bo h unc ions since hey
a e used wi h he same bi s
//We enable he cap u e/compa e channels
//CH1 (Q1) & CH1_N (Q2)
TIM1->CCER |= (1U<<0);
TIM1->CCER |= (1U<<2);
//CH2 (Q3) & CH2_N (Q4)
TIM1->CCER |= (1U<<4);
TIM1->CCER |= (1U<<6);
//CH3 (Q5) & CH3_N (Q6)
TIM1->CCER |= (1U<<8);
TIM1->CCER |= (1U<<10);
//CH4 (Q7)
TIM1->CCER |= (1U<<12);
//Clea coun e
TIM1->CNT = 0;
// Enable ime 1 as sla e, igge by Time 2
//Sla e mode selec ion, We can y ei he T igge mode (0110)
o Combined ese + igge mode (1000)
TIM1->SMCR |= (1U<<16); // Sla e mode selec ion: T igge Mode
( ese on ising edge)
TIM1->SMCR &= ~(1U<<0);
TIM1->SMCR &= ~(1U<<1);
TIM1->SMCR &= ~(1U<<2);
//TS, igge selec ion, 001 In e nal T igge 1 (ITR1), which
ollowing he able, co esponds o TIM2
TIM1->SMCR |= (1U<<4); // T igge selec ion: TI1FP1 (TI1 Edge
De ec o )
TIM1->SMCR &= ~(1U<<5);
TIM1->SMCR &= ~(1U<<6);
}
oid im2_in e up _ini ( oid){
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
105
//Enable clock access o TIM2
RCC->APB1ENR |= (1U<<0);
//Se p escale alue
TIM2->PSC = 4-1; // 16 000 000 Hz/ 4 = 4 000 000 Hz
//Se au o- eload alue
TIM2->ARR = 256 - 1; // 4 000 000/256 = 15625 Hz
//Clea coun e
TIM2->CNT = 0;
//Enable TIM in e up , con igu ing he in e up enable egis e
TIM2->DIER |= DIER_UIE;
//Enable TIM in e up in NVIC, TIM2_IRQn is equi alen o 28
NVIC_EnableIRQ(TIM2_IRQn);
//Mas e Mode selec ion o TIM2, Upda e, he upda e e en is
selec ed as igge ou pu
TIM2->CR2 |= (1U<<5);
TIM2->CR2 &= ~(1U<<4);
TIM2->CR2 &= ~(1U<<6);
}
Annexos
106
MAIN.H
#i nde MAIN_H_
#de ine MAIN_H_
#de ine EPSILON 1e-6
#de ine EQ(x, y) ( abs((x) - (y)) < EPSILON)
#de ine LT(x, y) (((x) - (y)) < -EPSILON)
#de ine GT(x, y) (((x) - (y)) > EPSILON)
#de ine SR_UIF (1U<<0)
//Cons an de ini ions
#de ine SQRT3 1.73205080757
#de ine PI 3.14159265358
#de ine PI2 6.283185307
#de ine VOLTAGE_STEP 0.01 // Inc emen o ol age o e e y
in e up ion
in coun e = 0;
in i = 0;
//Va iables de ini ion
//Con igu able a iables by he use , in he cu en p og am eq
and Tcom a e compu ed in main
loa eq;
in ol age_ll =230;
loa ol age = 230/SQRT3;
loa Tcom;
//Compu ed a iables ela ed o con igu able a iables
loa w;
//in angle=0;
loa angle = 0.0 ;
loa al a, be a;
//T ansis o commu a ion imes, pe iods, and in ege s
loa T1, T2, T3, T4, T5, T6, T0;
loa Tq1, Tq3, Tq5;
in Nq1, Nq3, Nq5;
in Ncom;
//Subdi isions o he SVPWM pe iod (powe o 2)
in N o = 256; //2^8 subdi isions, same as leng h o look up
ables
loa e , ba = 300, e = 50; //Measu ed alues, no in he
cu en e sion
//Minimum T IGBTs can handle ( ising / alling edges...)
loa Tmin = 0;
//Look-up ables o sin and cos o 256 alues (2^8)
cons loa sin_ able[256] = {
0.0000000000, 0.0245412285, 0.0490676743, 0.0735645636,
0.0980171403, 0.1224106752, 0.1467304745, 0.1709618888,
0.1950903220, 0.2191012402, 0.2429801799, 0.2667127575,
0.2902846773, 0.3136817404, 0.3368898534, 0.3598950365,
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
107
0.3826834324, 0.4052413140, 0.4275550934, 0.4496113297,
0.4713967368, 0.4928981922, 0.5141027442, 0.5349976199,
0.5555702330, 0.5758081914, 0.5956993045, 0.6152315906,
0.6343932842, 0.6531728430, 0.6715589548, 0.6895405447,
0.7071067812, 0.7242470830, 0.7409511254, 0.7572088465,
0.7730104534, 0.7883464276, 0.8032075315, 0.8175848132,
0.8314696123, 0.8448535652, 0.8577286100, 0.8700869911,
0.8819212643, 0.8932243012, 0.9039892931, 0.9142097557,
0.9238795325, 0.9329927988, 0.9415440652, 0.9495281806,
0.9569403357, 0.9637760658, 0.9700312532, 0.9757021300,
0.9807852804, 0.9852776424, 0.9891765100, 0.9924795346,
0.9951847267, 0.9972904567, 0.9987954562, 0.9996988187,
1.0000000000, 0.9996988187, 0.9987954562, 0.9972904567,
0.9951847267, 0.9924795346, 0.9891765100, 0.9852776424,
0.9807852804, 0.9757021300, 0.9700312532, 0.9637760658,
0.9569403357, 0.9495281806, 0.9415440652, 0.9329927988,
0.9238795325, 0.9142097557, 0.9039892931, 0.8932243012,
0.8819212643, 0.8700869911, 0.8577286100, 0.8448535652,
0.8314696123, 0.8175848132, 0.8032075315, 0.7883464276,
0.7730104534, 0.7572088465, 0.7409511254, 0.7242470830,
0.7071067812, 0.6895405447, 0.6715589548, 0.6531728430,
0.6343932842, 0.6152315906, 0.5956993045, 0.5758081914,
0.5555702330, 0.5349976199, 0.5141027442, 0.4928981922,
0.4713967368, 0.4496113297, 0.4275550934, 0.4052413140,
0.3826834324, 0.3598950365, 0.3368898534, 0.3136817404,
0.2902846773, 0.2667127575, 0.2429801799, 0.2191012402,
0.1950903220, 0.1709618888, 0.1467304745, 0.1224106752,
0.0980171403, 0.0735645636, 0.0490676743, 0.0245412285,
0.0000000000,-0.0245412285,-0.0490676743,-0.0735645636,
-0.0980171403,-0.1224106752,-0.1467304745,-0.1709618888,
-0.1950903220,-0.2191012402,-0.2429801799,-0.2667127575,
-0.2902846773,-0.3136817404,-0.3368898534,-0.3598950365,
-0.3826834324,-0.4052413140,-0.4275550934,-0.4496113297,
-0.4713967368,-0.4928981922,-0.5141027442,-0.5349976199,
-0.5555702330,-0.5758081914,-0.5956993045,-0.6152315906,
-0.6343932842,-0.6531728430,-0.6715589548,-0.6895405447,
-0.7071067812,-0.7242470830,-0.7409511254,-0.7572088465,
-0.7730104534,-0.7883464276,-0.8032075315,-0.8175848132,
-0.8314696123,-0.8448535652,-0.8577286100,-0.8700869911,
-0.8819212643,-0.8932243012,-0.9039892931,-0.9142097557,
-0.9238795325,-0.9329927988,-0.9415440652,-0.9495281806,
-0.9569403357,-0.9637760658,-0.9700312532,-0.9757021300,
-0.9807852804,-0.9852776424,-0.9891765100,-0.9924795346,
-0.9951847267,-0.9972904567,-0.9987954562,-0.9996988187,
-1.0000000000,-0.9996988187,-0.9987954562,-0.9972904567,
-0.9951847267,-0.9924795346,-0.9891765100,-0.9852776424,
-0.9807852804,-0.9757021300,-0.9700312532,-0.9637760658,
-0.9569403357,-0.9495281806,-0.9415440652,-0.9329927988,
-0.9238795325,-0.9142097557,-0.9039892931,-0.8932243012,
-0.8819212643,-0.8700869911,-0.8577286100,-0.8448535652,
-0.8314696123,-0.8175848132,-0.8032075315,-0.7883464276,
-0.7730104534,-0.7572088465,-0.7409511254,-0.7242470830,
Annexos
108
-0.7071067812,-0.6895405447,-0.6715589548,-0.6531728430,
-0.6343932842,-0.6152315906,-0.5956993045,-0.5758081914,
-0.5555702330,-0.5349976199,-0.5141027442,-0.4928981922,
-0.4713967368,-0.4496113297,-0.4275550934,-0.4052413140,
-0.3826834324,-0.3598950365,-0.3368898534,-0.3136817404,
-0.2902846773,-0.2667127575,-0.2429801799,-0.2191012402,
-0.1950903220,-0.1709618888,-0.1467304745,-0.1224106752,
-0.0980171403,-0.0735645636,-0.0490676743,-0.0245412285 };
cons loa cos_ able[256] = {
1.0000000000, 0.9996988187, 0.9987954562, 0.9972904567,
0.9951847267, 0.9924795346, 0.9891765100, 0.9852776424,
0.9807852804, 0.9757021300, 0.9700312532, 0.9637760658,
0.9569403357, 0.9495281806, 0.9415440652, 0.9329927988,
0.9238795325, 0.9142097557, 0.9039892931, 0.8932243012,
0.8819212643, 0.8700869911, 0.8577286100, 0.8448535652,
0.8314696123, 0.8175848132, 0.8032075315, 0.7883464276,
0.7730104534, 0.7572088465, 0.7409511254, 0.7242470830,
0.7071067812, 0.6895405447, 0.6715589548, 0.6531728430,
0.6343932842, 0.6152315906, 0.5956993045, 0.5758081914,
0.5555702330, 0.5349976199, 0.5141027442, 0.4928981922,
0.4713967368, 0.4496113297, 0.4275550934, 0.4052413140,
0.3826834324, 0.3598950365, 0.3368898534, 0.3136817404,
0.2902846773, 0.2667127575, 0.2429801799, 0.2191012402,
0.1950903220, 0.1709618888, 0.1467304745, 0.1224106752,
0.0980171403, 0.0735645636, 0.0490676743, 0.0245412285,
0.0000000000,-0.0245412285,-0.0490676743,-0.0735645636,
-0.0980171403,-0.1224106752,-0.1467304745,-0.1709618888,
-0.1950903220,-0.2191012402,-0.2429801799,-0.2667127575,
-0.2902846773,-0.3136817404,-0.3368898534,-0.3598950365,
-0.3826834324,-0.4052413140,-0.4275550934,-0.4496113297,
-0.4713967368,-0.4928981922,-0.5141027442,-0.5349976199,
-0.5555702330,-0.5758081914,-0.5956993045,-0.6152315906,
-0.6343932842,-0.6531728430,-0.6715589548,-0.6895405447,
-0.7071067812,-0.7242470830,-0.7409511254,-0.7572088465,
-0.7730104534,-0.7883464276,-0.8032075315,-0.8175848132,
-0.8314696123,-0.8448535652,-0.8577286100,-0.8700869911,
-0.8819212643,-0.8932243012,-0.9039892931,-0.9142097557,
-0.9238795325,-0.9329927988,-0.9415440652,-0.9495281806,
-0.9569403357,-0.9637760658,-0.9700312532,-0.9757021300,
-0.9807852804,-0.9852776424,-0.9891765100,-0.9924795346,
-0.9951847267,-0.9972904567,-0.9987954562,-0.9996988187,
-1.0000000000,-0.9996988187,-0.9987954562,-0.9972904567,
-0.9951847267,-0.9924795346,-0.9891765100,-0.9852776424,
-0.9807852804,-0.9757021300,-0.9700312532,-0.9637760658,
-0.9569403357,-0.9495281806,-0.9415440652,-0.9329927988,
-0.9238795325,-0.9142097557,-0.9039892931,-0.8932243012,
-0.8819212643,-0.8700869911,-0.8577286100,-0.8448535652,
-0.8314696123,-0.8175848132,-0.8032075315,-0.7883464276,
-0.7730104534,-0.7572088465,-0.7409511254,-0.7242470830,
-0.7071067812,-0.6895405447,-0.6715589548,-0.6531728430,
-0.6343932842,-0.6152315906,-0.5956993045,-0.5758081914,
-0.5555702330,-0.5349976199,-0.5141027442,-0.4928981922,
De elopmen o a obus h ee-phase in e e o mic og id (MG) and elec ic ac ion expe imen a ion: con ol subsys em
109
-0.4713967368,-0.4496113297,-0.4275550934,-0.4052413140,
-0.3826834324,-0.3598950365,-0.3368898534,-0.3136817404,
-0.2902846773,-0.2667127575,-0.2429801799,-0.2191012402,
-0.1950903220,-0.1709618888,-0.1467304745,-0.1224106752,
-0.0980171403,-0.0735645636,-0.0490676743,-0.0245412285,
-0.0000000000, 0.0245412285, 0.0490676743, 0.0735645636,
0.0980171403, 0.1224106752, 0.1467304745, 0.1709618888,
0.1950903220, 0.2191012402, 0.2429801799, 0.2667127575,
0.2902846773, 0.3136817404, 0.3368898534, 0.3598950365,
0.3826834324, 0.4052413140, 0.4275550934, 0.4496113297,
0.4713967368, 0.4928981922, 0.5141027442, 0.5349976199,
0.5555702330, 0.5758081914, 0.5956993045, 0.6152315906,
0.6343932842, 0.6531728430, 0.6715589548, 0.6895405447,
0.7071067812, 0.7242470830, 0.7409511254, 0.7572088465,
0.7730104534, 0.7883464276, 0.8032075315, 0.8175848132,
0.8314696123, 0.8448535652, 0.8577286100, 0.8700869911,
0.8819212643, 0.8932243012, 0.9039892931, 0.9142097557,
0.9238795325, 0.9329927988, 0.9415440652, 0.9495281806,
0.9569403357, 0.9637760658, 0.9700312532, 0.9757021300,
0.9807852804, 0.9852776424, 0.9891765100, 0.9924795346,
0.9951847267, 0.9972904567, 0.9987954562, 0.9996988187 };
#endi /* MAIN_H_ */
