Advanced I-cache prefetcher design for Out-of-Order superscalar processors

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ADVANCED I-CACHE PREFETCHER DESIGN
FOR OUT-OF-ORDER SUPERSCALAR
PROCESSORS
ADRIAN RIOS LOPEZ
Thesis supe iso
OSCARPALOMARPÉREZ(BARCELONASUPERCOMPUTINGCENTER-CENTRONACIONALDE
SUPERCOMPUTACION)
Thesis co-supe iso
MIQUELROSETJULIA(Ba celonaSupe compu ingCen e )
Tu o :MIQUELMORETÓPLANAS(Depa men o Compu e A chi ec u e)
Deg ee
Bachelo 'sDeg eeinIn o ma icsEnginee ing(Compu e Enginee ing)
Bachelo 's hesis
Facul a d'In o mà ica de Ba celona (FIB)
Uni e si a Poli ècnica de Ca alunya (UPC) - Ba celonaTech
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Abs ac
This Bachelo ’s hesis ocuses on he design and e alua ion o an ad anced Ins uc-
ion Cache (I-cache) Fe ch Di ec ed P e e che (FDP) o add ess he memo y wall
challenge in Ou -o -O de Supe scala p ocesso s. The memo y wall a ises due o
he dispa i y in he pe o mance o memo y sys ems ela i e o p ocesso s. FDP
le e ages b anch p edic o ou pu s o an icipa e ins uc ion blocks and p eload hem
in o he I-cache, educing cache miss penal ies and imp o ing e ch e iciency.
The esea ch includes designing he mic oa chi ec u e o he Fe ch Ta ge Queue
(FTQ), implemen ing i s RTL in Sys emVe ilog, and de eloping a clock-accu a e
e e ence model o alida ion. Ve i ica ion was conduc ed using Coco b, wi h pe -
o mance benchma ks highligh ing FDP’s abili y o educe ins uc ion- e ch la ency
and enhance o e all p ocesso h oughpu . This wo k con ibu es o ad ancing
high-pe o mance compu ing by op imizing p e e ching s a egies and enabling hei
in eg a ion in o u u e Eu opean-made RISC-V p ocesso designs.
Resumen
Es a esis de g ado se cen a en el dise˜no y e aluaci´on de un p e e che di igido po
la b´usqueda de ins ucciones (I-cache Fe ch Di ec ed P e e che , FDP) a anzado
pa a abo da el desa ´ıo del mu o de memo ia en p ocesado es supe scala es ue a de
o den. El mu o de memo ia su ge debido a la dispa idad en el endimien o de los
sis emas de memo ia en elaci´on con los p ocesado es. El FDP ap o echa las salidas
del p edic o de sal os pa a an icipa bloques de ins ucciones y p eca ga los en la
I-cache, educiendo las penalizaciones po allos de cach´e y mejo ando el endimien o
de e ch.
La in es igaci´on incluye el dise˜no de la mic oa qui ec u a de la cola de obje i os
de ob enci´on (FTQ), la implemen aci´on de su RTL en Sys emVe ilog y el desa ollo
de un modelo de e e encia p eciso en cuan o a los ciclos de eloj pa a la alidaci´on.
La e i icaci´on se lle ´o a cabo u ilizando Coco b, con benchma ks de endimien o que
des acan la capacidad del FDP pa a educi la la encia de ob enci´on de ins ucciones
y mejo a el endimien o gene al del p ocesado . Es e abajo con ibuye al a ance
de la compu aci´on de al o endimien o al op imiza las es a egias de p e e ching
y pe mi i su in eg aci´on en u u os dise˜nos de p ocesado es RISC-V ab icados en
Eu opa.
Resum
Aques a esi de g au se cen a en el disseny i a aluaci´o d’un p e e che di igi pe la
ce ca d’ins uccions (I-cache Fe ch Di ec ed P e e che , FDP) a an¸ca pe abo da
el ep e de la pa e de mem`o ia en p ocessado s supe scala o a d’o d e. La pa e
de mem`o ia es p odueix a causa de la dispa i a en el endimen dels sis emes de
mem`o ia espec e als p ocessado s. El FDP ap o i a les so ides del p edic o de
sal s pe an icipa blocs d’ins uccions i p eca ega -los a la I-cache, eduin les pe-
nali zacions pe allades de mem`o ia i millo an l’e ici`encia del e ch.
La ece ca inclou el disseny de la mic oa qui ec u a de la cua d’objec ius d’ob-
enci´o (FTQ), la implemen aci´o del seu RTL en Sys emVe ilog i el desen olupamen
d’un model de e e `encia p ec´ıs pel que a als cicles de ello ge pe a la alidaci´o.
La e i icaci´o es a du a e me u ili zan Coco b, amb benchma ks de endimen
que des aquen la capaci a del FDP pe edui la la `encia d’ob enci´o d’ins uccions i
millo a el endimen global del p ocessado . Aques eball con ibueix a l’a en¸c de
la compu aci´o d’al endimen op imi zan les es a `egies de p e e ching i pe me en
la se a in eg aci´o en u u s dissenys de p ocessado s RISC-V ab ica s a Eu opa.
Con en s
1. Backg ound 3
1.1. In oduc ion................................ 3
1.1.1. Con ex .............................. 4
1.1.2. S akeholde s............................ 4
1.2. Concep s.................................. 5
1.2.1. B anch p edic o s . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.2.2. Supe scala p ocesso . . . . . . . . . . . . . . . . . . . . . . . 6
1.2.3. Ou o O de p ocesso . . . . . . . . . . . . . . . . . . . . . . 7
1.2.4. I-cache P e e che s . . . . . . . . . . . . . . . . . . . . . . . . 7
1.2.5. Fe ch Di ec ed P e e ching . . . . . . . . . . . . . . . . . . . . 10
1.2.6. Non-blocking Caches . . . . . . . . . . . . . . . . . . . . . . . 10
1.2.7. Design Ve i ica ion . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.8. UVM................................ 11
1.3. P oblem iden i ica ion . . . . . . . . . . . . . . . . . . . . . . . . . . 12
1.3.1. Jus i ica ion............................ 13
1.4. Scope ................................... 15
1.4.1. Objec i e ............................. 15
1.4.2. Addi ional objec i es . . . . . . . . . . . . . . . . . . . . . . . 16
1.4.3. Requi emen s ........................... 16
1.4.4. Obs acles and Risks . . . . . . . . . . . . . . . . . . . . . . . 16
1.4.5. Me hodology ........................... 17
2. P oposal 18
2.1. Fe ch Ta ge Queue mic oa chi ec u al design . . . . . . . . . . . . . 18
2.1.1. Design in oduc ion . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.2. Fea u es Requi emen s . . . . . . . . . . . . . . . . . . . . . . 19
2.1.3. Module Func ionali y . . . . . . . . . . . . . . . . . . . . . . . 20
2.2. Fe ch Ta ge Queue implemen a ion . . . . . . . . . . . . . . . . . . . 28
2.2.1. En i onmen Se up and Tools . . . . . . . . . . . . . . . . . . 28
2.2.2. Design implemen a ion . . . . . . . . . . . . . . . . . . . . . . 29
2.2.3. Module signals in e ace . . . . . . . . . . . . . . . . . . . . . 31
2.2.4. Fe ch Ta ge Queue e i ica ion . . . . . . . . . . . . . . . . . 33
2.2.5. In eg a ion conside a ions . . . . . . . . . . . . . . . . . . . . 36
3. E alua ion 39
3.1. FTQ Pe o mance E alua ion . . . . . . . . . . . . . . . . . . . . . . 39
3.1.1. Pe o mance es bench . . . . . . . . . . . . . . . . . . . . . . 39
3.1.2. Reques s pa allelism . . . . . . . . . . . . . . . . . . . . . . . 41
3.1.3. B anch p edic o accu acy impac . . . . . . . . . . . . . . . . 45
1

4. Fu he wo k and Conclusions 48
4.1. Fu he wo k ............................... 48
4.1.1. Con idence Es ima o Op imiza ion . . . . . . . . . . . . . . . 48
4.2. Conclusions ................................ 50
A. Tempo al Planning 51
A.1.Desc ip iono asks............................ 51
A.1.1. Es ima es and he Gan . . . . . . . . . . . . . . . . . . . . . 53
A.1.2.Gan diag am .......................... 54
A.1.3. Risk managemen . . . . . . . . . . . . . . . . . . . . . . . . . 55
B. Budge 56
B.0.1. S a cos s............................. 56
B.0.2. De elopmen ools cos s . . . . . . . . . . . . . . . . . . . . . 58
B.0.3. Con ingency............................ 60
B.0.4. Unexpec ed issues . . . . . . . . . . . . . . . . . . . . . . . . . 60
B.0.5. To alcos ............................. 60
B.1.Managmen con ol............................ 61
C. Sus ainabili y epo 62
2
Chap e 1
Backg ound
1.1. In oduc ion
One o he g ea es challenges ha he compu e a chi ec u e ield is acing is,
undoub edly, he memo y wall p oblem. This issue a ises because memo y pe o -
mance has no been able o keep up wi h p ocesso s’ pe o mance, esul ing in a
bo leneck due o he high la ency o memo y access. In Figu e 1.1, we can see how
his p oblem has e ol ed om he ea ly s ages o p ocesso design up o he p esen
day.
Figu e 1.1: E olu ion o he memo y wall, compa ing memo y bandwid h o p o-
cesso ’s pe o mance [6]
Since memo y echnologies a e no keeping up wi h p ocesso s’ pe o mance, we
ha e o seek al e na i es, ocusing on mic oa chi ec u e. One o he g ea es im-
p o emen s o b eak he memo y wall has been he implemen a ion o cache mem-
o ies. These caches a e SRAM, which a e as e and smalle han main memo y.
They s o e da a ha is likely o be accessed la e , due o p og ams’ p ope ies o
empo al and spa ial locali y. These p ope ies e e o he likelihood ha con igu-
ous memo y da a, o he same da a, will be accessed in he nea u u e.
The sys em mus access he da a o he i s ime o e ie e da a ha was
eplaced, his ope a ion, in he wo s case, incu s he ull la ency cos . Howe e ,
his may no always be he case, as he da a could s ill be s o ed in he uppe le els
o he cache hie a chy. Ne e heless, he e will always be some la ency in ol ed.
3
One o he wo ypes o da a s o ed in caches is he ins uc ions ha he p ocesso
will execu e. In ac , he e is a dedica ed cache o hem called he Ins uc ion
Cache (I-cache). By sepa a ing ins uc ion da a om o he da a, i educes he
numbe o cache misses du ing ins uc ion e ching, as he e is a less in e e ence
om non-ins uc ion da a. This is an excellen imp o emen in ega d o ha ing
non sepa a ed caches, bu we s ill ha e o b ing he da a om he memo y, now
by using p e e che s we can imp o e his ime-consuming ope a ions, by p edic ing
ahead o ime which block will be used and eques ing i o he cache. Then when
he e ch s age eques s, i is a hi in cache.
1.1.1. Con ex
This Bachelo ’s Thesis is pa o he In o ma ics Enginee ing Deg ee, specializ-
ing in Compu e Enginee ing, o e ed by he Facul a d’In o m`a ica de Ba celona
a he Uni e si a Poli `ecnica de Ca alunya. The esea ch was conduc ed a he
Ba celona Supe compu ing Cen e —Cen o Nacional de Supe compu aci´on, wi hin
he Compu e Sciences—RTL Design Depa men . The p ojec ocuses on designing
an ad anced I-cache p e e che aimed a signi ican ly enhancing he pe o mance o
Ou -o -O de supe scala p ocesso s. The module will be used la e on many o he
BSC p ocesso s designs.
1.1.2. S akeholde s
The p ojec will be conduc ed a he Ba celona Supe compu ing Cen e (BSC),
wi h a ocus on esea ch a he han comme cial applica ions. I s p ima y goal is o
de elop RTL (Regis e -T ans e Le el) modules ha he BSC will use in he design
and manu ac u ing o ad anced p ocesso s. These p ocesso s a e in ended o show-
case he capabili ies o he RISC-V a chi ec u e in handling supe compu ing asks.
Addi ionally, he p ojec aims o con ibu e o he de elopmen o a Eu opean-made
p ocesso , p omo ing echnological so e eign y in high-pe o mance compu ing.
4
1.2. Concep s
1.2.1. B anch p edic o s
B anch p edic o s a e componen s in a p ocesso mic oa chi ec u e ha aim o
imp o e pe o mance by guessing he ou come o a b anch/con ol ins uc ion be-
o e i is known o ce ain. A b anch ins uc ion is a poin in a p og am whe e he
CPU mus decide whe he o con inue execu ing he nex ins uc ion in sequence
o jump o a di e en pa o he p og am, he p og am is add essed in memo y,
and his add ess is wha we call he P og am Coun e (PC). These b anches end
o block he p ocesso o some cycles. Essen ially, his will be ou main p edic ion
mechanism in ou e ch di ec ed p e e che design.
Dynamic b anch p edic o s a e he s anda d in HPC ha dwa e; his is due o
hei high p edic ion accu acy pe o mance. This kind o p edic o can adap hei
p edic ion s uc u es dynamically o e ec i ely p edic he ou pu o a b anch.
One common ype o b anch p edic o is he Global His o y Regis e p edic o .
This p edic o combines he use o a egis e con aining he n las b anches ak-
en/no aken in o ma ion, hen indexes a able whe e we can ind he las di ec ion
aken by ha speci ic pa e n. Fu he mo e, we need a way o know whe e o jump.
B anch Ta ge Bu e s (BTB) o e a solu ion o his speci ic p oblem by essen ially
making a cache o he ins uc ion poin e s o each p e ious b anch. Hence, we do
no ac ually need o wai by s alling he pipeline un il he b anch execu es i o ge
he alue o he nex PC. This in o ma ion is upda ed a e he execu ion o each
b anch ins uc ion.
An example o his b anch p edic ion scheme can be ound a [15], whe e he
ollowing igu e is p esen ed:
Figu e 1.2: Global His o y P edic o S uc u e
We should also ha e a BTB ha akes as eques he cu en PC and ou pu s
he nex a ge , i i is no a alid en y, hen i will show i by ma king i as a miss.
I beha es jus as a cache would do, we can e en add mul iple le els, bu ha ’s ou
o he scope o his hesis. Then by checking i we hi and he b anch is aken, we
will ake he esul o no .
Va ia ions o his b anch p edic o a ise, such as he Gsha e p edic o . The
Gsha e p edic o is a sub ype o global p edic o such as he Global His o y Regis e
(GHR) in e ms o main aining and u ilizing global b anch his o y. Howe e , i
5
1.3. P oblem iden i ica ion
In mode n p ocesso a chi ec u es, pe o mance elies hea ily on minimizing la-
ency when e ching ins uc ions. A poo ly designed o unde pe o ming I-cache
p e e che can lead o signi ican delays because i canno an icipa e which ins uc-
ions will be needed nex . Wi hou imely and accu a e ins uc ion p e e ching, he
CPU pipeline migh s all while wai ing o ins uc ions o be e ched om highe
le els o he memo y hie a chy (e.g., L2 cache o main memo y). These s alls de-
g ade o e all sys em pe o mance.
La es academia ends show how CPUs a e ending owa ds execu ing la ge
ins uc ion oo p in s. Tha supe scala ou -o -o de p ocesso s can execu e as e
hanks o he use o echniques desc ibed p e iously, e ec i ely inc easing he in-
s uc ions execu ed pe cycle (IPC) by doing his we will p opo ionally dec ease he
execu ion ime o many wo kloads. Bu i we do no ha e he ins uc ion da a eady
o be ead, hen i will be useless o ha e hese kinds o op imiza ions a he back
end o ou p ocesso . Because despi e ha ing he abili y o pe o m such ope a ions,
we can’ execu e hem. This can be quan i ied wi h he e ching bandwid h me ic,
and wi h he abili y o commi ins uc ions by he backend is he main bo leneck
o any mic oa chi ec u e, you will ne e be able o execu e mo e ins uc ions han
he ins uc ions you a e e ching.
Howe e , o e many yea s, esea che s ocused on c ea ing o modi ying exis ing
p e e ching p edic ion echniques. These echniques a e always somewha ela ed
o memo izing he access pa e ns o he p og am in execu ion. Essen ially, up o
some deg ee hey we e eplica ing he b anch p edic o , hese p edic ion echniques
ha e high a ea equi emen s. Since we need o s o e copious amoun s o p edic ion
da a. The e o e, esea che s ocused on c ea ing smalle p edic ion s uc u es e en
hough his app oach will cause mo e on end s alls, due o he inabili y o make
accu a e p edic ions.
This issue is exace ba ed in mul ip ocesso sys ems, whe e mul iple co es o p o-
cesso s sha e memo y esou ces and in e connec ion ne wo ks. He e, ins uc ion
cache misses slow down indi idual p ocesso s and impac sys em-wide pe o mance.
When an I-cache miss occu s, he p ocesso sends a memo y eques o e he sha ed
in e connec ion ne wo k o e ch he equi ed ins uc ion. I he p e e che is in-
e ec i e, he equency o hese misses inc eases, which causes conges ion in he
ne wo k due o addi ional memo y ansac ions. This ne wo k conges ion—o pol-
lu ion—a ec s all p ocesso s, c ea ing delays ha ipple ac oss he sys em.
To mi iga e hese issues, one e ec i e echnique is e ch-di ec ed p e e ching,
which is designed speci ically o imp o e he e iciency o he I-cache by in elligen ly
p edic ing he u u e ins uc ions he p ocesso will need. Unlike gene al p e e ch-
e s ha may ely on simple heu is ics (e.g., sequen ial p e e ching), e ch-di ec ed
p e e che s use he ac ual ins uc ion e ch s eam o guide p e e ching decisions.
This allows he sys em o mo e accu a ely an icipa e ins uc ion access pa e ns,
signi ican ly educing cache misses and imp o ing cache hi a es.
By educing he numbe o cache misses, e ch-di ec ed p e e ching alle ia es he
conges ion in he in e connec ion ne wo k. I dec eases he numbe o a oidable
12

Figu e 1.8: One o he i s -e e FDP designs [16]
memo y eques s, eeing up bandwid h o essen ial da a ans e s. This can sig-
ni ican ly enhance he pe o mance o mul ip ocesso sys ems, whe e he e iciency
o he in e connec ion ne wo k is c ucial o main aining high h oughpu and low
la ency.
1.3.1. Jus i ica ion
Fo many yea s, I-cache p e e che designs ha e been e ol ing, d i en by he need
o educe ins uc ion cache (I-cache) miss penal ies and imp o e o e all p ocesso
pe o mance. I ini ially hough I was on o some hing no el when I came up wi h he
idea o using he b anch p edic o as he p edic ion mechanism o p e e ching in-
s uc ions. The logic seemed sound, since b anch p edic o s p o ide accu a e con ol
low p edic ions, which could heo e ically guide ins uc ion p e e ching. Howe e ,
I la e disco e ed ha I was no he i s o hink along hese lines. In ac , Fe ch
Di ec ed P e e che s (FDPs) and simila app oaches ha e been a ound since he
la e 1990s [4] [5]. These designs le e age he b anch p edic o ’s ou pu o guide
p e e ching decisions, ensu ing ha he nex ins uc ions a e e ched ahead o ime,
based on p edic ed p og am low. This concep , while no new, emains a c i ical
a ea o esea ch and de elopmen , wi h mode n p ocesso s con inuing o op imize
b anch p edic o -guided I-cache p e e ching echniques o imp o ed accu acy and
educed la ency.
Wha eally s uck me was why esea che s s opped using Fe ch Di ec ed P e e ch-
e s (FDPs) o e he yea s. Pe haps his was due o b anch p edic o s ha ing lowe
accu acy a he ime, o maybe i was because caches hadn’ eached he high le els
o pe o mance hey ha e oday. Rega dless o he easoning, one hing became clea
by 2021 when esea che s launched an ins uc ion p e e ching compe i ion: ARM
enginee s decided o e isi FDPs. In a pi o al pape [9], hey explained why FDP
ou pe o med any o he me hod hey could come up wi h. And indeed, i p o ed
supe io —achie ing a 1.4x speed-up while simul aneously educing he amoun o
SRAM needed by se e al kiloby es.
This enewed in e es in FDPs shows ha ad ancemen s in b anch p edic ion
accu acy and cache pe o mance ha e made hem mo e iable in mode n a chi ec-
u es. Wha was once pe haps imp ac ical due o he limi a ions o ha dwa e has
now become a compe i i e and e icien app oach, as demons a ed by he imp es-
13
si e gains in pe o mance and memo y e iciency achie ed by ARM enginee s.
F om his pape onwa ds is whe e I decided o implemen he module. The pape
does no p o ide an implemen a ion, jus he main idea behind FDP p e e ching and
an in e ace p oposed o in e ac wi h he I-cache, which I will need o change, and
ano he one wi h he b anch p edic o . As I ha e p e iously jus i ied, his is he
mos cu ing edge p e e ching echnology ha I could implemen . I does no exis
any open-sou ce implemen a ion ha I would be able o eplica e o imp o e.
14
1.4. Scope
1.4.1. Objec i e
The objec i e behind his p ojec is o design, implemen , e i y he unc ional-
i y and es he pe o mance o an I-cache Fe ch Di ec ed P e e che module, hence
p o ing ha an FDP can be implemen ed and ha e p omising pe o mance cha ac-
e is ics. Since i is a c i ical s ep owa ds he de elopmen o an HPC p ocesso , i
mus be as e icien as he echnology allows i o be and bug ee.
Rega ding he e i ica ion p ocess, a e e ence model in C should be c ea ed o
es he implemen a ion wi h how we ac ually expec i o wo k.
Ano he impo an cha ac e is ic i mus ha e is ha i should be p ope ly doc-
umen ed, allowing o he BSC enginee s o imp o e he module o he I-cache in a
nea u u e. The in eg a ion o he module is mo e o a sub objec i e, since he
p ocesso we plan ins an ia ing i on is cu en ly unde de elopmen .
E en hough we will mos likely no be eady o in eg a e he module on o he
supe scala , ou -o -o de co e, he e will be de ailed s eps abou he cons ain s o
his in eg a ion o happen consis ing on de ailed documen a ion.
Summing up, he objec i e is o design, implemen and e i y unc ionali y and
pe o mance o he FDP module ega dless o he CPU mic oa chi ec u e, hus
p o ing he e ec i eness o using such p e e ching echniques showcasing he bene i s
and cons ain s o using his ype o p e e che s and documen he whole p ocess.
Figu e 1.9: FDP p e e che schema ic p oposed a he 2021 IPC [9]
15
1.4.2. Addi ional objec i es
I would say he e a e 2 addi ional objec i es ha b anch om his p ojec :
1. UVM es bench: Implemen ing a UVM es bench o e i y he p e e che
module i is no he main objec i e o his p ojec . Bu i is a g ea elemen
o ha e, since we could euse i o es o he ha dwa e models. Wi h he
componen s ha will gene a e signals o s imula e he DUT acco dingly o
a module o submodule beha io (UVM agen s) ha I will de elop o his
p ojec . I will ensu e he eusabili y o he en i onmen . This way, we will
ca ch a mo e e o s in he design phase and lea e mo e bandwid h o he
e i ica ion eam o e i y o he p ojec s.
2. Module In eg a ion The in eg a ion o he module is no he main objec i e
o his p ojec , and i will depend on he de elopmen o he RISC-V co e done
by BSC.
1.4.3. Requi emen s
The equi emen s I would say a e o ha e a well-de ined in e ace wi h he co e
and o he componen s, o be able o un he p ojec coded in Sys emVe ilog wi hou
compile e o s o wa nings. And o he non- unc ional ones, is ha ing a g ea
documen a ion enabling o u he de elopmen and in eg a ion.
1.4.4. Obs acles and Risks
We ha e been able o iden i y a main obs acle o his p ojec , and i is ha
he e a e no pas e e ences we can sus ain ha a eal implemen a ion wi h g ea
pe o mance can be achie ed. Ano he mino obs acle is ha since he e was a ime
when he de eloping o hese FDPs was held on s andby, he e is a lack o public
esea ch a ailable, al hough his could also be an oppo uni y.
The e a e no any impo an isks o conside , maybe he mos impo an is he
ime and deadlines.
16
1.4.5. Me hodology
An Agile me hodology is p oposed o he implemen a ion and e i ica ion o
he Fe ch Di ec ed P e e che (FDP) in his hesis due o i s adap abili y and sui -
abili y o managing complex esea ch-based p ojec s. The p ojec will be di ided
in o i e a i e sp in s, wi h each sp in ocusing on speci ic aspec s such as designing,
op imizing, and e i ying he FDP. This inc emen al app oach will acili a e con-
inuous p og ess, allowing o egula deli e y o unc ional componen s h oughou
he de elopmen cycle.
F equen eedback loops will be in eg al o he p ocess, enabling cons an e ine-
men and adjus men s based on ea ly es ing esul s. Agile’s lexibili y will help
add ess un o eseen challenges, such as po en ial bo lenecks in p edic ion accu acy
o pe o mance, by allowing o dynamic ep io i iza ion and expe imen a ion wi h
al e na i e solu ions. Regula sp in e iews and e ospec i es will ensu e ha is-
sues a e iden i ied and esol ed p omp ly.
Clea miles ones will be es ablished a he end o each sp in o ensu e s uc u ed
p og ess acking, helping o main ain alignmen wi h p ojec goals and imelines.
Agile will also acili a e egula collabo a ion h ough check-ins wi h ad iso s and
s akeholde s, ensu ing ha eedback is consis en ly inco po a ed in o he de elop-
men p ocess. Con inuous in eg a ion and es ing phases will be embedded wi hin
each sp in o ensu e ha he FDP’s unc ionali y and pe o mance a e e i ied in-
c emen ally.
By deli e ing wo king componen s ea ly and e ining hem i e a i ely, he Agile
app oach is expec ed o minimize isks ela ed o incomple e o un e i ied wo k.
This me hodology will p o ide he necessa y s uc u e, lexibili y, and esponsi eness
o manage he complexi ies o FDP implemen a ion and e i ica ion, ensu ing he
p ojec emains on ack o achie e i s objec i es e icien ly and e ec i ely. [19]
17

Chap e 2
P oposal
2.1. Fe ch Ta ge Queue mic oa chi ec u al de-
sign
2.1.1. Design in oduc ion
The Fe ch Ta ge Queue is an implemen a ion o he well-known Fe ch Ta ge
Queue (FTQ) [16] wi h he addi ional suppo o Fe ch Di ec ed P e e ching (FDP).
The main pu pose o his module is o use he p edic ed ins uc ion blocks om he
b anch p edic o o p e e ch hem in o he L1 I-cache, he e o e when he ins uc-
ion is e ched by he e ch engine we al eady ha e hem a ailable in he I-cache,
and i does no gene a e a miss o ha access.
As i was ea ly s a ed by [16], opposed o a adi ional e ch engine ha couples
he b anch p edic o wi h he ins uc ion cache, he FTQ a chi ec u e is wha en-
ables o p o ide a decoupled on -end. The b anch p edic o in a ypical coupled
on end e ec i ely p oduces he nex e ch add ess, ob iously his would no gi e us
any kind o p e e ching ad an age because i is no unning ahead om e ch. Fu -
he mo e, by no ha ing a decoupled on -end we a e causing he ins uc ion e ch
ope a ion o s op whene e we ha e an ins uc ion cache s all, as well as s opping
he b anch p edic o ope a ions un il he cache miss ha caused he s all esol es.
Ano he impo an conside a ion is ha he use o he so-called Fe ch Ta ge
Bu e desc ibed a [17], which nowadays is used in e changeably wi h he BTB.
This FTB concep di e s om he adi ional BTB by using ins uc ion poin e s
blocks ins ead o p edic ing smalle a ge s (some imes e en jus a single ins uc-
ion, depending on he a chi ec u e) his showed a g ea pe o mance imp o emen
o a 25% a he ime. In he es o he documen , we will use FTB and BTB e ms
in e changeably, bu i was impo an o de ine his e m due o he scalabili y ben-
e i s ha i p o ides.
The FTQ is he on -end decoupling mechanism ha we will be using in his
implemen a ion. The b anch p edic o will p oduce e e y cycle a s a add ess o
a cache block, which will be bu e ed in o he FTQ, whe e i will make he eques
o he I-cache, e ec i ely making b anch p edic o and cache ope a ions o ally
independen . The e o e, he b anch p edic o can un ahead om he ins uc ion
cache when i is s alled in a miss. The b anch p edic o p oduce in e ace is p e y
clea , bu how will we upda e i s en ies o make co ec p edic ions, and o he
18
ele an in eg a ion cons ain s in he pipeline, will be u he discussed in sec ion
2.2.5.
The FTQ has o s o e he p edic ed blocks in a FIFO way. The da a s uc u es
ha we will s o e a e de ined in sec ion 2.1.3. We ha e also no iced ha we will
need some kind o con ol mechanism pe FTQ en y, his shall be done h ough
he use o a Fini e S a e Machine (FSM), hanks o his mechanism we will be able
o know when an en y has been al eady eques ed o he I-cache and when i has
been alloca ed, he de ini ion o his FSM can be ound in igu e 2.2.
The mos c i ical FTQ design ea u e will be o ha e wo head poin e s and a
common ail, unlike a common FIFO con olle whe e he e is jus one o each, la e
on in sec ion 2.1.3, i will be explained why.
2.1.2. Fea u es Requi emen s
The ea u es equi ed o his module aim o p o ide he in e aces necessa y o
bo h, he Fe ch engine, and he Ins uc ion Memo y.
A minimum ea u e is he c ea ion o a c edi in e ace o he p oduce o he
FIFO, be i he Fe ch Engine, his in e ace shall be capable o w i ing in o he Fe ch
Ta ge Queue whene e he b anch p edic o is eady o his ope a ion o happen
as well as he FTQ, also we should p o ide he FTQ wi h some mechanism o ese
he queue and lush he con olle s in case a misp edic happens. The ull p ocess
is desc ibed a 2.2.5.
Secondly, an implemen a ion o a agged in e ace o esol e I-TLB/I-cache ag
lookup and ga he he da a a ay posi ion (way) as a con i ma ion o he success o
he ope a ion. This in e ace has a eady/ alid handshake o he way eques wi h
an iden i ica ion ID/ ag, and an addi ional esponse channel wi h a alid handshake,
which can come ou -o -o de wi h he co esponding ID.
Thi dly, we mus T ack I-TLB/I-cache ag lookup comple ion wi hin alid FTQ
en ies, using a head ha dwa e poin e , so ha whene e i is ma ked as alloca ed
i can i e a signal o le he consume know ha he da a is a ailable and upda e
he b anch p edic o .
Fou hly, implemen ing a alid handshake o he ead ope a ion o he Ins uc-
ion memo y da a a ay, his p ocess should be con olled by he I-cache, basically
because mos o he in o ma ion needed is in he cache con olle , bu we will p o-
ide he necessa y in o ma ion and a de ailed in e ace on how o do i .
The e is only one desi ed op ional ea u e, and i is o pa ame ize he numbe
o po s o he FIFO p oduce , his could imp o e he un ahead capabili ies o he
module, by basically ha ing a highe bandwid h communica ion wi h he b anch
p edic o .
19
Fu he mo e, a pa ame iza ion o he wo ollowing pa ame e s mus be done,
la e on, we will speci y in sec ion 2.1.3 how he da a s uc u es o each en y should
be pa ame ized.
Field Type Desc ip ion
WR PORTS in Numbe o w i e po s o he FTQ.
SIZE in Numbe o en ies o he FTQ.
Table 2.1: FTQ Con igu a ion Pa ame e s
2.1.3. Module Func ionali y
The unc ionali y o his module is based on he wo k om [9]. Mo e p ecisely,
he low o ins uc ions h ough he FTQ, he concep o decoupling om he on-
end, as well as how we upda e he b anch p edic o .
In Figu e 2.1 we can see a high-le el abs ac ion o he inal design. We will
explain how he basic concep s o he design wo k, be o e deep di ing in o he
con ol logic and de ailed da a low.
Figu e 2.1: Fe ch Ta ge Queue module abs ac ed
We can no ice a he design he FIFO queue which holds he ins uc ion blocks
w i en h ough he p oduce w i e po s ( q w en y i), ha a e hen eques ed
o he cache. The en ies a e being w i en will be eques ed o he cache will
be pe o med h ough he eques Da a po , he esponse will be ecei ed by he
Way agged in e ace. Finally, hese en ies a e consumed h ough he ead po
( q d en y o).
The 4 s ages ha he Fe ch Ta ge Queue module will need o implemen a e
called FTQ 0, FTQ 1, FTQ 2 and FTQ 3 espec i ely. As i would be expec ed om
a egula FIFO queue, poin e s a e needed o pe o m he w i e and ead ope a ions,
also unlike a ypical FIFO his design needs o ha e 2 head poin e s and a common
ail.
20
A i s , i may seem qui e odd o ha e h ee poin e s in a FIFO queue, bu once
we explain he module unc ionali y, i will be clea ed ou . The h ee poin e s a e
desc ibed as ollows:
1. Tail poin e : The ail poin e keeps ack o he nex posi ion o inse da a
a he “end” o he queue. I ensu es ha elemen s a e inse ed in he o de
hey a i e and emo ed in he same o de , ollowing he FIFO p inciple
2. FDP (Fe ch Di ec ed P e e ching) poin e : The FDP poin e is he one in
cha ge o eading each en y and he necessa y da a o make he I-cache e-
ques , as long as he en y ead mee s he necessa y condi ions.
3. Head poin e : Las ly, we ha e he head poin e , i will be cons an ly eading
he in o ma ion om he oldes w i en en y o he FTQ, and once i is
ma ked as alloca ed i will i e a signal o ma k i as alid, so he consume
can ead i .
FTQ En y
Each FTQ en y needs o s o e he da a needed o make he eques s o he I-
cache and la e on upda e be consumed. E e y ield’s wid h is ully pa ame izable,
o adap o any design. In Table 2.2 we can see how each ield is de ined and i s
co esponding size.
Field Size
S a add ess Vadd
I-cache way log2(I-cache associa i i y)
S a e 2-bi
Me ada a METADATA SIZE
Table 2.2: FTQ En y da a s uc u e and sizes
We only need o hold 4 da a ields o each FTQ en y o ha e a unc ional
module, we will see he size implica ions la e on. Each ield is de ined as ollows:
S a add ess: I is he i ual add ess o he e ch block being e ched. In
his case, i is he i ual add ess ins ead o he physical add ess because he
cache is i ually indexed. I could also be changed o he physical add ess
size hanks o he highly pa ame izable capabili ies o he module.
I-cache way: i is he way whe e he p e e ched block has been alloca ed a
he I-cache, o be used as he con i ma ion.
S a e: This iled s o es he s a e o he FTQ en y. A de ailed FSM diag am
is p o ided in igu e 2.2. I uses 2 bi s because we need 3 s a es, In alid, Valid
and Read Ready.
Me ada a: This ield is implemen a ion-independen . This means ha he
in o ma ion necessa y o s o e depends on he con ex in which he FTQ is
used ins ead o his implemen a ion. I his in o ma ion we e o be used in
he con ex o p edic o s, he minimum in o ma ion equi ed would be he one
necessa y o communica e he decisions made in he p edic ion s age, mainly
o co ec ion pu poses.
21
2.2. Fe ch Ta ge Queue implemen a ion
This sec ion discusses how he FTQ module design was implemen ed in RTL.
We will i s in oduce he echnologies used, as well as he submodules and logic
implemen ed, passing by he inal module in e ace and inally a p ac ical example
o how i ope a es.
2.2.1. En i onmen Se up and Tools
The implemen a ion and e i ica ion (la e o be explained in Sec ion 2.2.4) ools
ha I used o he de elopmen o he p ojec can be summa ized in o 4.
1. Docke : A con aine iza ion pla o m ha p o ides a consis en and ep o-
ducible en i onmen o de elopmen and es ing. By encapsula ing all de-
pendencies wi hin a Docke con aine , i was possible o s eamline he se up
p ocess and main ain compa ibili y ac oss di e en sys ems.
2. Ve ila o : A con aine iza ion pla o m ha p o ides a consis en and ep o-
ducible en i onmen o de elopmen and es ing. By encapsula ing all de-
pendencies wi hin a Docke con aine , i was possible o s eamline he se up
p ocess and main ain compa ibili y ac oss di e en sys ems.
3. HLIB: A Sys em Ve ilog Ha dwa e Lib a y o highly pa ame ized s anda d
usage modules de eloped a BSC. The e a e many ways o app oach an RTL
design, and o en, i is no necessa y o s a om sc a ch because some mod-
ules ha e al eady been designed; he missing pa was o iden i y and o ganize
hose modules o common use and ha mo i a ion is wha gi es li e o his
lib a y ha aims o con ibu e wi h he pa ame e iza ion o hese modules
and hus educe he o e head o mic o-a chi ec u al ha dwa e design.
4. Coco b: A Py hon-based co ou ine es bench amewo k designed o e i ying
HDL designs. Coco b enabled high-le el, lexible es w i ing, allowing Py hon
o in e ace wi h he RTL module h ough a simula ion backend, in ou case
Ve ila o .
As you ha e may no ice, I did no use Ques aSim o any o he comme cial
EDA ools, his was an unexpec ed p oblem in which licenses o Ques aSim we e
empo a ily una ailable a BSC. When licenses came back, he p ojec was oo
ad anced o swi ch in as uc u e, so i was decided o ca y he whole p ojec wi h
Ve ila o and Coco b.
28

2.2.2. Design implemen a ion
In his sec ion, we will alk abou how we managed o implemen he design
p esen ed in he p e ious sec ions. Fo emos , he g ea es challenge o his module
was o c ea e a FIFO queue wi h wo head poin e s and a common ail poin e .
Making a whole new module o jus manage wo heads and a common jus did
no make sense, specially when we al eady go a FIFO con olle module. Maybe
in a nea by u u e, he FTQ module will be imp o ed wi h his 2 headed FIFO
con olle . Mo eo e , conside ing he igh schedule o his p ojec , and he possible
imp o emen s would no be wo h o spending ha p ecious ime on implemen ing
and, mo e impo an , e i ying he module.
The e o e, i was decided o use he al eady exis ing module, he FIFO con-
olle . This module implemen s he con ol sys em o a highly pa ame izable
ci cula bu e FIFO, allowing use s o de ine he pa ame e s o he queue. Commu-
nica ion wi h he module is acili a ed h ough w i e and ead eques s, o which he
module esponds by g an ing hese eques s and p o iding indexes o ope a ions in
he ac ual memo y.
I managed o connec wo o hese FIFO con olle modules in a single module,
he queue in i sel is jus a highly pa ame izable logic a ay o he de ined s uc u e
in Sec ion 2.1.3. Mo eo e , a ese a ay was de ined by se ing all elemen s o 0,
lushing he queue. I he e was a ese , he FIFO con olle s would lush and ese
bo h poin e s.
FIFO con olle s usage
Once we go bo h FIFO con olle s ins ances de ined inside he FTQ module, we
need o comp ehend how hey wo k o unde s and u u e p oblems ha may a ise
om his ope a ion. The mos di icul p oblem is, undoub edly, synch onizing bo h
poin e s, o ensu e a co ec ope a ion.
Fi s , i should be made clea ha he FIFO con olle module is a module which
gi es us wo poin e s, o a he indexes, hese indexes ell us which a ay posi ion
we should w i e o o ead om. Fu he mo e, i is impo an o ensu e ha i is
possible o do he ope a ion, his is called g an . A w i e ope a ion will be g an ed
in a po whene e he po is ee and he queue is no ull. A ead will be g an ed
when he po is no being accessed by ano he componen and he queue is no
emp y, o a oid eading in alid da a.
Fo FTQ 0 s age, he only ime when we should synch onize is whene e he e is
a w i e ope a ion in o he FTQ by he p oduce , since his ope a ion is ully ans-
pa en o he o he con olle . The bes solu ion ha I was able o ind was ha
he FDP head would also ecei e he same w i e enable signal, he e o e bo h ails
a e now in sync.
Then we go h ough FTQ 1, in his s age we should ead wi h he FDP head
each en y. Howe e , he ead should only be pe o med whene e he cache is eady
o ecei e a eques . Essen ially, he ead enable signal is he cache eady signal.
29
We can ead he da a by jus assigning he ou pu o he a ay posi ion indica ed by
he index. By doing his we can sa e logic, imp o e eadabili y and keep i simple.
In his s age, he e is he so called agged in e ace, his in e ace p o ides jus he
cu en ead index om he FDP head o he cache, by doing his simple mechanism
we le he cache handle i , which has al eady exis ing s uc u es ha could add an
ex a ield o manage i , ins ead o elabo a ing complex logic o ables. Now he
only hing ha is le is when should we igge he eques , o in o he wo ds, when
is he da a ha we a e eading alid.
Well, o answe his ques ion, we should hink how his poin e mo es, he head
poin e will ad ance un il i eaches he ail poin e , so i will only ead da a in
he alid s a e, since in his implemen a ion canno come back o p e ious accessed
posi ions ( his is a c i ical poin ha was a oided hanks o he agged in e ace),
a some poin he ail will be eached and his is he only case whe e he da a is no
alid. This case is he same as conside ing he queue as emp y, hen he alid da a
signal will be he no emp y signal.
In FTQ2, we ecei e he way assigned o he ins uc ions block om he cache
and he ag belonging o ha eques . When we ecei e he esponse, we jus need
o index he a ay wi h he ag and se o e w i e he way as well as he s a e (se
o Read Ready).
Finally, we ha e he FTQ3 s age, he da a ead po is always assigning he alue
o he en y poin ed by he head, by indexing he memo y a ay. The alid da a
depends on he ead enable signal, whene e we ead we should ha e he en y in a
Read Ready s a e and he consume as eady. These condi ions a e checked in an
always comb s a emen , hen i is assigned o a alid da a signal ha will igge
he ac ion.
I would also like o ei e a e ha his was all made wi h he in en ion ha e e y
single s age could happen a once o di e en en ies, also known as segmen ed
o pipelined design. Thanks o his ea u e, he pe o mance o he module will
inc ease, allowing us o mask some added la ency o he pipeline
A he ollowing Subsec ion 2.2.3 i is possible o ind he inal module in e ace
signals as well as he pa ame e s o con igu e i .
30
2.2.3. Module signals in e ace
Now we a e going o name each signal om he in e ace o e e p ope ly o
hem om now on.
Pa ame e s
Pa ame e Desc ip ion
FIFO SIZE Numbe o elemen s (en ies) in he lis .
START ADDRESS SIZE Wid h o he s a add ess in bi s.
TAG SIZE Size o he ag ield in bi s.
STATE SIZE Size o he s a e ield in bi s.
METADATA SIZE Size o me ada a associa ed wi h each en y.
WORD WIDTH Numbe o bi s pe wo d in he FIFO.
WR PORTS Numbe o pa allel w i e po s.
RD PORTS Numbe o pa allel ead po s.
RPTR INIT VALUE Ini ial alue o he ead poin e .
WPTR INIT VALUE Ini ial alue o he w i e poin e .
FULL OFFSET Numbe o slo s ha de ine FIFO ull.
WR WHEN FULL AND RD Allow w i es e en when FIFO is ull and a ead is hap-
pening a he same cycle.
RST DATA VALUE Rese alue o all FIFO slo s.
UNORDERED READS Allow uno de ed pa allel eads.
UNORDERED WRITES Allow uno de ed pa allel w i es.
PARALLEL FLUSH WR Allow lush and w i e simul aneously.
PTR BITS Bi s needed o index a poin e o FIFO SIZE.
PTR COUNT BITS Bi s needed o ep esen he numbe o slo s in he
FIFO.
Table 2.3: Pa ame e s o he Fe ch Ta ge
31
Inpu s
Inpu Po Desc ip ion
clk i Sys em clock signal.
s n i Sys em ese signal (ac i e low).
lush i Flush FIFO, p io i izing lush o e eads and w i es.
o e w i e d eq i Reques o o e w i e ead poin e .
o e w i e d p i Value o o e w i e he ead poin e .
o e w i e w eq i Reques o o e w i e w i e poin e .
o e w i e w p i Value o o e w i e he w i e poin e .
q0 alid da a i Valid da a signal o p oduce .
q0 s a add ess i S a add ess o p oduce da a.
q0 me ada a i Me ada a o p oduce da a.
q1 cache eady i Cache eady signal.
q2 cache alid i Valid da a signal om cache.
q2 way assigned i Cache way assignmen .
q2 ag i Queue posi ion ag.
q3 consume eady i Consume eady signal.
asse ions enable i (Simula ion only) Asse ion enable signals.
Table 2.4: Inpu Signals o he Fe ch Ta ge Queue
Ou pu s
Ou pu Po Desc ip ion
w g an s o W i e g an s a ay o po s.
d g an s o Read g an s a ay o po s.
cu en w p o Cu en alue o he w i e poin e .
cu en d p o Cu en alue o he ead poin e .
consumed slo s o Numbe o elemen s s o ed in he FIFO.
a ailable slo s o Numbe o ee slo s in he FIFO.
i o ull o Indica es when he FIFO is ull.
i o emp y o Indica es when he FIFO is emp y.
q0 i o no a ailable o Indica es FIFO is no a ailable.
q1 eq alid o Cache eques alid signal.
q1 eq add o Cache eques add ess.
q1 eq ag o Tag o cache eques .
q3 da a o Da a o consume .
q3 alid da a o Valid da a signal o consume .
Table 2.5: Ou pu Signals o he Fe ch Ta ge Queue
32
2.2.4. Fe ch Ta ge Queue e i ica ion
An essen ial s ep in he design and implemen a ion pipeline is he design e i i-
ca ion. This will ell us i he design wo ks o no , i will also ligh up he bugs ha
ou design could po en ially ha e.
A UVM en i onmen was decided o no be c ea ed, unlike i was planned in
Sec ion 1.4.2. This decision was aken because a he end i would ha e mean o
ha e eplica ed wo k, and his wo k could ha e no been eused o o he p ojec s.
Mo eo e , he lack o Ques aSim licenses made a g ea impac since we could no un
any UVM simula ions, his was he inal de e en o making a UVM en i onmen .
Le ’s elabo a e on wha I mean by eplica ed wo k. The HLIB lib a y is an RTL
lib a y c ea ed and main ained by RTL enginee s, hey decided o use coco b o
e i ying hei wo k, which is a e y alid op ion o only doing uni e i ica ion, bu
lacks o unc ionali ies ha make UVM g ea , such as i s eusabili y, complica es
connec ions o o he modules, lack o a well-de ined es ing so wa e a chi ec u e
ha could induce e o s, i is e y slow and has poo scalabili y . . . These a e only
some easons o why UVM is he e i ica ion indus y s anda d, bu his is eally
no needed o uni e i ica ion, o a he i can be easie o use coco b in his case,
o no eplica e wo k and since Coco b capabili ies as UVM o his use case. Co-
co b was he only one ha was decided o be used and keep consis ency wi hin he
exis ing eposi o y.
The o he eason o use UVM was due o eusabili y, bu in his con ex he
UVM made would be p obably a oo much speci ic, hus mos o he UVM would
p obably need o be changed o use i wi h o he modules. The in e es ing pa
would be o euse he FTQ agen , which edoing i could be a edious wo k o
someone who has no wo ked be o e on he module.
The solu ion I came up wi h was o make a e e ence model in C which can sub-
s i u e he UVM agen in case i is needed o o he p ojec s, including in eg a ing
i in a UVM en i onmen , as well as using i o he coco b uni e i ica ion.
33

In he ollowing igu e, you can see he p oposed schema ic o he UVM, jus o
look a how he e e ence model in e ac s.
Figu e 2.10: UVM p oposal
Re e ence model
The FTQ e e ence model mus be w i en in C, o ensu e po abili y o a UVM
ha could be w i en o ano he module, and should be able o in e ac wi h he
Coco b es bench w i en in py hon. In his case, I ha e chosen o use c ypes, which
is a py hon API ha enables o in e ac wi h he C code compiled as a sha ed objec .
Ano he eason o choose his one is due o he g ea suppo om he communi y
as well as he ex ensi e documen a ion.
Howe e , he use o his API is only empo al and o simplici y pu poses, in
he nea u u e i would be use ul o po i o dpi-c. Which is ano he lib a y ha
enables o in e ace Sys emVe ilog wi h o eign languages, in his case C. This po
should no ake ha much ime, bu I did no do i because I would also need o use
c ypes, so i would add an ex a s ep whe e hings can ail. Addi ionally, depending
on which HDL simula o is being used, da a de ini ions such as s uc s can change
i s o de .
34
Finally, he mos impo an de ail abou he e e ence model is ha i is clock
accu a e. This means ha when he unc ion is called om he es bench i emula es
exac ly all he signals a e one clock, as well as he FTQ en ies, o cou se.
Uni e i ica ion es bench
The es bench, as we men ioned be o e, was made in py hon using he coco b
lib a y. In his es bench we do no need o ha e a p ecise cache model because we
a e looking o co ne cases ha could cause a bug.
The connec ions o he DUT a e made h ough he coco b API wi h Sys emVe -
ilog, now we should emula e he ese as well as he clock ope a ions. These a e
done h ough special coco b API calls.
We ha e a e e ence model, bu i we do no compa e he esul s, hen i is use-
less. Since I decided ha i was going o be a clock accu a e model, I could compa e
each en y e e y cycle o he DUT and i i is di e en om he expec ed alue,
aise an excep ion.
Fi s I did a simple es ha would go h ough he simple ope a ions, in his case
i was decided o i s w i e in o FTQ, and simula e a ead om he FDP poin e as
well as he esponse and consume ope a ions. When I go hese simple ope a ions
wo king, I s a ed es ing e e y s age in pa allel by aising all alid signals a he
same ime. A e wo king on some condi ions ha should ha e been handled by he
p oduce , consume and he I-cache, ha we e emula ed by he es bench, I go i
wo king.
The nex s ep would be o use ully andomized es s, hese es s also needed o
gua an ee ha impossible si ua ions could no happen. Fo example, a esponse o
a non- eques ed add ess could in e e e wi h he ag in e ace.
To accomplish his, I needed o keep ack o he eques s ha had been made.
Wi h he use o a simple py hon code, by pushing in o an a ay and doing a pop o
he da a, I was able o emula e he cache beha io .
Now, by ully andomizing he inpu s, in a cons ain manne , we can compa e
he esul s.
Random es s esul s
A e some debugging i e a ions, he design was capable o execu ion 100k an-
dom i e a ions success ully wi hou any asse ion ailing.
35
2.2.5. In eg a ion conside a ions
E en ually, he FTQ (Fe ch Ta ge Queue) module will need o be in eg a ed
in o a p ocesso co e. This in eg a ion necessi a es ca e ul conside a ion o se e al
aspec s ha di e om he scena io whe e a e ch-di ec ed p e e che is no p esen .
The FTQ inhe en ly modi ies how ins uc ion e ch and p edic ion in e ac , as i in-
oduces an addi ional laye o complexi y in managing e ch a ge s and ensu ing
high bandwid h u iliza ion.
Addi ionally, when we a e adding such a new elemen ha changes he pipeline
i does no come as cos ee, his impac is quan i ied in Figu e 2.11 and es ed
agains expe imen al esul s in sec ion 3.1.
Added pipeline la ency
The FTQ is essen ially a bu e and a bu e adds ex a cycles o he pipeline,
conside ing how he w i e and eques ope a ions ha e o be ca ied whene e he
FTQ is emp y.
Thank ully, hese cycles a e masked when ei he he p og am low has no s a ed
ye and is a miss, hen he signi ican la ency will be he eques and no he cycles
om w i ing and eques ing, also i he ollowing eques s a e misses i will no im-
pac he pe o mance since he p e ious eques s a e also misses, and hey a e being
esol ed in pa allel.
The o he case is when he p og am is unning and hi ing, wi hou he b anch
p edic o sending lush eques s hinking o a alse misp edic , hanks o he p o en
un ahead capabili ies o he FTQ i will compensa e o he delay.
The penal y incu ed by lushing he FTQ e e y ime a eco e y e en is ig-
ge ed by he e ch engine canno be a oided by any means. This penal y canno
be masked in any way, bu his penal y is much lowe han he one i would ha e
i i we e due o a Cache e o . Since we ha e a segmen ed pipeline, once he da a
pa h s a s illing up again, he pe o mance would be he same as no ha ing a
p e e che in he pipeline.
One clea case whe e we can see he impac o his la ency is whene e he p o-
g am is hi ing, bu he eco e y e en igge s a lush eques , his will make he
di e ence no iceable, and we will be able o quan i y he FTQ delay.
36
We can ep esen and quan i y he impac o his added la ency in he ollowing
igu e, whe e he pipeline is ep esen ed.
Figu e 2.11: Added pipeline la ency compa ed o p e ious pipeline
As we can see, we now add 2 ex a penal y cycles whene e a eco e y ope a-
ion igge s a lush o he FTQ. We can see ha no ex a eques s o he I-cache
a e made, e en hough he eco e y ope a ion comes 2 cycles la e han we expec ed.
In conclusion, we ha e quan i ied he o al penal y, in he wo s case, o be 4
cycles, 2 mo e han he p e ious pipeline wi hou he p e e che . In sec ion 3.1 we
will expe imen ally p o e ha i does no su pass his numbe .
37
And we can also see i s speed-up o no p e e ching:
Figu e 3.4: Speed-up achie ed using 8 MSHRs o each FTQ size
Finally, he ques ion ha we migh ask ou sel es is o a ce ain numbe o
MSHRs which is he ideal FTQ size, he ollowing igu e answe s his ques ion:
Figu e 3.5: Ideal FTQ numbe o en ies pe numbe o MSHRs
We can see o his wo kload ha up o a numbe o MSHRs (32 in his case) we
no longe ob ain g ea e imp o emen , his can be one o he easons o why I-caches
a ely ha e mo e han 32 MSHRs, o i also could be ha he numbe o accesses is
low.
In ac , wha we a e ac ually seeing is he maximum la ency o 30 cycles men-
ioned abo e. So he e is no mo e ad an age o ha ing mo e eques s no MSHRs.
44

3.1.3. B anch p edic o accu acy impac
The Fe ch Ta ge Queue depends solely on he b anch p edic o accu acy. Be-
sides he ob ious eason o p e e ching he co ec block, he e is also ano he
eason o which he p edic o accu acy is impo an . As I explained in sec ion 2.2.5
whene e he e is a misp edic i needs o lush he FTQ, which in he wo s case
adds a bubble o 4 cycles in which he pending s ages will be disca ded by he lush
igge ed by he eco e y ope a ion.
Fo his eason, we will measu e he numbe o cycles was ed by he eco e y
ope a ion o ensu e ha i does no su pass he expec ed maximum la ency. To
do his i s , we need o calcula e he expec ed wo s -case o al added la ency. To
do so, we need o de e mine he numbe o accesses o execu e, which all o hem
should be hi o a oid mixing he esul s wi h he la ency due o misses, a e some
es ing I ound ha he a e age o he esul s (selec ing be ween eco e y o no )
ma ched he expec ed alue o he accu acy o he b anch p edic o se o 90% which
can be easily achie ed by mode n b anch p edic o s. This numbe was 5120 accesses.
Fi s le ’s calcula e he esul o a 100% o accu acy La ency = (1 ∗1 + 0 ∗3) ∗
5120 + 4 = 5124cycles, he 4 ex a cycles a e o he i s 4 cycles accoun o he
cold s a . Now we jus need o calcula e he o al cycles alue, o accomplish his,
we need o calcula e he ollowing o mula. La ency = (0.9∗1 +0.1∗3)∗5120+ 4 =
6144cycles This is he expec ed alue o ou implemen a ion. I is in ac 2 cycles o
penal y only, since he design in his es does no need a cycle o p oduce he alue,
and i can ac ually pe o m he FTQ 1 eques and FTQ 2 esponse in he same
cycle. Since he access is a hi , i will espond in he same cycle and he ope a ions
needed o change he s a e can be pe o med nea he end o he cycle.
A e execu ing i 10 imes, we go he uppe alue o be 5972 cycles and he
lowe alue o be 5667, wi h an a e age o 5753, his a iance can be accoun ed o
he momen whe e he lush a i es o he FTQ, o ins ance consecu i e lushes
whe e he la ency in be ween is smalle han he penal y. Fu he mo e, he andom
module om py hon is no pe ec and in o al is accoun ing o a 4% di e ence in
his case
45
Then i is also in e es ing o see how by inc easing he b anch p edic o accu acy
he cycles aken o execu e he es e olu ion, s a ing a an 85% and ending a he
100%.
Figu e 3.6: Cycles aken o execu e he wo kload s. he accu acy o he b anch
p edic o
In his case, as we expec ed, we can see how he cycles aken o execu e he wo k-
load dec ease p opo ionally o he b anch p edic o p ecision. This shows ha ou
module beha es co ec ly and has g ea pe o mance, specially when inc easing he
accu acy o he b anch p edic o .
Ano he me ic we a e eage ly awai ing o ex ac wi h his es i he blocks
e ched pe cycle, depending on he b anch p edic o accu acy. We should expec
his numbe o go up as we inc ease he b anch p edic o accu acy. We will s ill
keep he 5120 accesses. I we do so, we will see he ollowing igu e:
Figu e 3.7: Fe ched blocks pe cycle s. he accu acy o he b anch p edic o
46
We can see how i inc eases p opo ionally o he accu acy o he b anch p edic-
o .
In conclusion, his es has shown ha he module implemen ed is capable o
ha ing a good pe o mance when we a e compa ing i o he al e na i e non-p e e ch,
despi e he added la ency o he pipeline. I also s ongly sugges s ha ha ing a
high b anch p edic o accu acy such as he ones we can ind a mode n b anch
p edic o s. Mo eo e , i has p o en ha he p e e ching bandwid h is high enough,
despi e he misses, o s ill un ahead o he p og am low.
47
Chap e 4
Fu he wo k and Conclusions
4.1. Fu he wo k
Besides he in eg a ion o he FTQ module o wo king mode n supe scala and
ou o o de CPU, he e is one mo e op imiza ion ha could help o imp o e he
pe o mance o he execu ion. Specially in mul ip ocesso designs, whe e ne wo k
and cache pollu ion due o inco ec o oo agg essi e p e e ching can become a
p oblem.
4.1.1. Con idence Es ima o Op imiza ion
Fe ch Di ec ed P e e ching le e ages p e e ching en i ely o decisions made by
he b anch p edic o s. Howe e , b anch p edic o s despi e ha ing high accu acy,
some o hem eaching 98%, acco ding o p obabili y a e n decisions he p obabil-
i y o p edic ing he co ec b anch would be 0.9ni we ied p edic ing co ec ly 6
consecu i e b anches we would ha e a success p obabili y o a ound 0.53, which is
eally low o he wo kload ha we a e execu ing.
Occasionally, i can be bene icial o no p e e ch wi h such low p obabili y, since
inaccu a e p e e ches can lead o cache pollu ion, was ed memo y bandwid h, and
inc eased ene gy consump ion. Specially in mul ico e sys ems whe e bandwid h and
ne wo k pollu ion a e essen ial o good pe o mance.
P e e ch il e ing add esses hese challenges by selec i ely allowing only high-
con idence p e e ch eques s. This me hod is no common and no much esea ch
has been done, on he p e e ching side, bu in [12] he e is a me hod p oposed o
da a caches e ch di ec ed p e e ching.
Con idence es ima o s a e c i ical ools in specula i e mic oa chi ec u al ech-
niques, enabling p ocesso s o assess he eliabili y o p edic ions, such as b anch
di ec ions o specula i e alues. In [10], con idence es ima o s a e de ined as mech-
anisms ha classi y p edic ions as ei he high o low con idence, balancing he
ade-o be ween inco ec specula ions and missed oppo uni ies. Key me ics
used o e alua e hei pe o mance include speci ici y (SPEC)— he p obabili y o
co ec ly iden i ying misp edic ions as low-con idence—and p edic i e alue o neg-
a i es (PVN)— he likelihood ha low-con idence p edic ions a e indeed inco ec .
These me ics a e in e sely ela ed, equi ing ca e ul uning o con idence h esholds
o op imize pe o mance o speci ic applica ions. By combining mul iple es ima o s
48
in o composi e con idence es ima o s, Jim´enez demons a es an enhanced abili y
o inely con ol specula ion, achie ing highe accu acy and lexibili y compa ed o
s andalone es ima o s. These ad ancemen s a e pa icula ly impac ul in applica-
ions like pipeline ga ing and eage execu ion, whe e specula ion con ol di ec ly
in luences ene gy e iciency and o e all p ocesso pe o mance.
Going back o he p e e ching side, his con idence es ima o s we e applied in
The p e e ch il e ing mechanism in B-Fe ch is cen e ed on dynamically assessing
he con idence o p e e ch eques s o minimize unnecessa y ope a ions. I employs
a pe -load con idence es ima ion p ocess, whe e each memo y load ins uc ion is as-
socia ed wi h a con idence sco e de i ed om i s his o ical p e e ch accu acy. This
is achie ed using h ee skewed sampling ables, each con aining 3-bi up/down sa -
u a ing coun e s. The coun e s a e inc emen ed when a p e e ch is success ul (i.e.,
he da a is used by he p og am) and dec emen ed o he wise. Du ing execu ion,
he con idence sco es om hese ables a e agg ega ed o o m a pe -load con idence
alue. I his alue alls below a p ede ined h eshold, p e e ch eques s o ha load
ins uc ion a e il e ed ou , p e en ing low-con idence p e e ches om pollu ing he
cache. The mechanism ope a es in pa allel wi h he pa h con idence es ima o , which
de e mines he eliabili y o he p edic ed execu ion pa h. Toge he , hese compo-
nen s ensu e ha only p e e ches wi h bo h high pa h and pe -load con idence a e
issued, op imizing cache u iliza ion and educing unnecessa y memo y a ic.
In conclusion, we hink ha a simila mechanism could be implemen ed o he
FTQ, his mechanism would enable o adap he p e e ching agg essi eness based on
wo kload cha ac e is ics and obse ed cache beha io . Mo eo e , o mul ico e p o-
cesso s, mo e s ic il e ing could be applied o minimize he impac o p e e ching
eques s. We expec ha i will educe cache pollu ion by elimina ing low con idence
p e e ches and inc ease ene gy e iciency and pe o mance, also om he e could be
imp o emen s on he b anch p edic o side, o example in me ap edic o s selec o s
as well. Al hough, benchma ks will need o be un and a mic oa chi ec u e will need
o be de ined.
49

4.2. Conclusions
In conclusion, we ha e been able o design, implemen and e i y he e ch a ge
queue as well as ex ac ing pe o mance esul s p o ing ha he main ad an ages
due o he use o Fe ch Di ec ed P e e che s (FDPs) ha e been achie ed. As well as
ela ing hem o he esul s ob ained by [9], whe e simila app oaches demons a ed
signi ican gains in pe o mance and esou ce u iliza ion.
A module has been implemen ed ha only needs no mo e han 32 en ies o
achie e i s maximum pe o mance, which in size would be 211 by es. Compa ed o
IPC-1 winne s [18] using 128 KB o s o age o hei p edic ion mechanism is an
excellen imp o emen in bo h a ea and ene gy e iciency. This now eed esou ces
can be used o imp o e o he pa s o he p ocesso o make each manu ac u ed
p ocesso cheape .
The pe o mance es s also show ha he FTQ mi iga es he nega i e impac
o I-cache misses by main aining high p e e ch accu acy and educing non-co e ed
misses (NCs). This was achie ed e en unde he addi ional pipeline la ency in o-
duced by he FTQ, which was shown o incu only a mino penal y compa ed o he
bene i s o sus ained p e e ching h oughpu .
The esul s u he unde sco e ha mode n b anch p edic ion me hods a e es-
sen ial o he e ec i eness o FDPs, as ini ially p oposed in [9]. By le e aging he
GHR (Global His o y Regis e ) and BTB (B anch Ta ge Bu e ), he FTQ enables
p ecise p e e ching, e en in complex pipeline scena ios, ul ima ely con ibu ing o
he o e all pe o mance imp o emen s.
This wo k con ibu es o ad ancing p ocesso design by op imizing ins uc ion
e ch mechanisms and pa ing he way o u u e enhancemen s, such as con idence
es ima o op imiza ion and u he modula in eg a ion wi hin supe scala p oces-
so s.
50
Appendix A
Tempo al Planning
A.1. Desc ip ion o asks
The asks o implemen ing a e ch-di ec ed p e e che using Agile me hodology
in ol e i e a i e de elopmen , whe e each sp in ocuses on deli e ing unc ional in-
c emen s ha p og essi ely build owa d he inal sys em. In his app oach, Agile
sp in s a e designed o g adually b eak down he complex p ocess o designing, im-
plemen ing, op imizing, and e i ying he p e e che . Each sp in includes speci ic
goals, such as basic unc ionali y, pe o mance op imiza ion, and inal deploymen ,
wi h e i ica ion asks using UVM (Uni e sal Ve i ica ion Me hodology) unning in
pa allel o ensu e co ec ness and pe o mance alida ion a each s age. UVM e -
i ica ion asks a e in eg a ed in o each sp in o ensu e ha he design mee s bo h
unc ional and pe o mance equi emen s ea ly on and h oughou de elopmen .
The use o UVM p o ides a s uc u ed and scalable way o es he p e e che unde
a ious scena ios, ca ching po en ial issues in an au oma ed ashion and ensu ing
ho ough co e age o all key ea u es and co ne cases.
This ask b eakdown helps main ain lexibili y, adap abili y, and con inuous eed-
back, which a e essen ial in bo h ha dwa e design and e i ica ion.
Sp in 1: Planning, Resea ch and Se up
Resea ch e ch-di ec ed p e e ching echniques and selec an algo i hm.
De ine sys em equi emen s and success me ics (cache hi a e, la ency).
Se up Agile ools (Ji a/T ello) and e sion con ol (Gi Hub/Gi Lab).
De elopmen en i onmen con igu a ion.
Ve i ica ion Plan c ea ion.
UVM en i onmen design and documen a ion.
Mee ings wi h u o and RTL eam.
Sp in 2: Design A chi ec u e and In e aces
Design he Fe ch Di ec ed P e e che a chi ec u e.
De ine communica ion in e aces wi h he I-cache, P oduce and consume .
51
Selec he mos e icien da a s uc u es o each case.
De elop UVM es bench a chi ec u e.
Plan basic unc ionali y es s.
Sp in 3: Ini ial P e e che Implemen a ion
Implemen he p e e che module.
W i e uni es s o unc ional alida ion.
Run simula ions o ea ly pe o mance analysis.
W i e UVM es sequences o alida e basic unc ionali y.
Plan basic unc ionali y es s.
Sp in 4: Pe o mance Tuning and Op imiza ion
W i e a comple e UVM en i onmen suppo ing pe o mance e alua ion.
Run expe imen s based on he p e iously ob ained esul s.
Op imize he p e e che module.
Sp in 5: Module alida ion and pe o mance
Run andom eg essions in UVM o ca ch e e y bug.
Run he SPEC2017 es s o compa e he pe o mance ob ained wi h eal ap-
plica ions.
Ex ac conclusions.
52
A.1.1. Es ima es and he Gan
Numbe Desc ip ion Du a ion Dependencies Roles
S1.1 Resea ch e ch-di ec ed p e e ching
echniques and selec an algo i hm
40 None E, LE
S1.2 De ine sys em equi emen s and success
me ics
20 S1.1 LE, DD
S1.3 Se up Agile ools (Ji a/T ello) and e -
sion con ol (Gi Hub/Gi Lab)
10 None E
S1.4 De elopmen en i onmen con igu a-
ion
20 None E
S1.5 Ve i ica ion Plan c ea ion 30 S1.1 E , LE
S1.6 UVM en i onmen design and docu-
men a ion
40 S1.5 E, LE
S1.7 Mee ings wi h u o and RTL eam 10 Con inuous,
None
LE, DD
Sp in 1 170
S2.1 Design he Fe ch Di ec ed P e e che
a chi ec u e
60 S1.1 LE, E
S2.2 De ine communica ion in e aces wi h
I-cache, P oduce , Consume
40 S2.1 LE, E
S2.3 Selec he mos e icien da a s uc u es 30 S2.1 LE
S2.4 De elop UVM es bench a chi ec u e 30 S1.6 E, LE
S2.5 Plan basic unc ionali y es s 20 S2.4 E
Sp in 2 180
S3.1 Implemen he p e e che module 80 S2.1 E, LE
S3.2 W i e uni es s o unc ional alida-
ion
30 S3.1 E
S3.3 Run simula ions o ea ly pe o mance
analysis
30 S3.1 E
S3.4 W i e UVM es sequences o alida e
basic unc ionali y
30 S2.4 E, LE
S3.5 Plan basic unc ionali y es s 10 S3.1 E
Sp in 3 180
S4.1 W i e a comple e UVM en i onmen
suppo ing pe o mance e alua ion
40 S2.4 E, LE
S4.2 Run expe imen s based on he p e i-
ously ob ained esul s
40 S4.1 E
S4.3 Op imize he p e e che module 40 S4.2 E
Sp in 4 120
S5.1 Run andom eg essions in UVM o
ca ch e e y bug
20 S4.1 E
S5.2 Run SPEC2017 es s o compa e pe -
o mance wi h eal applica ions
20 S4.3 E
S5.3 Ex ac conclusions 10 S5.2 LE
Sp in 5 50
To al 600
53
B.0.3. Con ingency
As wi h any p ojec , i is impo an o include a con ingency o co e obs acles
and un o eseen ci cums ances. In his case, while he p ojec in ol es esea ch wi h
inno a i e echnologies, he likelihood o encoun e ing p oblems du ing de elopmen
is no excessi ely high. The e o e, i has been decided o se a 20% con ingency o
ensu e ha any e en uali ies can be add essed.
Cos Con ingency
Lap op 120€
S a 1971€
Ques aSim license 16.8€
Table B.4: Con ingency able
B.0.4. Unexpec ed issues
In his p ojec , he likelihood o encoun e ing unexpec ed issues is ela i ely low
due o he na u e o he asks and he s abili y o he ools in ol ed. Mos p oblems
ha could a ise du ing he de elopmen p ocess would be manageable and could be
esol ed quickly wi h minimal dis up ion. Fo example, mino ha dwa e o so wa e
issues can ypically be add essed wi h s aigh o wa d ixes o eplacemen s, causing
li le o no delays.
The only a ea whe e a highe isk migh exis is in ela ion o he Ques aSim
licenses. Since Ques aSim is a specialized ool used o e i ica ion, any issues
wi h licensing—such as unexpec ed expi a ion, limi a ions on usage, o delays in
enewal—could po en ially esul in p ojec delays o addi ional cos s.
To quan i y he likelihood o hese issues, he able below p o ides an es ima ion
o he pe cen age p obabili y o encoun e ing di e en ypes o unexpec ed p oblems,
based on p ojec analysis.
I em Failu e p obabili y cos
Lap op 5% 10€
Ques aSim license 10% 200€
Table B.5: Unexpec ed issues cos s
B.0.5. To al cos
Cos To al cos
S a 9855€
De elopmen ools 684€
To al 10539€
Table B.6: To al cos
60

B.1. Managmen con ol
Once he ini ial budge is de ined, he necessa y con ol mechanisms a e es ab-
lished o a oid de ia ions, as well as nume ical indica o s ha aid in moni o ing.
Du ing he weekly mee ings, e e y ime a ask is comple ed, he budge will be
upda ed wi h he ac ual hou s spen and compa ed o he es ima ed hou s.
To manage un o eseen expenses, upon comple ion o a ask, any ex a cos s
ha ha e occu ed will also be eco ded and compa ed wi h he con ingency and
un o eseen expense o ecas . This way, any de ia ion can be quickly de ec ed, and
i can be p edic ed whe he i is necessa y o cu asks o inc ease he budge .
Below a e he nume ical indica o s o con ol:
De ia ion in pe sonnel cos pe ask:
(es ima ed cos −ac ual cos ) ×ac ual hou s
De ia ion in ask comple ion:
(es ima ed hou s −ac ual hou s) ×ac ual cos
To al de ia ion in ask comple ion:
o al es ima ed cos − o al ac ual cos
To al de ia ion in esou ces (so wa e, ha dwa e, space, o pe son-
nel):
o al es ima ed cos − o al ac ual cos
To al de ia ion in un o eseen cos s:
es ima ed un o eseen cos s −ac ual un o eseen cos s
To al de ia ion in hou s:
es ima ed hou s −ac ual hou s
61
Appendix C
Sus ainabili y epo
This sus ainabili y epo e alua es he p ojec ”Ad anced I-cache P e e che
Design o Ou -o -O de Supe scala P ocesso s” om he pe spec i e o h ee key
sus ainabili y dimensions: economic,en i onmen al, and social. These dimen-
sions p o ide a amewo k o unde s anding how he p ojec con ibu es o sus-
ainable de elopmen and i s long- e m impac . The epo conside s he esou ce
e iciency, en i onmen al oo p in , and social implica ions o he p ojec .
1. Economic Sus ainabili y
The economic sus ainabili y o his p ojec is measu ed by i s abili y o op imize
esou ce u iliza ion while p o iding long- e m economic bene i s. Se e al ac o s
con ibu e o his dimension:
Resou ce E iciency
The design o an ad anced I-cache p e e che enhances p ocesso pe o mance by
minimizing ins uc ion- e ching la ency. By imp o ing he accu acy and imeliness
o p e e ching, he p ojec educes he p ocesso ’s idle ime and dependency on
slowe memo y ope a ions. This inc eases compu a ional h oughpu and e iciency,
which ansla es in o educed ope a ional cos s, pa icula ly in high-pe o mance
compu ing en i onmen s like da a cen e s.
Cos Managemen
E icien p e e ching mechanisms educe he need o equen access o highe
memo y le els (e.g., L2 cache o main memo y), he eby lowe ing he ene gy and
mone a y cos s associa ed wi h high-la ency memo y ansac ions. The p e e che
design ocuses on using he a ailable ha dwa e esou ces op imally, hus p e en ing
he need o cos ly upg ades in memo y o p ocesso subsys ems. By using exis -
ing in as uc u e mo e e icien ly, he p ojec helps o a oid unnecessa y capi al
expendi u e.
Long-Te m Viabili y
The implemen a ion o he p e e che aligns wi h he goal o de eloping mo e e i-
cien p ocesso s ha can mee he g owing demands o compu a ional asks wi hou
62
equi ing equen ha dwa e changes. This ensu es ha in es men s in supe com-
pu ing in as uc u e a e p o ec ed, as he imp o ed pe o mance om he p e e che
will ex end he use ul li e o exis ing sys ems. In his way, he p ojec con ibu es o
he long- e m economic sus ainabili y o o ganiza ions elying on high-pe o mance
compu ing.
2. En i onmen al Sus ainabili y
The en i onmen al sus ainabili y o his p ojec e lec s i s po en ial o educe
ene gy consump ion, minimize elec onic was e, and lowe he en i onmen al impac
o p ocesso manu ac u ing.
Ene gy Consump ion
One o he p ima y goals o he I-cache p e e che is o educe p ocesso s alls
caused by ins uc ion cache misses. By an icipa ing ins uc ion e ches mo e accu-
a ely, he p ocesso can ope a e mo e e icien ly, educing he powe was ed du ing
idle cycles. As p ocesso s become mo e e icien , he o e all ene gy consump ion in
sys ems such as da a cen e s o la ge-scale compu ing acili ies dec eases. This en-
e gy educ ion is especially c i ical in en i onmen s whe e supe compu e s consume
as amoun s o powe .
En i onmen al Impac o Manu ac u ing
Al hough he ocus o he p ojec is on design and e i ica ion a he han ha d-
wa e manu ac u ing, i indi ec ly in luences he en i onmen al impac o u u e p o-
cesso s. A well-designed p e e che educes he need o la ge caches o addi ional
memo y, allowing o smalle and mo e e icien p ocesso designs. This could lead o
a educ ion in he aw ma e ials and ene gy equi ed o manu ac u ing, con ibu ing
o lowe ca bon oo p in s associa ed wi h ha dwa e p oduc ion.
E-was e Reduc ion
The p ojec ’s emphasis on enhancing p ocesso pe o mance h ough a chi ec-
u al imp o emen s ( a he han ha dwa e upg ades) helps ex end he li espan o ex-
is ing sys ems. By imp o ing he e iciency o p ocesso s h ough so wa e and ha d-
wa e design a he han eplacing en i e sys ems, he p ojec educes he u no e
o obsole e equipmen . This con ibu es o a dec ease in elec onic was e (e-was e),
which is a signi ican en i onmen al conce n globally.
3. Social Sus ainabili y
Social sus ainabili y conside s he p ojec ’s con ibu ion o socie y h ough ech-
nological inno a ion, educa ion, and b oade socie al bene i s.
Technological So e eign y
This p ojec is pa o he b oade ini ia i e o de elop Eu opean-made p o-
cesso s, p omo ing echnological independence and educing eliance on ex e nal
63
echnologies. By con ibu ing o he esea ch and de elopmen o p ocesso s op i-
mized o supe compu ing asks, his p ojec helps s eng hen Eu ope’s posi ion in
he global high-pe o mance compu ing ma ke . The ad ancemen o independen
echnology os e s job c ea ion, economic g ow h, and inno a ion wi hin he egion.
Educa ional Impac
As a Bachelo ’s hesis p ojec conduc ed a he Ba celona Supe compu ing Cen-
e (BSC), he wo k has signi ican educa ional alue. I p o ides hands-on expe-
ience in designing and e i ying ad anced mic oa chi ec u al componen s, he eby
enhancing he skills o u u e enginee s and esea che s. The p ojec also adds o
he academic body o knowledge in compu e enginee ing, speci ically in p ocesso
design and pe o mance op imiza ion, con ibu ing o he academic g ow h o bo h
he s uden and he ins i u ion.
Socie al Bene i s
The long- e m impac o his p ojec on socie y is subs an ial, especially in a eas
whe e high-pe o mance compu ing is c i ical. Fo example, as e and mo e e icien
p ocesso s enable ad ancemen s in scien i ic esea ch, clima e modeling, heal hca e
simula ions, and a i icial in elligence. These imp o emen s con ibu e o sol ing
global challenges, such as clima e change, disease p e en ion, and inno a ion in
echnology, he eby bene i ing socie y as a whole.
Conclusion
The sus ainabili y assessmen o he Ad anced I-cache P e e che Design o Ou -
o -O de Supe scala P ocesso s p ojec e eals a s ong alignmen wi h he p in-
ciples o economic, en i onmen al, and social sus ainabili y. The p ojec op imizes
esou ce usage, minimizes ene gy consump ion, and educes he need o equen
ha dwa e upg ades, he eby con ibu ing o economic and en i onmen al sus ain-
abili y. Fu he mo e, by ad ancing echnological so e eign y, p omo ing educa ion,
and enabling socie al bene i s h ough high-pe o mance compu ing, he p ojec
demons a es i s commi men o social sus ainabili y. In summa y, his p ojec ep-
esen s a aluable con ibu ion o sus ainable de elopmen in he ield o compu e
a chi ec u e.
64
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