F om Ci cui Simula ion o Ci cui Ve i ica ion:
An In e nal + Bounda y Scan-based Solu ion
Gus a o R. Al es
[email p o ec ed]
J. Ma ins Fe ei a
[email p o ec ed]
DEEC / FEUP
Rua dos B agas
4000 Po o Po ugal
Ma celo Lubaszewski
[email p o ec ed]gs.b
Ma g i Reni K ug
ma [email p o ec ed]gs.b
PPGC / UFRGS
A . Ben o Gonçal es, 9500
CEP 91501-970 Po o Aleg e
B asil
DEE / ISEP
Rua S. Tome
4200 Po o Po ugal
CPLD
M1
M2
PRODEP
.CLF Au oma ic gene a ion
o he (debug and) es
p og am
Simula ion
esul s
BSDL
.CLT
In e nal
scan
chain(s)
BSDL ile
gene a ion ool
Tool ha au oma ically
gene a es he memo y
ini ialisa ion iles
Use
op ions
Pins,
signals,
e c.
S imulae o
simula ion
S uc u al
es ec o s
(in SVF)
De elopmen
sys em
(Tes and debug
p ocesso )
(Ci cui unde
debug and es )
IEEE Eu opean Tes Wo kshop 2000
Cascais, Po ugal, May 23 d-26 h, 2000
F om Ci cui Simula ion o Ci cui Ve i ica ion:
An In e nal + Bounda y Scan-based Solu ion
Gus a o R. Al es
DEE / ISEP
Rua S. Tome
4200 Po o – Po ugal
[email p o ec ed]
Ma celo S. Lubaszewski Ma g i Reni K ug
PPGC / UFRGS
A . Ben o Gonçal es, 9500
CEP 91501-970 Po o Aleg e – B asil
[email protected] gs.b ma g i @in .u gs.b
José M. Ma ins Fe ei a
DEEC / FEUP
Rua dos B agas
4000 Po o – Po ugal
jm @ e.up.p
Abs ac
Ma ching he esul s ob ained om ci cui simula ion
wi h hose ex ac ed om ci cui unc ioning is a common
s age o he inal e i ica ion p ocess. Many cu en
e i ica ion echniques use he I/O ec o s p oduced
du ing unc ional and / o iming simula ion, o c ea ing
he es ec o s o be applied / compa ed agains he ci cui
esponses. Techniques ha a e mo e comple e include
ex ac ing he alues o in e nal sequen ial nodes and
compa ing hese using in e nal scans. This pape desc ibes
such a solu ion o e i ying digi al designs implemen ed in
cu en ly comme cial a ailable CPLDs. The es p og am
is au oma ically gene a ed om in o ma ion ha
encompasses he design & de elopmen phase, namely: he
ile con aining he esul s om simula ion, he BSDL ile,
an in e nal scan chain desc ip ion ile, and one ile
con aining he use op ions.
1. In oduc ion
Compa ing he esul s ob ained om he simula ion
phase wi h hose ex ac ed om eal ci cui beha iou is a
adi ional me hod o ci cui e i ica ion, some imes
e e ed as unc ional es . While his me hod can be
ex ended o compa ing he alues o in e nal lip- lops
(FFs), he need o expensi e es equipmen p e en s such
an app oach o small esea ch g oups wi h limi ed budge s
[1]. The p esence o a Bounda y Scan Tes (BST)
in as uc u e in cu en comme cial a ailable Complex
P og ammable Logic De ices (CPLDs) is a possible
solu ion o implemen ing a simila app oach using wo
op ional ins uc ions desc ibed in he s anda d [2] and a
chip-le el con olle o debugging & es ing boa d-le el
applica ions [3, 4]. The INTEST ins uc ion allows he
applica ion o a es ec o o inpu pins and he cap u e o
a esponse ec o s in ou pu pins, while a use -de ined
op ional ins uc ion called ‘INTSCAN’ allows cap u ing
he alues p esen in in e nal sequen ial nodes. The es
con olle named PROcesso o DEbug Pu poses
(PRODEP) is esponsible o con olling all es
ope a ions. The es p og am execu ed by PRODEP is
au oma ically gene a ed om in o ma ion ha
encompasses he design & de elopmen phase. Key poin s
o ou solu ion include: a low-cos app oach dispensing he
use o complex es equipmen , e-use o simula ion
esul s, a boa d-le el BS con olle , and use o simple in-
house so wa e ( he au oma ic es p og am gene a ion -
ATPG - ool). O he con ibu ions include: iden i ica ion o
laws in INTEST and in he BSDL ile, in wha e e s o
access h ough he TAP o in e nal scan chains.
This pape is o ganised as ollows: sec ion 2
desc ibes he es p og am gene a ion p ocess, namely he
da a low and he I/O in o ma ion. Mos o his p ocess is
ac ually de o ed o o de ing in o ma ion ex ac ed om
exis ing iles. The conside a ions on INTEST and on he
BSDL ile a e included in his sec ion. Sec ion 3 desc ibes
how he es p og am is execu ed, sec ion 4 is de o ed o
he e o de ec ion / loca ion / diagnosis p ocess, and
sec ion 5 concludes.
2. The es p og am gene a ion da a low
The da a low in he es p og am gene a ion p ocess is
illus a ed in ig. 1. Mos o he inpu in o ma ion equi ed
by he ATPG ool is p o ided om ea lie s ages o he
design & de elopmen p ocess. The ool equi es: he
simula ion esul s; he BSDL ile; a ile desc ibing he
in e nal scan chain o de ing; a ile con aining he use
op ions; and he s uc u al es ec o s (op ional).
Fig. 1: Da a low o he ATPG p ocess
The i s ile con ains a comple e desc ip ion o all he
simula ion channels used, i.e. he pins and he in e nal FFs.
In e p e ing his ile is some imes a majo p oblem, as
he e isn’ a widely used public o de ac o s anda d o i s
o ma . The one gene a ed by he MaxPlusII de elopmen
sys em [5] comes in a abula o m, in ASCII, whe e
columns co espond o ci cui signals and ows co espond
o ime momen s. The cell co esponding o a ow ( ime) –
column (signal) in e sec ion con ains he signal alue o a
pa icula ci cui loca ion in a pa icula momen .
Simula ion iles in his o ma (wi h mino a ia ions) a e
qui e common, and in ac , hey ep esen a kind o iles
ha a e easie o p ocess. In ou case, we de eloped a
simple C p og am ha pe o ms his ope a ion, p o iding
he in o ma ion needed o he ATPG ool. The BSDL ile
maps he de ice pins o he co esponding BS cells. Ou
app oach includes wo op ions: he ec o s may ei he be
applied / cap u ed h ough he BS cells o de ice, using
INTEST, o h ough he BS cells o o he de ices, using
EXTEST. The second op ion equi es addi ional
componen s o p o ide he BS cells used as es channels,
while he i s op ion has o he d awbacks. The BSDL ile
also con ains he opcodes o all ins uc ions. Cu en ly
he e is a se ious omission in his ile, namely he s anda d
does no de ine a way o p esen ing he o de ing o an
in e nal scan chain accessible h ough he TAP. This
in o ma ion has o be p o ided by a di e en ile. The use
con igu a ion ile con ains addi ional in o ma ion, namely
some op ions associa ed wi h he esou ces a ailable in ou
boa d-le el BS con olle . The las ile enables a s uc u al
es o he ci cui implemen ed in he CPLD. The ATPG
ool p ocesses he inpu in o ma ion and p oduces wo
ou pu iles co esponding o he p og ams execu ed by
each o he wo con olle s embedded in PRODEP. One
con olle (CLT) is able o con ol wo BS chains and he
o he (CLF) is able o con ol one sys em clock and se e al
gene al-pu pose I/O pins.
3. The es p og am execu ion
The wo con olle s embedded in PRODEP in e p e
he wo iles o ming he es p og am. The in e nal
s uc u e o PRODEP is desc ibed in [4], so we will
concen a e on he es p og am execu ion. The basic
p ocedu e consis s o apply one inpu ec o used du ing
simula ion; cause he de ice o ad ance one s ep in i s
ope a ion; cap u e / shi / compa e he alues p esen a
he ou pu pins and in e nal FFs. The i s ac ion consis s
o mo ing he TAP con olle o Shi -DR, shi in he es
ec o and hen mo ing o Upda e-DR. This ac ion is
simila i using INTEST plus he de ice BS cells, o
EXTEST plus he BS cells o o he de ices. The second
ac ion may be pe o med in se e al ways, acco ding o he
in o ma ion p o ided in he use op ions ile. This
in o ma ion is closely ela ed o he examples p o ided in
[2], on how a s ep-by-s ep ope a ion may be implemen ed
o in e nal es ope a ions. As one o he con olle s
embedded in PRODEP is able o con ol one sys em clock,
he use is able o choose be ween an ex e nal o in e nal
clock sou ce ( his las con olled h ough he BST
in as uc u e). The las ac ion includes wo pa s. The i s
co esponds o mo ing he TAP con olle o Cap u e-DR
(whe e he esponse o he es ec o is cap u ed), mo ing
u he o Shi -DR, and hen shi ou he cap u ed ec o .
The second pa co esponds o loading he op ional
‘INTSCAN’ ins uc ion and hen pe o ming a ci cula
shi , i.e. he alues shi ed ou o he in e nal scan chain
a e also shi ed in, so ha he scan chain con en s emain
he same. Meanwhile, he shi ed alues a e also compa ed
( h ough a mask) agains he expec ed ones, inside
PRODEP. This way, PRODEP is esponsible o he e o
de ec ion phase.
4. The de ec ion / loca ion / diagnosis p ocess
A misma ch be ween a cap u ed / expec ed alue
causes PRODEP o acknowledge e o in an ou pu pin.
The es p og am may hen be hal ed h ough condi ional
ins uc ions ha es he in e nal e o lag, o con inued up
o he end. E o loca ion is pe o med by an in-house ool
ha ex ac s he ec o s cap u ed by PRODEP ( alues
shi ed in o PRODEP a e s o ed in an ex e nal memo y)
and compa es he las wi h he co esponding expec ed
one. The nex s ep consis s o iden i ying he o ending bi ,
i.e. which alue di e s in he cap u ed ec o , in ela ion o
he expec ed one. A e he bi o de is iden i ied, he ool
combines he in o ma ion p o ided by he in e nal da a
s uc u e o loca e he o ending node. Diagnosis implies
an addi ional simula ion session. By looking in o he ime
slo whe e he e o is de ec ed, namely o he alue o he
o ending node, he use is able o iden i y possible e o
sou ces. I mo e in o ma ion is needed he use may un a
mo e speci ic simula ion session wi h co ne cases
su ounding he exac e o si ua ion, and hen gene a e
ano he es p og am. The new alues ex ac ed om he
ci cui beha iou may hen help o ind a solu ion o he
ac ual e o . This las p ocess can be epea ed se e al imes
un il he use is ce ain ha he exac e o condi ion has
been unequi ocally iden i ied and ha he en isaged
solu ion is co ec .
5. Conclusion
This pape desc ibes a low-cos me hodology o
pe o ming ci cui e i ica ion. Key poin s a e e-usabili y
o iles ha encompass he design & de elopmen phase,
e-usabili y o he BST in as uc u e o debug pu poses
(besides he adi ional p oduc ion es ), and use o easy- o-
de elop in-house applica ions.
6. Re e ences
[1] K. Holdb ook e . al., “mic oSPARCTM: A Case-S udy o Scan
Based Debug,” in p oceedings o he In e na ional Tes
Con e ence, pp. 70-75, IEEE Compu e Socie y P ess, 1994.
[2] IEEE S anda d Tes Access Po and Bounda y-Scan
A chi ec u e, Oc . 1993, IEEE S d. 1149.1 (Includes IEEE
S d. 1149.1a), ISBN 1-55937-350-4.
[3] Gus a o R. Al es, T. Ama al and J. M. Fe ei a, “Boa d-le el
P o o ype Valida ion: A Buil -in Con olle and Ex ended
BST A chi ec u e,” in p oceedings o he In e na ional
Symposium on Ci cui s and Sys ems (ISCAS), IEEE Ci cui s
and Sys ems Socie y P ess, 1999.
[4] G. Al es, “Design o Debug and Tes based on he 1149.1
and P1149.4 a chi ec u es”, PhD Thesis, FEUP, Ap . 1999.
[5] Al e a Co po a ion Web si e, h p://www.al e a.com, 1999.