E²MC: Entropy Encoding Based Memory Compression for GPUs [original]

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Lal, S., Lucas, J., & Juurlink, B. (2017). E²MC: Entropy Encoding Based Memory Compression for GPUs. In
2017 IEEE International Parallel and Distributed Processing Symposium (IPDPS). IEEE.
https://doi.org/10.1109/ipdps.2017.101
Lal, Sohan; Lucas, Jan; Juurlink, Ben
E²MC: Entropy Encoding Based Memory
Compression for GPUs
Accepted manuscript (Postprint) Conference paper |

E 2 MC: Entrop y Encoding Based Memory
Compression for GPUs
Sohan Lal, Jan Lucas, Ben Juurlink
T echnische Uni versität Berlin, German y
{sohan.lal, j.lucas, b .juurlink}@tu-berlin.de
Abstract —Modern Graphics Pr ocessing Units (GPUs) pr ovide
much higher off-chip memory bandwidth than CPUs, b ut many
GPU applications are still limited by memory bandwidth. Unf or -
tunately , off-chip memory bandwidth is gr owing slower than the
number of cores and has become a perf ormance bottleneck. Thus,
optimizations of effectiv e memory bandwidth play a signiﬁcant
role f or scaling the performance of GPUs.
Memory compression is a promising appr oach for impr oving
memory bandwidth which can translate into higher perf ormance
and energy efﬁciency . Howe ver , compression is not fr ee and
its challenges need to be addressed, otherwise the beneﬁts of
compression may be offset by its o verhead. W e propose an
entropy encoding based memory compr ession (E 2 MC) technique
f or GPUs, which is based on the well-known Huffman encoding .
W e study the feasibility of entropy encoding f or GPUs and show
that it achiev es higher compression ratios than state-of-the-art
GPU compression techniques. Furthermor e, we address the key
challenges of probability estimation, choosing an appr opriate
symbol length f or encoding, and decompression with lo w latency .
The a verage compr ession ratio of E 2 MC is 53% higher than
the state of the art. This translates into an a verage speedup
of 20% compared to no compr ession and 8% higher compared
to the state of the art. Energy consumption and ener gy-delay-
product ar e reduced by 13% and 27%, r espectively . Moreov er ,
the compression ratio achie ved by E 2 MC is close to the optimal
compression ratio gi ven by Shannon’ s source coding theor em.
I. I NTR ODUCTION
GPUs are high throughput de vices which use ﬁne-grained
multi-threading to hide the long latency of accessing of f-chip
memory [
1
]. Threads are grouped into ﬁxed size batches called
warps in NVIDIA terminology . The GPU warp scheduler
chooses a ne w warp from a pool of ready w arps if the
current warp is w aiting for data from memory . This is ef fecti ve
for hiding the memory latency and k eeping the cores b usy
for compute-bound benchmarks. Ho we ver , for memory-bound
benchmarks, all warps are usually w aiting for data from mem-
ory and performance is limited by of f-chip memory bandwidth.
Performance of memory-bound benchmarks increases when
additional memory bandwidth is provided. Figure 1 sho ws
the speedup of memory-bound benchmarks when the of f-
chip memory bandwidth is increased by 2
×
,4
×
, and 8
×
.
The a verage speedup is close to 2
×
, when the bandwidth
is increased by 8
×
. An obvious w ay to increase memory
bandwidth is to increase the number of memory channels
and/or their speed. Ho we ver , technological challenges, cost,
and other limits restrict the number of memory channels and/or
their speed [
2
], [
3
]. Moreov er , research has already sho wn
that memory is a signiﬁcant po wer consumer [
4
], [
5
], [
6
] and
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Speedup
2xBW
4xBW
8xBW
Fig. 1: Speedup with increased memory bandwidth
increasing the number of memory channels and/or frequency
ele v ates this problem. Clearly , alternati ve w ays to tackle the
memory bandwidth problem are required.
A promising technique to increase the ef fecti ve memory
bandwidth is memory compression. Ho we ver , compression
incurs ov erheads such as (de)compression latency which need
to be addressed, otherwise the beneﬁts of compression could
be of fset by its ov erhead. Fortunately , GPUs are not as latency
sensiti ve as CPUs and the y can tolerate latency increases to
some extent. Moreo ver , GPUs often use streaming workloads
with lar ge working sets that cannot ﬁt into an y reasonably
sized cache. The higher throughput of GPUs and streaming
workloads mean bandwidth compression techniques are e ven
more important for GPUs than CPUs. The dif ference in the
architectures of fers ne w challenges which need to be tackled
as well as ne w opportunities which can be harnessed.
Most existing memory compression techniques e xploit
simple patterns for compression and trade lo w compression
ratios for lo w decompression latency . For e xample, Frequent-
Pattern Compression (FPC) [
7
] replaces predeﬁned frequent
data patterns, such as consecuti ve zeros, with shorter ﬁxed-
width codes. C-Pack [
8
] utilizes ﬁxed static patterns and
dynamic dictionaries. Base-Delta-Immediate (BDI) compres-
sion [
9
] exploits v alue similarity . While these techniques can
decompress with fe w cycles, their compression ratio is lo w ,
typically only 1.5
×
. All these techniques originally tar geted
CPUs and hence, traded lo w compression for lo wer latency .
As GPUs can hide latency to a certain e xtent, more aggressi ve
entropy encoding based data compression techniques such as
Huf fman compression seems feasible. While entropy encoding
could of fer higher compression ratios, these techniques also
ha ve inherent challenges which need to be addressed. The main
challenges are 1) Ho w to estimate probability? 2) What is an
appropriate symbol length for encoding? And 3) Ho w to keep
the decompression latency lo w? In this paper , we address these

ke y challenges and propose to use
E
ntropy
E
ncoding based
M emory C ompression (E 2 MC) for GPUs.
W e use both ofﬂine and online sampling to estimate probabil-
ities and sho w that small online sampling results in compression
comparable to of ﬂine sampling. While GPUs can hide a fe w
tens cycles of additional latenc y , too man y can still degrade
their performance [
10
]. W e reduce the decompression latency
by decoding multiple code words in parallel. Although parallel
decoding reduces the compression ratio because additional
information needs to be stored, we sho w that the reduction
is not much as it is mostly hidden by the memory access
granularity (MA G). The MA G is the minimum amount of data
that is fetched from memory in response to a memory request
and it is a multiple of b urst length and memory bus width.
For e xample, the MA G for GDDR5 is either 32B or 64B
depending upon if the b us width is 32-bit or 64-bit respectiv ely .
Moreov er , GPUs are high throughput de vices and, therefore,
the compressor and decompressor should also provide high
throughput. W e also estimate the area and power needed to
meet the high throughput requirements of GPUs. In summary ,
we make the follo wing contributions:
•
W e show that entrop y encoding based memory compres-
sion is feasible for GPUs and deli v ers higher compression
ratio and performance gain than state-of-the-art techniques.
•
W e address the key challenges of probability estimation,
choosing a suitable symbol length for encoding, and
lo w decompression latency by parallel decoding with
negligible or small loss of compression ratio.
•
W e provide a detailed analysis of the ef fects of memory
access granularity on the compression ratio.
•
W e analyze the high throughput requirements of GPUs
and provide an estimate of area and po wer needed to
support such high throughput.
•
W e further show that compression ratio achie ved is close to
the optimal compression ratio gi ven by Shannon’ s source
coding theorem.
This paper is or ganized as follo ws. Section II describes
related work. In Section III we present E
2
MC in detail.
Section IV explains the e xperimental setup and e xperimental
results are presented in Section V. Finally , we draw conclusions
in Section VI.
II. R ELA TED W ORK
Frame b uf fer and texture compression ha ve been adopted
by commercial GPUs. For e xample, ARM Frame Buffer
Compression [
11
] is a v ailable on Mali GPUs. AFBC is claimed
to reduce the required memory bandwidth by 50% for graphics
workloads. NVIDIA also uses DXT compression techniques
for color compression [
12
]. Ho we ver , these techniques only
compress color and texture data and not data for GPGPU
workloads. Furthermore, the micro-architectural details of most
GPU compression techniques are proprietary .
Recent research has sho wn that compression can be used
for GPGPU workloads [
13
], [
14
], [
15
]. Sathish et al. [
13
]
use C-Pack [
8
], a dictionary based compression technique to
compress data transferred through memory I/O links and sho w
performance gain for memory-bound applications. Ho we ver ,
they do not report compression ratios and their primary focus
is to sho w that compression can be applied to GPUs and
not ho w much can be compressed. Lee et al. [
15
] use BDI
compression [
9
] to compress data in the register ﬁle. The y
observe that the computations that depend on the thread-
indices operate on register data that e xhibit strong value
similarity and there is a small arithmetic dif ference between
two consecuti ve thread re gisters. V ijaykumar et al. [
14
]u s e
underutilized resources to create assist warps that can be used
to accelerate the work of re gular warps. These assist w arps are
scheduled and ex ecuted in hardware. They use assist warps
to compress cache block. In contrast to this, our compression
technique is hardware based and is completely transparent to
the warps. The assist w arps may compete with the regular
warps and can potentially af fect the performance. Compared
to FPC, C-P A CK and BDI, we use entropy encoding based
compression which results in higher compression ratio.
Huf fman-based compression has been used for cache com-
pression for CPUs [
16
], b ut to the best of our kno wledge
no work has used Huf fman-based memory compression for
GPUs. In this work Arelakis and Stenstrom [
16
] sample the
1K most frequent v alues and use 32-bit symbol length for
compression. In contrast to CPUs, GPUs ha ve been optimized
for FP operations and 32-bit granularity does not work well
for GPUs. W e show higher compression ratio and performance
gain for 16-bit symbols instead of 32-bit in E 2 MC.
III. H UF FMAN - BA S E D M EMOR Y B AND WIDTH
C OMPRESSION
First, we provide an o vervie w of a system with entropy
encoding based memory compression (E
2
MC) for GPUs and
its ke y challenges and then in the subsequent sections address
these challenges in detail.
A. Overview
Figure 2a sho ws an ov erview of a system with main
components of the E
2
MC technique. The memory controller
(MC) is modiﬁed to integrate the compressor , decompressor and
metadata cache (MDC). Depending on the memory request type,
either it needs to pass through the compressor or it can directly
access the memory . A memory write request passes through
the compressor while a read request can bypass the compressor .
The MDC is updated with the size of the compressed block and
ﬁnally the compressed block is written to memory . A memory
read request ﬁrst accesses the MDC to determine the memory
request size and then fetches that much data from memory .
(De)compression takes place in the MC and is completely
transparent to the L2 cache and the streaming multiprocessors.
The compressed data is stored in the DRAM. Ho we v er , the
goal is not to increase the ef fecti v e capacity of the DRAM but
to increase the ef fecti ve of f-chip memory bandwidth similar
to [
13
]. Hence, a compressed block is still allocated the same
size in DRAM, although it may require less space. Like [
14
],
E
2
MC requires compression when the data is transferred from
CPU to GPU to initialize the MDC. As the (de)compressors

Comp MDC Decomp
MC
NOC
DRAM
(a) System ov ervie w
Probabilit y
Estimation
Co de
Generation
Compression
(b) Phases of en-
tropy encoding
Fig. 2: System ov erview and compression phases
are integrated in the MC, data is compressed while transferring
from CPU to GPU and vice versa.
B. Huf fman Compr ession and K ey Challeng es
Huf fman compression is based on the e vidence that not all
symbols ha ve same probability . Instead of using ﬁxed-length
codes, Huf fman compression uses v ariable-length codes based
on the relati ve frequenc y of different symbols. A ﬁx ed-length
code assumes equal probability for all symbols and hence
assigns same length codes to all symbols. In contrast to ﬁxed-
length codes, Huf fman compression is based on the principle
to use fe wer bits to represent frequent symbols and more
bits to represent infrequent symbols. In general, compression
techniques based on v ariable-length codes can provide high
compression ratio, b ut they also ha ve high ov erhead in terms
of latency , area, and power [
16
]. Moreov er , to achie ve high
compression and performance, certain ke y challenges should
be addressed.
The ﬁrst challenge is to ﬁnd an appropriate symbol length
(SL). The choice of SL is a very important factor as it af fects
compression ratio, decompression latency and hardw are cost.
W e ev aluate the tradeof fs of using dif ferent SLs (4, 8, 16, 32-
bit). The second challenge is accurate pr obability estimation .
W e perform both ofﬂine and online sampling of data to estimate
the probability of symbols and sho w that it is possible to
achie ve compression ratio comparable to of ﬂine sampling
with small online sampling. The third important factor is low
decompr ession latency , which affects the performance gain.
W e reduce the decompression latency by decoding in parallel.
In the follo wing sections, we discuss these challenges in detail.
1) Choice of Symbol Length: W e encode with dif ferent SLs
of 4, 8, 16, and 32-bit and e v aluate their tradeof fs to make sure
that not only the compression ratio b ut other aspects are also
compared. Figure 3 sho ws the compression ratio for dif ferent
SLs (Benchmarks are described in Section IV). It can be seen
that 16-bit encoding yields the highest compression ratio for
GPUs. This result is in contrast to [
16
] where it was sho wn
that 16 and 32-bit encodings yield almost same compression
ratio for CPUs. The next highest compression ratio is provided
by 8-bit symbols. For some benchmarks (TP , MUM, SPMV),
8-bit encoding of fers the highest compression ratio. GPUs often
operate on FP v alues, b ut INT v alues are also not uncommon.
Most of the benchmarks in MARS [
17
] and Lonestar [
18
]
suites are INT . Often smaller symbols are more ef fecti v e for
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Compression ratio
4
6
8 SL4
SL8
SL16
SL32
Fig. 3: Compression ratio for dif ferent symbol lengths
FP , while longer symbols are more ef fecti ve for INT and on
a verage 16-bit symbols pro vide good tradeof f for both.
2) Pr obability Estimation: Figure 2b sho ws the dif ferent
phases of an entropy encoding based compression technique.
In the probability estimation phase, frequencies of the dif ferent
symbols are collected. Based on frequencies, v ariable-length
codes are assigned to dif ferent symbols. In the ﬁnal phase,
compression takes place. Accurate probability estimation is
one of the ke y components of entropy based compression.
Therefore, in our proposed E
2
MC technique we use both of ﬂine
pr obability estimation where we estimate the probability of
symbols of ﬂine, and online pr obability estimation where we
sample the probability of symbols during runtime.
a) Of ﬂine Pr obability Estimation: W e simulate all bench-
marks and store their load and store data in a database. Then
we proﬁle the database of ﬂine to ﬁnd probability of symbols.
Of ﬂine probability estimate is the best estimate we can ha ve. In
Section V it is sho wn that of ﬂine probability yields the highest
compression ratio. Ho we ver , ofﬂine probability can only be
used if approximate entropy characteristics of a data stream
are kno wn in adv ance.
b) Online Pr obability Estimation: One of the dra wbacks
of entropy based compression techniques is that the y may
require online sampling to estimate the frequency of symbols
if entropy characteristics are not kno wn in advance. The
sampling phase is an additional ov erhead as during sampling no
compression is performed. Fortunately , our experiments sho w
that it is possible to achie ve compression ratio comparable to
of ﬂine probability with a very short online sampling phase at
the start of the benchmarks.
During sampling phase e very memory request is monitored
at the memory controller to record unique v alues and their
count. W e use a value frequenc y table (VFT) similar to [
16
]
to store them. For 4 and 8-bit SLs, we store all v alues as there
are only 16 and 256 possible v alues. Ho we ver , for SLs of 16
and 32-bit we only store the most frequent v alues (MFVs) and
use them to generate code words as the total number of v alues
is very lar ge and storing all of them is not practical.
There are two k ey decisions to mak e regarding online
sampling. First, what is the suitable number of MFVs? More
MFVs may help to encode better for some benchmarks at the
cost of increased hardware. Figure 4a sho ws the compression
ratio for dif ferent numbers of MFVs relati ve to 1K MFVs.
It sho ws that the compression ratio does not increase much
with the number of MFVs, only 1% on a verage. Only for
some benchmarks (FWT , TP , SCAN, SPMV) more MFV giv es

CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.6
0.7
0.8
0.9
1.0
1.1
Compression ratio
1K 2K 4K 8K 16K
(a) Compression ratio with dif ferent number of MFVs
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.6
0.8
1.0
1.2
1.4
1.6
1.8
Compression ratio
2.4
2.1
1.8
1M 10M 20M 30M 40M 50M 100M
(b) Compression ratio with dif ferent sampling durations
Fig. 4: Online sampling decisions
slightly higher compression ratio, FWT being the highest gainer
(6%). Hence, we choose 1K MFVs to construct encoding. In
some cases (PVR, MUM), the compression ratio can e ven
decrease with the increase in MFVs as the length of the preﬁx
which is attached to each uncompressed symbol can increase.
For e xample, for the MUM benchmark, the preﬁx is 3 bits
long for 2K MFVs and 4 bits long for 4K MFVs. Thus, the
compression ratio is lo wer for 4K MFVs compared to 2K
MFVs.Please refer to Section III-B2c for more details.
The second decision is: what is the best sampling duration?
Figure 4b sho ws the compression ratio for sampling durations of
1M, 10M, 20M, 30M, 40M, 50M and 100M instructions relati v e
to sampling duration of 1M instructions. It sho ws that sampling
for 20M instructions yields the highest compression ratio.
Hence, we choose 20M instructions for online sampling. The
longer sampling duration can improv e probability estimation,
ho we ver , there is a trade-off between compression ratio and
improv ed probability estimation as no compression is done
during sampling duration. Thus, we notice lo w compression
ratio for sampling durations longer than 20M instructions.
c) Codewor d Generation: After the sampling phase, code
generation takes place. Instead of classic Huf fman coding,
canonical Huf fman coding [
19
] is used because it is fast to
decode as the code word length is enough to decode a code word.
In canonical Huf fman coding, code words of the same length are
consecuti ve binary numbers. T o generate canonical Huf fman
code words (CHCs), ﬁrst classic code words are generated by
b uilding a Huf fman tree using a minimum heap data structure
as described in [
20
] and then symbols are sorted according to
their code lengths. The ﬁrst symbol is assigned a code word of
all zeros of length equal to the original SL. The next code word
is just the consecuti ve binary number if the SL is the same.
When a longer code word is encountered, the last canonical
code word is incremented by one and left shifted until its length
is equal to the original SL. The procedure is repeated for all
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.6
0.7
0.8
0.9
1.0
1.1
1.2
Speedup
80 40 20 10 0
(a) Ef fect of compression latency on speedup
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.6
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Speedup
80 40 20 10 0
(b) Ef fect of decompression latency on speedup
Fig. 5: Ef fect of latency
symbols. For e xample, assume we hav e three symbols (A =
(11) 2
,B=
(0) 2
,C=
(101) 2
) with classic Huf fman code words.
T o con vert them to canonical, we ﬁrst sort symbols according
to code length (B =
(0) 2
,A=
(11) 2
,C=
(101) 2
) and then the
ﬁrst symbol (B) is assigned code
(0) 2
. The CHC for the next
symbol A is
(10) 2
which is obtained by incrementing the last
code word by one and then left shifting to match the original
code length of A. Similarly , CHC for C is (110) 2 .
T o ensure that unnecessarily long codew ords are not gener -
ated, we assign a minimum probability to each symbol such
that no code word is longer than predetermined maximum
length. Our experiments sho w that there are only few symbols
which ha ve code words longer than 20-bit for SL 16 and 32-bit.
Hence, we adjust the frequency so that no symbol is assigned
a code longer than 20-bit. Similarly , for SL 4 and 8-bit we ﬁx
the maximum code word length to 8 and 16-bit, respecti vely .
Finally , all symbols that are not in MFVs are assigned a single
code word based on their combined frequenc y and this codew ord
is attached as a preﬁx to store all such symbols uncompressed.
Since we only need probability estimation and code generation
in the beginning, both of these steps can be done in softw are.
3) Low Decompr ession Latency: As already explained,
GPUs are high throughput de vices and less sensiti ve to latenc y
than CPUs. Ho we ver , large latency increases can also af fect
GPU performance. Figure 5a and 5b sho ws the speedup when
compression and decompression latency is decreased from 80
cycles to 0 c ycles, respectiv ely . It can be seen that there is a
small speedup (geometric mean of 1%) when the compression
latency is decreased to 0 c ycles. Howe ver , there is a signiﬁcant
speedup (geometric mean of 9%) when the decompression
latency is decreased to 0 c ycles. The speedup is more sensitiv e
to decompression latency because w arps ha ve to stall for loads
from memory , while stores can be done without stalling. The
results clearly sho w the importance of lo w decompression
latency . Thus, we perform parallel decoding to decrease the

DDR x BL DDR x BL
DDR1 2 DDR3/4 8
DDR2 4 GDDR5 8
T ABLE I: BL across DDR x
CR BF CR BF
1.00 - 1.33 128B 2.00 - 3.99 64B
1.33 - 1.99 96B ≥ 4.00 32B
T ABLE II: CR at MA G
decompression latency as e xplained in Section III-F1.
C. Memory Access Granularity and Compr ession
Memory access granularity (MA G) is the number of bytes
fetched from memory at a time and it is a product of the b urst
length (BL) and b us width. The BL is decided by DRAM
technology , and it directly determines the MA G. T able I sho ws
the BL for dif ferent generations of DDR
x
. The BL has increased
ov er the generations to support high data transfer rates.
The MA G is an important factor for memory compression
as it af fects the minimum amount of data that can be fetched
from memory . Assuming 32-bit bus width for DDR4, the MA G
of DDR4 is 32B. Since it is only possible to fetch in multiples
of the MA G, for a compression ratio (CR) that is not an exact
multiple of the MA G, more data needs to be fetched than what
is actually needed. For e xample, for a block that is compressed
from 128B to 65B (CR of 1.97), the actual amount of fetched
data is 96B (3
×
32B). Thus, while the CR looks very close to 2,
the ef fecti v e CR is only 1.33. Therefore, effecti ve compression
and performance gain could be signiﬁcantly less than what it
appears at ﬁrst due to MA G restrictions. T able II sho ws range
of CR and minimum number of bytes fetched (BF) assuming
32B MA G. W e assume the MA G is 32B for this study .
D. Compr ession Overhead: Metadata Cac he
T o sav e memory bandwidth as a result of compression,
we need to only fetch the compressed 32B bursts from a
DRAM. Therefore, the memory controller needs to kno w ho w
many b ursts to fetch for ev ery memory block. For GDDR5,
the number of b ursts v aries from 1 to 4. Similar to pre vious
work [
13
], [
14
], we store 2 bits for e very memory block as
metadata. For a 32-bit, 4GB DRAM with block size of 128B,
we need 8MB of DRAM for storing the metadata. Ho wev er ,
we cannot af ford to access the metadata ﬁrst from DRAM and
then issue a memory request for the required number of b ursts.
This requires two accesses to DRAM and defeats the purpose
of compression to sa ve memory bandwidth. Therefore, like
pre vious work [
13
], [
14
], we cache the most recently used
metadata in a cache. W e use a small 8KB 4-way set associate
cache to store the metadata. The 2 bits stored in the metadata
are also used to determine if the block is stored (un)compressed.
The v alue (11) 2 means the block is stored uncompressed.
E. Huffman Compr essor
Figure 6 sho ws an ov erview of the Huf fman compressor .
It can be implemented as a small lookup table (c-LUT) that
stores code words (CWs) and their code lengths (CLs) as sho wn
in Figure 6a. The maximum number of CWs is
2 N
, where
N
is the SL. As the maximum number of CWs is only 16 and
256 for SLs 4 and 8-bit, we store all CWs in a c-LUT and
index it directly using symbol bits. Ho we ver , for SLs 16 and
32-bit such a lookup table is not practical and instead we store
CW CL
Sym b
maxCL log 2 maxCL
(a) c-LUT
cw j Original CW
Extended CW
cw j
Shifted CW
(BL-WP-CL)
cw j
∨
Intermediate
buﬀer
cw i cw j ...
WP
(b) Placing code words together
Fig. 6: Huf fman compressor
1K MFVs as discussed in Section
III-B
2b. W e use an 8-way
set associati ve cache to implement c-LUT for 1K MFVs. The
cache is index ed by lower 7-bit of a symbol.
For SLs 4 and 8-bit, we b uild different Huf fman trees
corresponding to dif ferent symbols in a word and thus, also use
multiple c-LUTs, one corresponding to each tree. For e xample,
for SL 8-bit, we use 4 c-LUTs for the four dif ferent symbols
in a word. W e assume a word size of 32-bit for our study .
Once we obtain a CW from c-LUT , we need to place it
together with other CWs. Figure 6b sho ws ho w the CWs are
placed together . W e use an intermediate b uf fer of 2
×
maxCL
as b uf fer length (BL), where maxCL is the maximum code
length. T o place a CW at its right position, ﬁrst the CW is
extended to match BL and then the e xtended CW is left shifted
by
BL − WP − CL
using a barrel shifter , where WP is
the current write position in the b uf fer . Finally , the shifted
CW is bitwise ORed with the intermediate b uf fer and WP is
incremented by CL. When WP
≥
maxCL, compressed data,
equal to maxCL, is mov ed from the intermediate buf fer to the
ﬁnal b uf fer . The intermediate b uf fer is left shifted by maxCL
and WP is decremented by maxCL. Our R TL synthesis sho ws
that placing the CWs together takes more time than getting
CW and CL from c-LUT . The sum of the lengths of all CWs of
a block determines if a block is stored (un)compressed. When
the sum is
≤
96B, a block is stored compressed, otherwise
uncompressed. Please refer to Section
III-C
to understand the
reason to choose compressed size
≤
96B to decide if a block
is stored (un)compressed.
F . Huffman Decompr essor
Figure 7 sho ws an ov erview of the Huf fman decompressor .
Our design is based on the Huf fman decompressor as proposed
in [
16
], which mainly consists of a barrel shifter , comparators,
and a priority encoder to ﬁnd the CW and CL. W e use a
b uf fer of length 2
×
maxCL to store part of the compressed
block. W e use buf fer length of 2
×
maxCL instead of maxCL
as in [
16
] for two reasons. First, we can continue decoding
without shifting data e very c ycle from the compressed block
to the b uf fer . Second, it helps to deﬁne a ﬁxed-width interface
(maxCL in this case) to input compressed data instead of e very
cycle shifting a dif ferent number of bits, equal to the matched
CL. A pointer (b ufPos) which initially points to the end of the
b uf fer is used to track the ﬁlled size of the buf fer . T o ﬁnd a
CW , comparison is done in parallel between all potential CWs
and the First Code words (FCWs) of all lengths. The FCWs

Barrel shifter
...
Zeros
Compressed blo c k
≤
bufP os
maxCL
2 × maxCL
bufP os
≥
≥
...
Priorit y enco der
...
FCW(1)
FCW(2)
Shift amoun t (CL)
Matc hed CW
Extended CW
Sub
Oﬀsets
CL
maxCL
De-LUT
Sym b
maxCL
Fig. 7: Huf fman decompressor [16]
P 2 P 3 P 4 ... P n Compressed data
n parallel deco ding w a ys
Fig. 8: Structure of a compressed block
of all lengths are stored in a table. A priority encoder selects
the ﬁrst CW which is
≥
FCW of length
l
and
≤
FCW of
length
l +1
. The selected CW is extended by padding zeros
to match the maxCL. An of fset which depends on the CL and
is calculated during code generation is subtracted from CW to
obtain the index for the De-LUT . The barrel shifter shifts the
b uf fer by CL and the bufPos is decremented by CL. When the
b ufPos
≤
maxCL, the remaining compressed data of length
maxCL is shifted into the b uf fer from the compressed block
and the b ufPos is incremented by maxCL.
Although symbols are stored in consecuti ve locations in the
De-LUT , canonical CWs of different CLs are not consecuti ve
binary numbers. Therefore, the De-LUT cannot be index ed
directly using the CW to obtain the decoded symbol. W e need to
subtract an of fset from the CW to ﬁnd the index. These of fsets
are calculated during code generation. For e xample, assume
we ha ve three symbols with canonical Huf fman codew ords
(CHCs) (B =
(0) 2
,A=
(10) 2
,C=
(110) 2
). The symbol B
will be stored at index 0 in the De-LUT , so it has offset 0.
Ho we v er , A will be stored at index 1, so it has of fset 1 (
(10) 2
-
(01) 2
). Similarly , C will be stored at index 2 and it has of fset 4
(
(110) 2
-
(010) 2
). The maximum number of of fsets is equal to
maximum number of CWs of dif ferent lengths. Both of fset and
FCW tables are read and writable so that they can be changed
for dif ferent benchmarks. W e use multiple decompressor units
for dif ferent symbols in a word for SLs 4 and 8-bit.
1) P arallel Decoding and Memory Access Granularity:
W e need to decode in parallel to reduce the decompression
latency . Unfortunately , Huffman decoding is serial as the start
of the next CW is only kno wn once the pre vious CW has
been found. Serial decoding requires high latency which can
limit the performance gain. One way to parallelize Huf fman
decoding is to explicitly store pointers to CWs where we w ant
Compressor Decompresor
SL
(Bits)
Freq
(GHz)
BW
(GB/s)
Area
(
mm 2
)
Po wer
(mW)
Freq
(GHz)
BW
(GB/s)
Area
(
mm 2
)
Po wer
(mW)
4
1.67 0.84
0.02 1.43
1.11
0.56
0.01
5.12
8
1.54 1.54
0.08 4.01
0.91
0.91
0.04
11.91
16
1.43 2.86
0.11 5.47
0.80
1.60
0.07
11.89
32
1.43 5.72
0.17 9.34
0.80
3.20
0.12
14.30
T ABLE III: Frequency , bandwidth, area, and po wer of a single
unit of compressor and decompressor
Compressor Decompresor
GTX580
SL
(Bits)
Units
(#)
Area
(
mm 2
)
Po wer
(W)
Units
(#)
Area
(
mm 2
)
Po wer
(W)
Area
(%)
Po wer
(%)
4
464
7.9 0.7
692
10.3 3.6 3.4 1.7
8
252
20.3 1.0
424
18.1 5.0 7.3 2.5
16
136
14.6 0.7
240
16.4 2.8 5.8 1.5
32 68 11.5 0.6
120
14.3 1.7 4.9 0.9
T ABLE IV: #units, area, and power to support
4 ×
192.4 GB/s
to start decoding in parallel in the compressed block itself. The
number of pointers depends on the number of required parallel
decoding ways (PD Ws).
Figure 8 sho ws the structure of a compressed block. It
consists of
n − 1
pointers (
P 2
,
P 3
,
...
,
P n
) for
n
PD Ws, and
the compressed data. Each pointer consists of
N
bits where
2 N
is the block size in bytes. F or example, for a 128B block, 7-bit
are needed for each PD W . The starting codew ords for parallel
decoding are byte-aligned while compressing them. These
pointers are ov erhead and hence will reduce compression ratio.
Ho we v er , the effecti ve loss in compression ratio is usually much
lo wer due to the aforementioned memory access granularity
(MA G). Most blocks are compressed to a size that allo ws
adding extra bits for parallel decoding without reducing their
compression ratio at the MA G. Our experiments sho w that
e ven with 4 PD Ws where we store 21 extra bits (3
∗
7) in
the compressed block, there is either no or small loss in
compression ratio. W e analyze the loss in compression and the
number of PD Ws needed in Section V -A1 and V -C.
G. High Thr oughput Requir ements
T o gain from memory compression, the throughput (bytes
(de)compressed per second) of the compressor and decom-
pressor should match the full compressed memory bandwidth
(BW). Suppose we can obtain a maximum compression of
4
×
, then the compressor and decompressor throughput has to
be 4 times the GPU BW to fully utilize the compressed BW .
Unfortunately , a single (de)compressor unit cannot meet such
high throughput.
T able III shows the frequenc y , BW , area, and power of
a single compressor and decompressor unit as reported by
the Synopsis design compiler for dif ferent SLs. The BW of
NVIDIA GTX580 is 192.4 GB/s (32.1 GB/s per memory con-
troller). Ho we v er , the combined throughput of the compressor
and decompresor for any SL is f ar less than 4
×
32.1 GB/s.
For e xample, the combined throughput of the SL 16-bit is only
4.46 GB/s. Clearly , a single (de)compressor unit is not enough
and we need multiple units.
T able IV shows the total number of compressor and de-
compressor units needed to support 4
×
192.4 GB/s and the

#SMs 16 L1 $ size/SM 16KB
SM freq (MHz) 822 L2 $ size 768KB
Max #Threads per SM 1536 # Memory controllers 6
Max #CT A per SM 8 Memory type GDDR5
Max CT A size 512 Memory clock 1002 MHz
#FUs per SM 32 Memory bandwidth 192.4 GB/s
#Registers/SM 32K Burst length 8
Shared memory/SM 48KB Bus width 32-bits
T ABLE V: Baseline simulator conﬁguration
BDI FPC E
2
MC4 E
2
MC8 E
2
MC16 E
2
MC32
Compressor latency 1 6 154 84 46 24
Decompressor latency
1 10 233 143 82 42
T ABLE VI: Compressor and decompressor latency in cycles
corresponding area and po wer . The n parallel decoding ways
(n PD Ws) utilize n decompressors from these total numbers of
units to decode a single block in parallel. This only decreases
decompression latency and does not add up to the total number
of required units. Thus, no further multiplication of the numbers
sho wn in T able IV is required for n PD Ws.
T able IV also shows the total area and po wer needed as
percentage of the area and peak po wer of the GTX580. A
single (de)compressor unit requires less area and po wer for
smaller SLs. Ho we ver , the total area and power needed to
support the GTX580 BW is much higher for smaller SLs as
more units are required to meet the BW . W e ha ve smaller area
and po wer for SL 4-bit because the c-LUT and De-LUT hav e
very small number of entries (16). In general, the area numbers
are likely higher than e xpected because the memory design
library does not ha ve e xact memory designs needed to design
(de)compressor and we ha ve to combine smaller designs to
get the required size. W e believ e that a custom design will
be denser and will need less area. W e found that none of the
related work discussed throughput requirements of GPUs.
IV . E XPERIMENT AL M ETHODOLOGY
In this section, we describe our experimental methodology .
A. Simulator
W e use gpgpu-sim v3.2.1 [
21
] and modify it to integrate
BDI, FPC and E
2
MC. W e conﬁgure gpgpu-sim to simulate a
GPU similar to NVIDIA ’ s GF110 on the GTX580 card. The
baseline simulator conﬁguration is summarized in T able V.
T able VI shows the (de)compressor latencies used to e v aluate
BDI, FPC, and E
2
MC. For E
2
MC, we e v aluate four designs of
SLs 4, 8, 16, and 32-bit denoted by E
2
MC4, E
2
MC8, E
2
MC16,
and E
2
MC32, respecti vely . The latencies of the BDI and FPC
are obtained from their published papers [
9
] and [
7
]. For E
2
MC,
we wrote R TL for the compressor and decompressor designs
and then synthesized R TL using Synopsis design compiler
version K-2015.06-SP4 at 32nm technology node to accurately
estimate the frequency , area, and power . The compressor is
pipelined using two stages. The ﬁrst stage fetches the CW
and CL from the c-LUT , while the second stage combines
CWs together . W e ﬁnd that the critical path delay is in the
second stage of the compressor . The decompressor is pipelined
using three stages. The ﬁrst stage ﬁnds a CW , the second
stage calculates the index for the De-LUT using CW and
Name Abbre v . Data T ype Origin
con volSeparable CS Single-precision FP CUD A SDK
fastW alshT rans FWT Single-precision FP CUD A SDK
libor LIB Single-precision FP CUD A SDK
transpose TP Single-precision FP CUD A SDK
scan SCAN INT CUD A SDK
PageV iewCount PVC INT MARS
PageV iewRank PVR INT MARS
backprop BP Single-precision FP Rodinia
bfs BFS1 INT Rodinia
heartwall HW Mixed Rodinia
kmeans KM1 Mixed Rodinia
mummergpu MUM INT Rodinia
bfs BFS2 INT Lonestar
sssp SSSP INT Lonestar
spmv SPMV Mixed SHOC
T ABLE VII: Benchmarks used for experimental e v aluation
of fsets, and the De-LUT is accessed in the third stage to get
the decoded symbol. W e ﬁnd that the critical path delay is
in the ﬁrst stage of the decompressor . In E
2
MC, one symbol
can be (de)compressed in a single cycle of frequenc y listed in
T able III. The frequency is calculated using critical path delay .
Ho we ver , the DRAM frequency is 1002 MHz for GTX580.
W e scale the (de)compressor frequency and then count the
number of cycles needed to (de)compress a memory block
of size 128B. Furthermore, for each PD W , we assume the
decompressor latency is decreased by the same f actor .
For estimating the ener gy consumption of different bench-
marks, GPUSimPo w [
5
] is modiﬁed to integrate the po wer
model of the compressor and decompressor . The po wer numbers
obtained by R TL synthesis are used to deriv e the power model
for the compressor and decompressor .
B. Benchmarks
T able VII shows the benchmarks used for e valuation. W e
include benchmarks from the popular CUD A SDK [
22
],
Rodinia [
23
], Mars [
17
], Lonestar [
18
], and SHOC [
24
]. A
benchmark can belong to single-precision FP , INT , or mix ed
category depending upon its data types. W e modiﬁed the inputs
of SCAN and FWT benchmarks as the original inputs were
random which are not suitable for any compression technique.
W e use SCAN for stream compaction which is an important
application of SCAN and FWT to transform W alsh functions.
V. E XPERIMENT AL R ESUL TS
T o ev aluate the ef fecti veness of E
2
MC, we compare compres-
sion ratio (CR) and performance of E
2
MC for SLs 4, 8, 16, and
32-bit with BDI and FPC. W e provide two kinds of compression
ratios, raw CR and CR at memory access granularity (MA G).
The raw CR is the ratio of the total uncompressed size to total
compressed size. For CR at MA G, the total compressed size is
calculated by scaling up the compressed size of each block to
the nearest multiple of MA G, and then adding all the scaled
block sizes.
First, we present CR results using of ﬂine and online
probability estimation and discuss CR and parallel decoding
tradeof f. W e then compare the speedup of E
2
MC with BDI
and FPC and sho w the importance of decoding in parallel.

CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Compression ratio
4 68
BDI FPC E 2 MC4 E 2 MC8 E 2 MC16 E 2 MC32
(a) Raw compression ratio
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Compression ratio
BDI FPC E 2 MC4 E 2 MC8 E 2 MC16 E 2 MC32
(b) Compression ratio at MA G
Fig. 9: Compression ratio of BDI, FPC and E 2 MC
Finally , we present the sensiti vity analysis of compute-bound
benchmarks to E
2
MC and study the ener gy ef ﬁciency of E
2
MC.
A. Compr ession Ratio using Of ﬂine Pr obability
Figure 9a depicts the raw CR of BDI, FPC, and E
2
MC with
of ﬂine probability . It sho ws that on av erage E
2
MC provides
higher CR than BDI and FPC for all SLs. The geometric
mean of the CR of E
2
MC for SLs 4, 8, 16 and 32-bit is
1.55
×
, 1.80
×
, 1.97
×
, and 1.76
×
, respecti vely , while that of
BDI is only 1.44
×
and FPC is 1.53
×
. This sho ws that entropy
based compression techniques provide higher CR than simple
compression techniques such as BDI and FPC whose CR is
limited. E
2
MC16 yields the highest CR which is 53% and 42%
higher than the CR of BDI and FPC respecti vely .
As discussed in Section
III-C
, data from memory is fetched
in the multiple of MA G. Figure 9b sho ws the CR of BDI,
FPC and E
2
MC when this is taken into account. W e see that
the CR of all three techniques at MA G is less than the raw
CR. Ho we ver , the CR of E
2
MC is still higher compared to
BDI and FPC. The geometric mean of the CR of E
2
MC for
SLs 4, 8, 16 and 32-bit is 1.36
×
, 1.53
×
, 1.62
×
, and 1.45
×
,
respecti vely , while the CR of BDI is only 1.24
×
and the CR
of FPC is 1.34
×
. W e see that E
2
MC16 also yields the highest
CR at MA G. So, we select E
2
MC16 and sho w CR results only
for it and lea ve out other SLs for space reasons.
T o obtain an estimate how close E
2
MC16 is to the optimal
CR, we calculate the upper bound on CR using Shannon’ s
source coding theorem [
25
]. The a verage optimal CR for SL
16-bit is 2.61
×
, which means there is a gap of 64% that could
be further exploited. Ho we ver , we think that further narrowing
the gap is dif ﬁcult as compression is data dependent.
1) Compr ession Ratio and P arallel Decoding T radeof f:
As sho wn in the Section
III-B
3, lo w decompression latency
is important for achie ving high performance. T o reduce the
decompression latency we decode in parallel as discussed in
the Section
III-F
1. Ho we ver , parallel decoding is not for free
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Compression ratio
6.0
5.8
5.5
4.7
BDI FPC E 2 MC16-PDW1 E 2 MC16-PD W2 E 2 MC16-PDW4 E 2 MC16-PD W8
(a) Raw compression ratio
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Compression ratio
BDI FPC E 2 MC16-PDW1 E 2 MC16-PD W2 E 2 MC16-PDW4 E 2 MC16-PD W8
(b) Compression ratio at MA G
Fig. 10: Compression ratio of E
2
MC16 with parallel decoding
as it decreases the CR. Hence, the number of parallel decoding
ways (PD Ws) needs to be selected in a way such that the
performance gain is maximal and the loss in CR is minimal.
Figure 10a sho ws that the CR decreases slightly when the
number of PD Ws increases. Howe ver , we will see in the
Section
V- C
, the performance increases with the number of
PD Ws as the decompression latency decreases. Moreov er , we
see from the Figure 10a that the CR of E
2
MC16 e ven for 8
PD Ws is still much higher than the CR of BDI and FPC.
W e hav e seen that parallel decoding causes loss in CR.
Ho we ver , the loss in CR at MA G is much lo wer than the
loss in raw CR as sho wn in Figure 10b than Figure 10a. For
example, there is 9% loss in ra w CR with 4 PDWs, while at
MA G it is only 4%. The reason for lo wer CR loss at MA G
is that at MA G we usually need to fetch some extra bytes to
meet the MA G requirements. Using these extra bytes to store
of fsets for parallel decoding does not cause loss in CR. This
is not alw ays true, ho we ver , and hence we see some loss in
CR e ven at MA G.
B. Compr ession Ratio using Online Sampling
As discussed in the Section
III-B
2b online sampling might
be needed to estimate probability if entropy characteristics are
not kno wn in adv ance. Figure 11a sho ws the CR for online
sampling size of 20M instructions. W e choose 20M instructions
for online sampling as it gi ves the highest CR as sho wn in
the Figure 4b and we only sample at the beginning of each
benchmark. The CR of E
2
MC16 is 1.79
×
, which is 35% and
26% higher than the CR of BDI and FPC, respecti vely . Howe ver ,
as expected the CR with online sampling is lo wer by 18% on
a verage than that of of ﬂine sampling.
Figure 11b sho ws the CR with online sampling at MA G.
The CR of E
2
MC16 at MA G is 1.52
×
, which is still 28% and
18% higher than BDI and FPC, respecti vely . The CR results
sho w that it is possible to achie ve reasonably higher CR with

CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Compression ratio
BDI FPC E 2 MC16-PDW1 E 2 MC16-PD W2 E 2 MC16-PDW4 E 2 MC16-PD W8
(a) Raw compression ratio
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
Compression ratio
BDI FPC E 2 EMC16-PDW1 E 2 MC16-PD W2 E 2 MC16-PDW4 E 2 MC16-PD W8
(b) Compression ratio at MA G
Fig. 11: Compression ratio of BDI, FPC and E
2
MC16 for
online sampling size of 20M instructions
small online sampling. Ho we ver , the CR at MA G with online
sampling is 10% lo wer than of ﬂine sampling.
C. Speedup
W e ﬁrst establish an upper bound on the speedup assuming
fa vorable conditions and then use realistic conditions to
study the actual gain. Figure 12a sho ws the speedup of BDI,
FPC, and E
2
MC16 when of ﬂine probability is used and the
(de)compression latency is only one c ycle for all techniques.
BDI and FPC achie ve an a verage speedup of 12% and 16%,
respecti vely , while the av erage speedup of E
2
MC is 16%, 21%,
23%, and 16% for SLs 4, 8, 16, and 32-bit, respecti vely . The
speedup is due to the decrease in DRAM bandwidth which is
reciprocal of the achie ved compression ratio.
Figure 12b and Figure 12c sho ws the speedup of BDI, FPC
and E
2
MC16 for of ﬂine and online sampling with realistic
latencies as sho wn in the T able VI. For E 2 MC we only sho w
speedup in detail for SL 16-bit with 1 to 8 PD Ws because
of the space reasons. A brief discussion of the speedup for
SL 4, 8, and 32-bit is presented later in the section. W e see
that the speedup is less for FPC and E
2
MC16 using realistic
latencies. Ho we ver , the speedup of BDI does not change as
actual latency is also single c ycle. The speedup of E
2
MC16 with
of ﬂine probability (13%) is equal to the speedup of FPC (13%)
and e ven slightly less with online probability (11%) when no
parallel decoding is used, e ven though the CR of E
2
MC16
is much higher than that of FPC. This is because without
parallel decoding the decompression latency of E
2
MC16 is 82
cycles, which is much higher than the decompression latency
of FPC which is 10 cycles. The speedup increases when we
increase the PD Ws from 1 to 4 because each PDW decreases
the decompression latency by half. Ho we ver , each PDW also
decreases the CR as we need to store the of fsets for parallel
decoding and hence there is a tradeof f between the CR and
performance gain. Figure 12b sho ws that there is no further
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.6
0.8
1.0
1.2
1.4
1.6
Speedup
BDI FPC E 2 MC4 E 2 MC8 E 2 MC16 E 2 MC32
(a) Of ﬂine sampling with single cycle latenc y
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.6
0.8
1.0
1.2
1.4
1.6
Speedup
BDI FPC E 2 MC16-PDW1 E 2 MC16-PD W2 E 2 MC16-PDW4 E 2 MC16-PD W8
(b) Of ﬂine sampling with realistic latency
CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.6
0.8
1.0
1.2
1.4
1.6
Speedup
BDI FPC E 2 MC16-PDW1 E 2 MC16-PD W2 E 2 MC16-PDW4 E 2 MC16-PD W8
(c) Online sampling with realistic latency
Fig. 12: Speedup of BDI, FPC and E 2 MC
gain in performance from 4 PD Ws to 8 PDWs. This is because
the increase in performance due to further decrease in latency
is nulliﬁed by the decrease in CR. Hence, to achie ve higher
speedup for E
2
MC16 we not only need higher CR b ut also the
decompression latency has to be reasonably lo w .
Figure 12a sho ws that the a verage speedup of E
2
MC for SL
8-bit with single cycle latenc y is much higher than the speedup
of BDI and FPC and close to the speedup for SL 16-bit. The
speedup for SLs 4 and 32-bit is also higher or equal to BDI
and FPC. Ho we ver , when actual latency is used the av erage
speedup is much lo wer . The av erage speedup of E
2
MC for
SLs 4, 8-bit with 8 PD Ws and for SL 32-bit with 4 PD Ws is
2%, 14% and 15% respecti vely . The reason for low speedup
for SLs 4, and 8-bit is their high decompression latency .
W e see that both ofﬂine and online sampling results in higher
performance gain for E
2
MC16 than BDI and FPC, provided
decompression latency is reduced by parallel decoding. The
geometric mean of the speedup of E
2
MC16 with 4 PD Ws
is about 20% with of ﬂine probability and 17% with online
probability . The av erage speedup is 8% higher than the state
of the art with of ﬂine and 5% higher with online sampling.
D. Sensitivity Analysis of Compute-Bound Benchmarks
W e conduct sensitivity analysis to v erify that E
2
MC increases
performance of the memory-bound benchmarks without hurting
the performance of the compute-bound benchmarks. The

CS
FWT
LIB
TP
SCAN
PVC
PVR
BP
BFS1
HW
KM1
MUM
BFS2
SSSP
SPMV
GM
0.0
0.2
0.4
0.6
0.8
1.0
1.2
Energy and EDP
Base E-OFF EDP-OFF E-ON EDP-ON
Fig. 13: Energy and EDP of E
2
MC16 for of ﬂine and online
sampling ov er baseline
compute-bound benchmarks do not gain from increase in
bandwidth and we compress them using E
2
MC16. On a verage
there is only 1% reduction in performance for 1 PD W due
to high decompression latency . Howe ver , we propose to use
4 PD Ws and we notice no decrease in performance of the
compute-bound benchmarks at 4 PD Ws.
E. Effect on Ener gy
Figure 13 sho ws the reduction in ener gy consumption and
ener gy-delay-product (EDP) ov er no compression for E
2
MC16
for of ﬂine and online sampling. On av erage there is 13%
and 27% reduction in ener gy consumption (E-OFF) and EDP
(EDP-OFF) respecti vely , for ofﬂine sampling and 11% and 24%
reduction in ener gy consumption (E-ON) and EDP (EDP-ON)
respecti vely , for online sampling. E
2
MC16 reduces the ener gy
consumption by reducing the of f-chip memory traf ﬁc and total
ex ecution time. W e sho w ener gy and EDP of E
2
MC only ov er
no compression due to lack of po wer models for BDI and FPC.
VI. C ONCLUSIONS
Most pre vious compression techniques were originally
proposed for CPUs and hence, these techniques tradeof f lo w
compression for lo w latency by using simple compression
patterns. Ho we v er , GPUs are less sensitiv e to latency than CPUs
and they can tolerate increased latenc y to some extent. Thus,
we studied the feasibility of relati vely more comple x entropy
encoding based memory compression (E
2
MC) technique for
GPUs which has higher compression potential, b ut also
higher latency . W e sho wed that E
2
MC is feasible for GPUs
and deli vers higher compression ratio and performance gain.
W e addressed the key challenges of probability estimation,
choosing an appropriate symbol length, and decompression
with reasonably lo w latency . E
2
MC with of ﬂine sampling results
in 53% higher compression ratio and 8% increase in speedup
compared to the state-of-the-art techniques and sav es 13%
ener gy and 27% EDP . Online sampling results in 35% higher
compression ratio and 5% increase in speedup compared to
the state of the art and sa ves 11% ener gy and 24% EDP . W e
also provided an estimate of the area and po wer needed to
meet the high throughput of GPUs. In the future we plan to
study the ef fect of multiple encodings and extend E
2
MC to
other le vels of the memory hierarchy .
VII. A CKNO WLEDGMENTS
This work has recei ved funding from the European Union’ s
Horizon H2020 research and innov ation programme under grant
agreement No. 688759 (Project LPGPU2).
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