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DOI: 10.5281/zenodo.17288071
RADNEXT T ansna ional Access Summa y Repo
P ojec i le
Faul Resilience Analysis o he Dynamic-TMR RISC-V Faul
Tole an Mic op ocesso Design
P ojec TA iden i ie
TA12-378
Gene al applica ion
Space, high- eliabili y g ound le el
Type o es
SEE
G oup leade , Ins i u e
Ma cello Ba bi o a, Sapienza Uni e si y o Rome
Co-au ho s, Ins i u es
Ma co Angioli, Mau o Oli ie i, An o nio Mas and ea
Da e(s) o he expe imen
24/06/2025 – 25/06/2025
Facili y
HollandPTC
Amoun o access g an ed
8 h
Objec i es o he expe imen s
Faul Tole ance (FT) ensu es con inuous ope a ion despi e aul s by enabling isola ion and eco e y
wi hou sys em ailu e. G owing in e es in FT-COTS embedded mic op ocesso s has led o a ious
s udies o e he yea s es ing FPGAs unde di e en adia ion injec ion acili ies. While cu en FPGA
echnologies can be cha ac e ized wi h nea -accu acy, mos designs implemen ed on hem s ill ely on
adi ional edundancy me hods, like empo al o spa ial edundancy, wi hou in oducing new
inno a ions.
In his s udy, we p opose in es iga ing he aul eliabili y o an inno a i e app oach in ol ing a
mic oa chi ec u e In e lea e Mul i-Th eading (IMT) RISC-V design capable o dynamically swi ching
om Dual Modula Redundancy (DMR) o T iple Modula Redundancy (TMR) in case o aul s.
This p oposal i s he as scena io o mic op ocesso de ices o FT COTS embedded applica ions,
ha ing as i s basis he i s de ailed exploi a ion o he In e lea e Mul i-Th eading (IMT) execu ion
scheme o implemen ing aul ole an p ocesso s on FPGA.
This wo k ills a gap in he li e a u e by analyzing he FT po en ial o IMT a chi ec u es:
• I alida es and demons a es he FT ad an age o he p oposed Dynamic-TMR me hod o e exis ing
locks ep echniques by unc ioning as a DMR-locks ep dual co e. This app oach a oids he o e head
o duplica ing all ha dwa e and aims o signi ican ly educe checkpoin ing and ollback ou ines.
• I quan i ies he e iciency o he echnique h ough ex ensi e FI campaigns unde adia ion
condi ions, showing ha he esilience achie able is compa able o a locks ep dual co e. This makes
he me hod sui able o sys ems wi h high aul a es o c i ical applica ions.
• I compa es he implemen a ion inside he Klessyd a-d T03 a chi ec u e wi h he unp o ec ed e sion
and he p o ec ed Bu e ed TMR Klessyd a- T03 co e, alida ing he IMT FT app oaches ac oss he
Klessyd a amily and pa ing he way o u u e compa isons wi h o he RISC-V FT p ocesso s.
• The signi icance o his wo k lies in i s po en ial o p oduce Failu e P obabili y da a compa able wi h
esul s om Single-E en -Upse aul injec ion es s, use ul o me ics such as Mean-Time- o-Failu es
EDMS 3355743 .1 s a us In Wo k access Res ic ed
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(MTTF), Mean-Wo k- o-Failu es (MWBF), A chi ec u al-Co ec -Execu ion (ACE) bi s, and
A chi ec u al-Vulne abili y-Fac o (AVF).
The o e all app oach e lec s he es s p e iously conduc ed a PSI’s P o on I adia ion Facili y.
Al hough FT p ocesso s a e ideally es ed wi h hea y ions ha simula e space condi ions, we chose o
epea hese es s using he same p o on sou ces. This pe mi s a clea compa ison wi h ea lie da a
and ela ed esea ch on RISC-V p ocesso s wi h p o on adia ion. P o on es ing was selec ed due o
he limi ed exis ing li e a u e, which p edominan ly ocuses on hea y ions o neu ons.
Expe imen es epo
The es s we e ca ied ou on di e en FPGA boa ds, numbe ed 1, 3, 4, and 5, om he same FPGA
amily, Xilinx A ix7, on a CMODA7 Digilen Boa d.
Fi s , he beam was calib a ed wi h High ene gy = 70 MeV wi h he ollowing luence and lux:
Cu en = 3nA - lux= 1,22x10^7 p/cm^2/s - luence = 1,43x10^9 p/cm^2
Cu en = 21nA - lux= 8,55x10^7 p/cm^2/s - luence = 1x10^10 p/cm^2
Cu en = 7nA - lux= 2,85x10^7 p/cm^2/s - luence = 3,3x10^9 p/cm^2
Cu en = 14nA - lux= 5,70x10^7 p/cm^2/s - luence = 6,67x10^9 p/cm^2
Cu en = 17nA - lux= 6,92x10^7 p/cm^2/s - luence = 3,32x10^9 p/cm^2
Cu en = 10nA - lux= 4,07x10^7 p/cm^2/s - luence = 1,95x10^9 p/cm^2
Cu en = 13nA - lux= 5,29x10^7 p/cm^2/s - luence = 2,54x10^9 p/cm^2
Second, we se up he en i onmen by pu ing he DUT unde he Beam and connec ing i o i s con ol
boa d, as shown in he image below.
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A e a ew simple uns, he beam con ol so wa e and he con ol boa d manually synch onized each
es o he ac i a ion o deac i a ion o bo h he boa d and he beam, leading o da a eadback om he
FPGA.
The 8 hou s we e di ided in o 2 di e en es campaigns o he wo di e en days, each wi h di e en
uns o each design e sion (T03 and d T03). In pa icula , we e ca ied ou :
Day1 70MeV
7 uns o d T03 -> 3nA -> Boa d n°1
12 uns o d T03 -> 21nA -> Boa d n°1
7 uns o d T03 -> 3nA -> Boa d n°3
8 uns o d T03 -> 21nA -> Boa d n°3
Day2 70MeV
4 uns o d T03 -> 14nA -> Boa d n°3
10 uns o d T03 -> 17nA -> Boa d n°3
10 uns o T03 -> 10nA -> Boa d n°5
9 uns o T03 -> 13nA -> Boa d n°5
10 uns o T03 -> 17nA -> Boa d n°4
10 uns o T03 -> 10nA -> Boa d n°4
12 uns o T03 -> 13nA -> Boa d n°4
A he beginning o each es , golden uns we e ca ied ou o di ec compa ison wi h subsequen
aul ed uns. Mo eo e , be o e and a e each un, bi s eam eadback was pe o med o bi
compa ison and e o checkou . The inal 99 collec ed es s will be subjec ed o pos -p ocessing
analysis and ca aloguing o he esul s.
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