In e na ional J
ou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1,
DOI : 10.5121/ lsic.2011.2105
O
PTIMIZATION TECHNIQU
FOLLOWER BASED
HIGH SPEED WIRELESS
Manoj Kuma
1
Depa men o
Elec onics & Comm., Vidya College o Engg., Mee u (U.P)
2
Depa men o
Elec onics & Comm., NIT Hami pu , Hami pu (H.P)
A
BSTRACT
Since he cu en demand o high
-
need o ack and hold ampli ie s (T&H) ope a ing a RF equencies. A
ci cui is he key elemen in any mode n wideband da a acquisi ion sys em. Applica ions like a cable
o a b oad a ie y o di e en adio s anda ds equi e high p ocessing speeds wi h high esolu ion. The
ack-and-hold (T&H) c
i cui is a undamen al block o analog
allows mos dynamic e o s o A/D con e e s o be educed, especially hose showing up when using
high equency inpu signals. Ha ing a wideband and p ecise acquisi ion sys em
oday’s end owa ds mul i-
s anda d lexible adios, wi h as much signal p ocessing as possible in
digi al domain.
This wo k in es iga es e ec o a ious design schemes and ci cui opology o ack
and-hold ci cui o achie e acc
ep able linea ly, high slew a e, low powe consump ion and low noise
K
EYWORDS
T ack and Hold Ci cui
, Low Powe Consump ion, Slew Ra e,
Analog o Digi al Con e e
1.
I
NTRODUCTION
T ack and hold ci cui is he undam
and hold ci cui is inse ed in on o a compa a o a ay o a lash A/D con e e o keep
compa a o ’s inpu ol ages cons an while he compa a o s a e se ling hei ou pu ol age
le els. T ac
k and hold a chi ec u e can be classi ied in o wo classes ( ig.1): open
closed-loop a chi ec u e [1]-[5].
Figu e 1a. Open-
loop T/H
The open loop T/H ci cui is sui able o high p ecision bu no
T/H ci cui s p oposed/implemen ed so a employ closed
8 bi accu acy. Howe e closed loop a chi ec u es su e om ela i ely lowe sampling
equency and highe powe consump ion as compa
ou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1,
Ma ch
PTIMIZATION TECHNIQU
ES FOR SOURCE
FOLLOWER BASED
TRACK
-
AND
-
HOLD CIRCUIT FOR
HIGH SPEED WIRELESS
COMMUNICATION
Manoj Kuma
1
and Gagnesh Kuma
2
Elec onics & Comm., Vidya College o Engg., Mee u (U.P)
[email p o ec ed]
Elec onics & Comm., NIT Hami pu , Hami pu (H.P)
[email p o ec ed]
-
esolu ion and as analog o digi al con e e s (ADC) is d i ing he
need o ack and hold ampli ie s (T&H) ope a ing a RF equencies. A
e y as and linea T&H
ci cui is he key elemen in any mode n wideband da a acquisi ion sys em. Applica ions like a cable
o a b oad a ie y o di e en adio s anda ds equi e high p ocessing speeds wi h high esolu ion. The
i cui is a undamen al block o analog
-
o digi al (A/D) con e e s. I s use
allows mos dynamic e o s o A/D con e e s o be educed, especially hose showing up when using
high equency inpu signals. Ha ing a wideband and p ecise acquisi ion sys em
is a p e equisi e o
s anda d lexible adios, wi h as much signal p ocessing as possible in
This wo k in es iga es e ec o a ious design schemes and ci cui opology o ack
ep able linea ly, high slew a e, low powe consump ion and low noise
, Low Powe Consump ion, Slew Ra e,
Peak Powe , Sampling
S
T ack and hold ci cui is he undam
en al block o analog o digi al (A/D) con e e s. T ack
and hold ci cui is inse ed in on o a compa a o a ay o a lash A/D con e e o keep
compa a o ’s inpu ol ages cons an while he compa a o s a e se ling hei ou pu ol age
k and hold a chi ec u e can be classi ied in o wo classes ( ig.1): open
loop T/H
Figu e 1b. Closed-
loop T/H
The open loop T/H ci cui is sui able o high p ecision bu no
o high speed. Mos CMOS
T/H ci cui s p oposed/implemen ed so a employ closed
-
loop a chi ec u e o ob ain be e han
8 bi accu acy. Howe e closed loop a chi ec u es su e om ela i ely lowe sampling
equency and highe powe consump ion as compa
ed o open-
loop a chi ec u e [6]. Open
Ma ch
2011
45
ES FOR SOURCE
HOLD CIRCUIT FOR
COMMUNICATION
Elec onics & Comm., Vidya College o Engg., Mee u (U.P)
Elec onics & Comm., NIT Hami pu , Hami pu (H.P)
esolu ion and as analog o digi al con e e s (ADC) is d i ing he
e y as and linea T&H
ci cui is he key elemen in any mode n wideband da a acquisi ion sys em. Applica ions like a cable
-TV
o a b oad a ie y o di e en adio s anda ds equi e high p ocessing speeds wi h high esolu ion. The
o digi al (A/D) con e e s. I s use
allows mos dynamic e o s o A/D con e e s o be educed, especially hose showing up when using
is a p e equisi e o
s anda d lexible adios, wi h as much signal p ocessing as possible in
This wo k in es iga es e ec o a ious design schemes and ci cui opology o ack
-
ep able linea ly, high slew a e, low powe consump ion and low noise
.
S
wi ch, Flash
en al block o analog o digi al (A/D) con e e s. T ack
and hold ci cui is inse ed in on o a compa a o a ay o a lash A/D con e e o keep
compa a o ’s inpu ol ages cons an while he compa a o s a e se ling hei ou pu ol age
k and hold a chi ec u e can be classi ied in o wo classes ( ig.1): open
-loop and
loop T/H
o high speed. Mos CMOS
loop a chi ec u e o ob ain be e han
8 bi accu acy. Howe e closed loop a chi ec u es su e om ela i ely lowe sampling
loop a chi ec u e [6]. Open
-
In e na ional J
ou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1,
loop a chi ec u es end o consume lowe powe and wo k a high sampling equencies han
closed-loop ones. Open-loop
a chi ec u es ha e been used
Sou ce- ollowe -
based T/H ci cui has be
speed and powe consump ion.
This pape in es iga es e ec o a ious design schemes and
ci cui opology o ack-and-
hold ci cui o achie e accep able linea ly, high slew a e, low
powe consump ion a
nd low noise. Supe io speed &
makes i p omising candida e o he pu pose o his wo k.
2.
SAMPLING SWITCHES FO
The sampling ne wo k consis s o a sampling swi ch (M
alue o sampled signal du ing he hold mode. Du ing he acking phase, he combina ion o
he swi ch and he capaci o o ms a i s
maximum achie able sampling equency. The speed o sampling ne wo
se ious limi a ion in his wo k because as will be seen he chosen ope a ing equency is a less
han he ime-
cons an o he swi ch ne wo k and is basically limi ed by o he pa s o he
ci cui [15].
The noise con ibu ion du
e o he sampling ne wo k is dependen on he sampling capaci ance
alue and he wid h o he swi ching ansis o . In addi ion o he noise added by he swi ch, he
non-linea i y due o he signal
-
linea i y o he T/H ci cui .
2.1. Single MOS Swi ch
The maximum ou pu ol age ha an NMOS ansis o can deli e is app oxima ely equal o
V
dd
-V
h.
Figu e 2.
Single MOS sampling swi ch
The on- esis ance o a long-
channel MOS de ice ope a ing in he linea ( iode) egions is gi en
by:
F om he abo e exp ession i is clea ha he esis ance o NMOS
a
pp oaches in ini y when Vin app oaches Vdd
ansis o [10].
2.2. T ansmission-
Ga e Swi ch
To ci cum en he abo e p oblem wi h a a ying swi ch esis ance he bene i o NMOS o
low inpu ol ages and he PMOS o
connec ing hem in pa allel and he eby o ming a ansmission ga e
ou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1,
Ma ch 2011
loop a chi ec u es end o consume lowe powe and wo k a high sampling equencies han
a chi ec u es ha e been used
in high-
speed ADCs [3][4].
based T/H ci cui has be
en op imized wi h espec o linea i y, noise, and
This pape in es iga es e ec o a ious design schemes and
hold ci cui o achie e accep able linea ly, high slew a e, low
nd low noise. Supe io speed &
accep able linea i y o sou ce
makes i p omising candida e o he pu pose o his wo k.
SAMPLING SWITCHES FO
R T
/
H
The sampling ne wo k consis s o a sampling swi ch (M
sw
) and a hold capaci o (C
s
) o s o e he
alue o sampled signal du ing he hold mode. Du ing he acking phase, he combina ion o
he swi ch and he capaci o o ms a i s
-o de RC ne wo k, he ime-
cons an o which se s he
maximum achie able sampling equency. The speed o sampling ne wo
k appea s no o be a
se ious limi a ion in his wo k because as will be seen he chosen ope a ing equency is a less
cons an o he swi ch ne wo k and is basically limi ed by o he pa s o he
e o he sampling ne wo k is dependen on he sampling capaci ance
alue and he wid h o he swi ching ansis o . In addi ion o he noise added by he swi ch, he
-
dependen beha iou o he swi ch can deg ade he o e all
The maximum ou pu ol age ha an NMOS ansis o can deli e is app oxima ely equal o
Single MOS sampling swi ch
channel MOS de ice ope a ing in he linea ( iode) egions is gi en
F om he abo e exp ession i is clea ha he esis ance o NMOS
swi ch is non-
linea ha is
pp oaches in ini y when Vin app oaches Vdd
-
V h,which is he uppe limi o he NMOS
Ga e Swi ch
To ci cum en he abo e p oblem wi h a a ying swi ch esis ance he bene i o NMOS o
low inpu ol ages and he PMOS o
high inpu ol ages can be U ilized.i is done simply by
connec ing hem in pa allel and he eby o ming a ansmission ga e
.
Ma ch 2011
46
loop a chi ec u es end o consume lowe powe and wo k a high sampling equencies han
speed ADCs [3][4].
en op imized wi h espec o linea i y, noise, and
This pape in es iga es e ec o a ious design schemes and
hold ci cui o achie e accep able linea ly, high slew a e, low
accep able linea i y o sou ce
- ollowe s
) o s o e he
alue o sampled signal du ing he hold mode. Du ing he acking phase, he combina ion o
cons an o which se s he
k appea s no o be a
se ious limi a ion in his wo k because as will be seen he chosen ope a ing equency is a less
cons an o he swi ch ne wo k and is basically limi ed by o he pa s o he
e o he sampling ne wo k is dependen on he sampling capaci ance
alue and he wid h o he swi ching ansis o . In addi ion o he noise added by he swi ch, he
dependen beha iou o he swi ch can deg ade he o e all
The maximum ou pu ol age ha an NMOS ansis o can deli e is app oxima ely equal o
channel MOS de ice ope a ing in he linea ( iode) egions is gi en
linea ha is
V h,which is he uppe limi o he NMOS
To ci cum en he abo e p oblem wi h a a ying swi ch esis ance he bene i o NMOS o
high inpu ol ages can be U ilized.i is done simply by
In e na ional J
ou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1,
Figu e 3.
T ansmission ga e sampling swi ch
NMOS ansis o shows
he non
ansis o wo ks poo ly o high ol ages. A PMOS ansis o on he o he hand , is known o
wo k poo ly o low ol ages and a he o high ol ages.
The ansmission-ga e-swi ch (
he solu ion o he p oblem aced by single NMOS and PMOS swi ches. As seen in igu e, he
esis ance o he ansmission
swi ches can be wise
choice o ge accep able li
Figu e 5.
3.
CONVENTIONAL T
/
H USING SOURCE FOLLO
Sou ce ollowe was used in his wo k o d i e he load c
de ices in he sou ce-
ollowe con ibu e o he noise in bo h he ack and hold modes o
ou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1,
Ma ch 2011
T ansmission ga e sampling swi ch
Figu e 4. On-
esis ance o he
ansmission ga e
he non
-
linea cha ac e isi cs o high ol ages. This is why NMOS
ansis o wo ks poo ly o high ol ages. A PMOS ansis o on he o he hand , is known o
wo k poo ly o low ol ages and a he o high ol ages.
NMOS-and-
PMOS ansis o connec ed in pa allel
he solu ion o he p oblem aced by single NMOS and PMOS swi ches. As seen in igu e, he
esis ance o he ansmission
-ga e-
swi ch is much linea ha is why ansmission
choice o ge accep able li
nea y and la ge ou pu gain [18].
Resis ance magni ude o sampling swi ches
H USING SOURCE FOLLO
WER
Sou ce ollowe was used in his wo k o d i e he load c
apaci ance o he T/H s age. The ac i e
ollowe con ibu e o he noise in bo h he ack and hold modes o
Ma ch 2011
47
esis ance o he
linea cha ac e isi cs o high ol ages. This is why NMOS
ansis o wo ks poo ly o high ol ages. A PMOS ansis o on he o he hand , is known o
PMOS ansis o connec ed in pa allel
) migh be
he solu ion o he p oblem aced by single NMOS and PMOS swi ches. As seen in igu e, he
swi ch is much linea ha is why ansmission
-ga e-
apaci ance o he T/H s age. The ac i e
ollowe con ibu e o he noise in bo h he ack and hold modes o
In e na ional Jou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1, Ma ch 2011
48
ope a ion. The noise o hese de ices mainly due consis s o channel he mal noise and ga e
licke noise.
3.1. Analysis o T/H Ci cui Using NMOS Sampling Swi ch
A con en ional sou ce ollowe T/H ci cui basically consis s o inpu , ou pu bu e s, a swi ch
and a sampling capaci o . An ou pu bu e is usually used o cha ge and discha ge he inpu
capaci ances o ollowing compa a o s.
A T/H ci cui has wo ope a ion phases named “ ack phase” and “hold phase”. Du ing a ack
phase he swi ch is sho ed and V
ou
becomes equal o V
in
. On he o he hand, du ing a hold
phase he swi ch is opened and he T/H ci cui keeps i s ou pu ol age equal o he alue a end
o ack phase. A equi ed hold ime o a T/H ci cui is usually decided by a se ling ime o he
ollowing compa a o s since he compa a o s mus se le hei ou pu ol age du ing a hold
ime [9].
Figu e 6. Single ended con en ional T/H
Table 1. Design speci ica ion o T/H
Powe supply ol age 1.8
Maximum inpu signal
equency
500 MHz
Sampling equency 1GHz
Maximum ou pu ol age
swing (Ain)
1 Vp-p
Resolu ion 6 bi
Load capaci ance (C
L
) 10p
Inpu o se 0.8
CMOS echnology 0.18µm
An inpu ol age ep esen ed by
sin
(2)
Whe e A
in
is equal o he maximum inpu ol age gi en by he speci ica ions and ω
in
is se o 2π
(
s
/2 ).
s
means i s sampling equency.
3.2. Analy ical Modeling o Con en ional T/H Ci cui
Figu e 7. Small signal model o con en ional T/H
In e na ional Jou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1, Ma ch 2011
49
A T ans e unc ions om V
in
o V
1
, and om V
1
o V
ou
is ep esen ed by
1
1
1
1
1
3
!
1
1
"
1
1
1
4
Respec i ely, whe e
and
is ime cons an which is de ined by
$
%
&'
( ,
*
+
%
&
,
5
,
"
,
1
.
/
.
/
.
0
,
23
.β
4
√
α
4
.
β
4
τ
C
6
Whe e/
, 0
is de ined as ollows
/
89
:;
<9
=>
?%
&'
, 0
"
;@'
,
A
;
9
BB
C
>
89
:;
<9
D>
?
E
;@'
7
On he assump ion ha an accep able gain e o a he inpu bu e o he T/H ci cui is e
1
an
op imum
mus sa is y
|
T
j
ω
KLM
|
1
.
1
ω
KLM
τ
2
1
P
e
8
and
VWX
L
<
[
1
1
s
τ
.
V
s
^
9
Whe e V
1
(s) is he ou pu o he inpu bu e o con en ional T/H ci cui .
Table 2. Hspice smula ion o
con en ional T/H ci cui
Vou 1.46
A e age powe
consump ion
76.94 mw
peak powe o e
a cycle
89.08 mw
Slew a e 89.64 m /ns
T ack ime 0.92 ns
Hold ime 0.76 ns
Figu e 8. Ou pu wa e o m o con en ional T/H
In e na ional Jou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1, Ma ch 2011
50
3.2.1 Noise Analysis o Con en ional T/H Ci cui
Table 2. Noise esul s o con en ional
T/H
To al ou pu noise
ol age
6.945e-01 Sq
V/Hz=833.37p
V/R (Hz)
T ans e unc ion
alue ( Vou /Vin )
1.64882n
Equi alen inpu
noise a Vin
505.43604m
To al equi alen
inpu noise ol age
1.14265K V
Figu e 9
.
Ou pu
n
oise o
c
on en ional T/H
3.3. Analysis o T/H Ci cui using T ansmission-Ga e Sampling Swi ch
He e NMOS sampling swi ch is eplaced wi h T ansmission-ga e sampling swi ch. As discussed
ea lie ha On- esis ance o T ansmission-ga e shows he linea cha ac e is ics hence linea i y
in ou pu wa e o m is expec ed his is con i med by he HSPICE simula ion esul . I imp o es
he linea i y bu a he cos o a ea o e head. We equi e one mo e clock o use ansmission-
ga e sampling swi ch
Figu e 10. Con en ional T/H using T ansmission-ga e
sampling swi ch
Table 3. Hspice simula ion esul s o
con en ional T ack-and-Hold using
T ansmission-Ga e
V
ou
1.57
A e age powe
consump ion
78.33 mw
Peak powe o e
a cycle
90.91 mw
Slew a e 110.48 m /ns
T ack ime 0.92 ns
Hold ime 0.81 ns
Figu e 11. Ou pu wa e o m o T/H using T ansmission-ga e sampling swi ch
In e na ional Jou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1, Ma ch 2011
51
F om he ou pu wa e o m i is clea ha V
ou
is linea in beha iou .
3.3.1 Noise Analysis o Con en ional T/H Ci cui using T ansmission-Ga e
Table 4. Noise esul s o con en ional
T/H using T ansmission-Ga e
To al ou pu noise
ol age
4.473e-019
Sq V/Hz =
668.83807p
V/R (Hz)
T ans e unc ion
alue (Vou /Vin)
1.06742n
Equi alen inpu
noise a Vin
626.59340m
To al equi alen
inpu noise ol age
1.43876K V
Figu e 12. Ou pu noise o con en ional T/H using
T ansmission-Ga e
3.4. Analysis o Pseudo-di e en ial T/H ci cui
The T/H ci cui is implemen ed in a pseudo-di e en ial ashion o supp ess e en–o de
nonlinea i ies as well as o se and common-mode noise. The biasing b anch o he sou ce-
ollowe is, howe e , sha ed be ween he wo hal ci cui s o cancel he noise con ibu ion o
biasing de ices.
Figu e 13. Pseudo-de e en ial T/H
Figu e 14. Ou pu wa e o m o pseudo-
de e en ial T/H
Table 5. Hspice Simula ion Resul o Pseudo-Di e en ial T/H
Vou 1.50
A e age powe consump ion 93.64 mw
Peak powe o e a cycle 103.5 mw
Slew a e 135m /ns
T ack ime 0.88 ns
Hold ime 0.77 ns
In e na ional Jou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1, Ma ch 2011
52
3.4.1 Noise Analysis o Pseudo-di e en ial T/H ci cui
Table 6. Noise esul s o con en ional
T/H using T ansmission-Ga e
To al ou pu noise
ol age
5.674e-019
Sq V/Hz
=753.29254p
V/R (Hz)
T ans e unc ion
alue (Vou /Vin)
1.04183n
Equi alen inpu
noise a Vin
723.05050m
To al equi alen
inpu noise ol age
1.63118K V
Figu e 15. Ou pu noise o pseudo-di e en ial T/H
3.5. Analysis o ully-di e en ial T/H ci cui
Figu e 16. shows ha inpu and ou pu bu e s o con en ional T ack-and-Hold ci cui a e
modi ied in di e en ial manne so ha common mode noise could be supp essed. This
a chi ec u e supp ess he noise up o 60-70% as compa ed o con en ional one bu a he cos
o powe consump ion and a ea o e head.
Figu e 16. Fully-de e en ial T/H
Figu e 17. Ou pu wa e o m o ully-
de e en ial T/H
Table 7. Hspice simula ion esul s o ully-di e en ial T/H
Vou 1.56
A e age powe consump ion 162 mw
Peak powe o e a cycle 182 mw
Slew a e 181 m /ns
T ack ime 0.92 ns
Hold ime 0.81 ns
In e na ional Jou nal o VLSI design & Communica ion Sys ems (VLSICS) Vol.2, No.1, Ma ch 2011
53
3.5.1 Noise Analysis o ully-di e en ial T/H ci cui
Table 8. Noise esul s o ully di e en ial
T/H ci cui
To al ou pu noise
ol age
2.981e
-
019 Sq
V/Hz
= 546.01522 p
V/R (Hz)
T ans e unc ion
alue (Vou /Vin)
0
Equi alen inpu
noise a Vin
0
To al equi alen
inpu noise ol age
0 V
Figu e 18. O/P Noise o ully-di e en ial T/H
3.5. Analysis o Two-S age T/H using Con en ional T/H Ci cui
In wo-s age T/H ci cui , wo con en ional T/H ci cui s a e connec ed in cascade. The ou pu o
he i s T/H se es as he inpu o he nex T/H. I he inpu ol age o a T/H ci cui is kep
cons an du ing i s ack phase, only one o cha ging o discha ging is occu ed in a ack phase.
In his case he ou pu ol age o he T/H ci cui se les mono onously in o he cons an ol age
om he beginning o he ack phase and i s hold ime mus be as long as possible. This
educ ion o he acking ime esul s in a low powe consump ion. In o de o apply such a
cons an ol age o he T/H ci cui an addi ional small T/H ci cui is inse ed in on o he
o iginal T/H ci cui as shown in Figu e 19. In e ing and non-in e ing clocks a e applied o he
wo swi ches, Msw0 and Msw1, espec i ely so ha he wo T/H ci cui s ac ecip ocally.
Figu e 19. Two s age T/H ci cui
Figu e 20. Ou pu wa e o m o wo s age T/H
ci cui
When he second T/H ci cui is in a ack phase he i s T/H ci cui is always in a hold phase
whose ou pu ol age is cons an . The i s T/H ci cui also cha ges and discha ges i s load
capaci ance du ing a ack phase, howe e , i can ope a e e y as because i s load capaci ance
is much smalle han ha o he con en ional T/H ci cui . The i s T/H ci cui consumes e y
low powe when he i s T/H ci cui and he con en ional one ha e he same ope a ion speed.
The ou pu ol age o he i s s age is applied o he second T/H ci cui . When he second T/H
ci cui is in he ack phase, i s inpu ol age is always cons an because he i s T/H ci cui is
al eady in he hold phase. The e o e, i s ou pu ol age app oaches o he inal alue di ec ly and
i ’s se ling ime dec eases d as ically [8].
