The Vertex Detector Upgrade of the Belle II Experiment

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The Ve ex De ec o Upg ade o he Belle II Expe imen
To u Tsuboyama, Maximilian Babeluk, Ma lon Ba be o, Pie e Ba illon,
Je ome Baudo , Thomas Be gaue , Flo ian U Be nlochne , G ego y
Be olone, S e ano Be a ini, Filippo Bosi, e al.
To ci e his e sion:
To u Tsuboyama, Maximilian Babeluk, Ma lon Ba be o, Pie e Ba illon, Je ome Baudo , e al.. The
Ve ex De ec o Upg ade o he Belle II Expe imen . 31s In e na ional Wo kshop on Ve ex De ec o s,
Oc 2022, Chiba, Japan. pp.011013, �10.7566/JPSCP.42.011013�. �hal-04631585�
The Ve ex De ec o Upg ade o he Belle II Expe imen
To u Tsuboyama(*)1 Maximilian Babeluk2 Ma lon Ba be o3 Pie e Ba illon3 Je ome
Baudo 4 Thomas Be gaue 2 Flo ian U. Be nlochne 5 G ego y Be olone4 S e ano
Be a ini6 Filippo Bosi7 Roua Boudagga3 Pa ick B eugnon3 Giulia Casa osa6 Giulio
Dujany4 Ch is ian Finck4 F ancesco Fo i6 Denis Fouge on3 Abdelkade Himmi4 Ch is ine
Hu4 Ch is ian I mle 2 Akimasa Ishikawa1 Ca los Ma inas(**)8 Mau izio Massa7
Ludo ico Massaccesi6 Massimo Minu i7 Su yana ayan Mondal6 F ede ic Mo el4 Pa ick
Pangaud3 Hung Pham4 Giuliana Rizzo6 Benjamin Schwenke 9 Ma ie Schwicka di9
Rachid Se i4 Pe os S a oulakis4 Isabelle Valin4 Danwei Xu3 o he Belle II Ve ex
De ec o upg ade g oup.
1KEK, High Ene gy Accele a o Resea ch O ganiza ion, Tsukuba, Japan
2Ins i u e o High Ene gy Physics, Aus ian Academy o Sciences, Vienna, Aus ia
3Aix Ma seille Uni , CNRS/IN2P3, CPPM, Ma seille, F ance
4Uni e si `e de S asbou g, CNRS, IPHC UMR 7178, S asbou g, F ance
5Uni e si y o Bonn, Bonn, Ge many
6Dipa imen o di Fisica, Uni e si `a di Pisa, I-56127 Pisa, I aly, INFN Sezione di Pisa, I aly
7INFN Sezione di Pisa, I aly
8IFIC - Ins i u o de F´ısica Co puscula (CSIC/Uni e si y o Valencia), E-46980 Pa e na, Spain
9II. Physikalisches Ins i u , Geo g-Augus -Uni e si ¨a G¨o ingen, Ge many
(*) Suppo ed by JSPS KAKENHI 20H01922, 19H00692 and 21K18633. (**)Suppo ed by G an
RYC2020-029875-I unded by MCIN/Agencia Es a al de In es igaci´on (Spain) and has ecei ed
unding om Eu opean Union’s Ho izon 2020 Resea ch and Inno a ion p og amme unde g an
ag eemen no. 101004761 (AIDAinno a) and Nex Gene a ionEU/PRTR.
E-mail: [email p o ec ed]
(Recei ed Feb ua y 28, 2023)
The Supe KEKB accele a o and Belle II expe imen ha e s a ed ull ope a ion in 2019, es ablishing
in 2022 a wo ld eco d wi h an ins an aneous luminosi y o 4.7 × 1034/cm2/s. To each he nominal
luminosi y pa s o Supe KEKB will be modified wi h a ime ame cu en ly p edic ed o be a ound
Long Shu down 2 in 2026. Thus, he Belle II collabo a ion is conside ing he possibili y o ins all
an upg aded e ex de ec o (VXD) sys em on he same ime scale. Such an upg ade should p o ide
a sufficien sa e y ac o wi h espec o he backg ound a e expec ed a he nominal luminosi y
(6.5 × 1035/cm2/s) and possibly enhance pe o mances o acking and e exing.
Se e al echnologies a e unde conside a ion o he upg ade. One app oach is o imp o e he pe o -
mance o he echnologies p esen in Belle II: as e DEPFET senso s [1] o he inne mos laye s,
hinne and mo e g anula double-sided silicon s ip de ec o s (DSSDs) o he emaining laye s. New
monoli hic echnologies o pixel senso s a e also unde discussion, namely SOI (Silicon-on-senso )
and CMOS. They offe a combina ion o g anula i y, speed, low ma e ial budge and adia ion ole -
ance ma ching well Belle II equi emen s and could be exploi ed o design a ully pixela ed VXD,
also benefi ing om significan de elopmen s made in ecen yea s o o he expe imen s. Following
his las concep , bo h simplified and comple e simula ions ha e been conduc ed o e alua e acking
and e exing pe o mance wi h a ious geome ies (e.g. numbe o laye s) and echnical specifica-
ions (e.g. g anula i y, speed).
This a icle e iews he con ex o he p oposed VXD upg ade in Belle II, p o iding some de ails o
he exis ing echnological p oposals and discussing pe o mance expec a ions om simula ions.
KEYWORDS: Supe KEKB, e ex de ec o , luminosi y, adia ion ole ance, physics
pe o mance
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JPS Con . P oc. , 011013 (2024)
©2024 The Au ho (s)
h ps://doi.o g/10.7566/JPSCP.42.011013
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mus main ain a ibu ion o he au ho (s) and he i le o he a icle, jou nal ci a ion, and DOI.
P oc. 31s In . Wo kshop on Ve ex De ec o s (VERTEX2022)
011013-1
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1. In oduc ion
Supe KEKB is an asymme ic ene gy e+e−collide a he Υ(4S) ene gy [2]. Belle II aims o
s udy, p ima ily, he Bmeson decays in high s a is ics [3]. As he Bmesons mo e along he beam
di ec ion (z), he ime dependence o he Bdecay can be measu ed by using he e ex de ec o
(VXD). The e o e, he posi ion esolu ion in zis equally impo an as in he ans e se di ec ion
( −ϕ). The cu en Belle-II VXD, as shown in Fig. 1, consis s o wo-laye DEPFET pixel de ec o s
(PXD) [4] and ou -laye double sided s ip senso s (SVD) [5]. The Belle II VXD co e s he angula
accep ance o 17◦< θ < 150◦.
SVD (R=39, 80, 105, 140)
R155
PXD(R=14, 22)
Be yllium beam pipe (R=10)
935
Fig. 1. The schema ic c oss sec ion o he Belle II in e ac ion egion. (uni =mm). The elec on and posi on
beams collide a he cen e o Be yllium beam pipe. The e ex de ec o consis s o wo DEPFET (PXD) laye s
and ou Silicon s ip de ec o laye s (SVD). suppo o SVD ladde s.
Table I. The laye s uc u e o he Belle II e ex de ec o , he ma e ial hickness o pixel and s ip laye s
includes he ma e ial o suppo
Laye Componen Ma e ial Radius Thickness Ma e ial hickness
(mm) (mm) o he laye (% X0)
Gold pla ing Au 10 0.01 0.3
Beam pipe Be 10 1.0 0.3
1 Pixel Si 14 0.075 0.2
2 Pixel Si 22 0.075 0.2
3 S ip Si 39 0.32 0.7
4 S ip Si 80 0.32 0.7
5 S ip Si 105 0.32 0.7
6 S ip Si 140 0.32 0.7
The PXD and SVD ha e been wo king success ully since 2019. The pe o mance o he p esen
VXD is desc ibed in he p oceeding pape s o his con e ence [6,7].
In 2022, he peak luminosi y o he Supe KEKB eached o 4.7×1034/cm2/s a beam cu en o
1 A (e+) and 1 A (e−) and Belle II has accumula ed da a co esponding o an in eg a ed luminosi y o
428 b−1.
To achie e he luminosi y goal o 6.5×1035/cm2/s, he Supe KEKB will be upg aded in wo
s eps. In July 2022, Supe KEKB en e ed he Long Shu down 1 (LS1) pe iod. The main pu pose
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Table II. Backg ound le el a he inne mos laye o VXD assumed o he VXD upg ade.
Backg ound hi a e 113 M hi s/cm2/s
TID Le el 100 kGy/yea
NIEL Fluence 5 ×1013 neq/cm2/yea
o LS1 is o eplace he DEPFET pixel de ec o [1] wi h he comple e wo laye sys em. The Long
Shu down 2 (LS2) is scheduled in 2026. In LS2, he Supe KEKB accele a o will be ein o ced o
each o he luminosi y goal and collec da a co esponding o 50 ab−1, as shown in Fig. 2.
In eg a ed luminosi y (ab-1)
Peak luminosi y (1035/cm2/s)
(Yea )
2019 2024 2029 2034
10
8
6
4
2
0
60
50
40
30
20
10
0
LS1 LS2
Fig. 2. P ospec o he Luminosi y imp o emen s o Supe KEKB. The ed line shows he peak luminosi y
in uni o 1035/cm2/s. The ze o luminosi y pe iods o he sho shu down a e no shown. The blue line shows
he in eg a ed luminosi y in uni o ab−1. LS1 and LS2 indica e he long shu down pe iods scheduled om
2022-2023 and 2027-2029.
The Belle II VXD will be upg aded in LS2 in o de o imp o e he backg ound immuni y and
physics pe o mance. To s a he design o he VXD upg ade, he beam backg ound om he Supe
KEKB was es ima ed. Table II shows he backg ound le el a he inne mos laye o he VXD a
he luminosi y o 6.5×1035/cm2/s wi h a ×5 sa e y ac o [8]. The upg aded senso s should be
sa ely ope a ed a he ha sh adia ion condi ion. The op imiza ion o he ma e ial budge and posi ion
esolu ion is also needed o o imp o e he physics pe o mance o Belle II.
In his a icle, he ollowing upg ade ac i i ies [8] will be desc ibed: (a) DMAPS ( ully-Deple ed
Monoli hic Ac i e Pixel Senso ), (b) SOIPIX (Silicon on Insula o Pixel senso ), and, and (c) TFP
(Thin Fine-Pi ch silicon s ip senso ).
2. DMAPS - Deple ed CMOS Ac i e Senso
The DMAPS (Deple ed MAPS) echnology is an imp o emen o he CMOS Ac i e Senso . The
CMOS ci cui is de eloped in he deep p-well egion abo e he p- ype epi axial laye as shown in
Fig. 3. A ull CMOS ci cui can be in eg a ed in he deep p-well egion. The sensi i e egion is ully
deple ed wi h he bias ol age. The small cha ge collec ion node makes he cha ge collec ion as and
efficien . The DMAPS echnology is adia ion ha d enough o he upg ade plan.
2.1 TJ-MONOPIX2 pixel senso
TJ-MONOPIX2 was o iginally de eloped o ATLAS and has been iden ified as a good candida e
o he Belle II VTX upg ade. The specifica ions o MONOPIX2 a e shown in Table III. The chip
includes as -shaping on end and ime-o e - h eshold ci cui o he clus e cha ge measu emen .
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Fig. 3. DMAPS s uc u e. The wa e is P− ype high esis i i y silicon. The CMOS ci cui is in eg a ed in
he deep p-well. The cha ge is collec ed by he collec ion N-well. The P−o epi axial egion can be deple ed
by he de ec o bias. The low dose N-implan egion and Ngap o ms he elec ic field o as and efficien
cha ge collec ion.
The MONOPIX2 chips we e ins alled o a pixel elescope and he de ec ion efficiency and posi ion
esolu ion we e measu ed a he DESY 5 GeV e−beam. Fig. 4(a) shows ha he de ec ion efficiency
was >99 % independen o he wa e ype. The esidual dis ibu ion o he clus e posi ion (Fig. 4(b))
was consis en wi h (pixel size)/√(12). The de ails o he MONOPIX e alua ion a e desc ibed in [9].
(a)
e iciency (%)
99
98
97
96
95
94
93
92
(b)
UHi - UFi [μm]
Numbe o clus e s
Fig. 4. Tes beam esul o TJ MONOPIX2 senso . (a) De ec ion efficiency s he bias ol age o diffe en
wa e ypes. W12R14, W5R9 and W5R18 co esponds o Cz-bulk, epi 30 µm and epi 30 µm, espec i ely. (b)
Spa ial esolu ion o pe pendicula inciden acks. Ho izon al axis shows he esidual o posi ion measu ed
by he DUT (de ice unde es ) and he elescope.
Table III. The main cha ac e is ics o TJ-MONOPIX2
Technoloy Towe Jazz 0.18 µm CMOS
Chip size 20 mm×20 mm
Ac i e a ea 17 mm ×17 mm
Pixel pi ch 33 µm×33 µm
Subs a e Epi (∼1 kΩ-cm) /Cz (>1 kΩ-cm)
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2.2 OBELIX pixel senso
Following he TJ-MONOPIX2, he fi s chip implemen ing he specific needs o Belle II is de-
signed, OBELIX (Op imized BELle II pIXel) [10] pixel senso as shown in Table IV is in p og ess.
The chip will include he necessa y unc ions o he Belle II ope a ion en i onmen : he as -shaping
on end, cha ge digi iza ion wi h ToT ci cui , igge -hi ma ching and ze o supp ession logic. The
OR o he pixel signal will be p oduced o he as hi in o ma ion o he Belle II igge . The fi s
p o o ype o he OBELIX senso will be submi ed in 2023.
Based on he OBELIX senso , he mechanical design o he e ex de ec o (VTX) sys em is
in p og ess. In VTX, no only he pixel laye s bu also he s ip laye s o he cu en Belle II VXD
will be eplaced wi h he pixel laye s. VTX will consis o wo inne laye s (iVTX, R=14 mm and
22 mm) and h ee ou e laye s (oVTX, R=39 mm, 90 mm and 140 mm). To simpli y he sys em, he
whole VTX will be buil wi h a single senso design. Fo he iVTX ou consecu i e chips on a wa e
a e cu ou as one sel -suppo ing module. The in e connec ions be ween he chips and he eadou
elec onics will be ealized as a high densi y in e connec laye . Ai cooling will be possible hanks
o he small powe consump ion (200 mW/cm2). In he oVTX modules, he OBELIX senso s will be
assembled wi h uss-shape ca bon fib e suppo . Wa e cooling wi h polyimide ubes has been es ed
success ully. The o al ma e ial hickness will be kep below 2 % adia ion leng h (X0) o imp o e he
physics pe o mance, whe eas he ma e ial hickness o he cu en Belle II VXD is 0.4 % X0(PXD)
and 2.8 % X0(SVD) [11].
Table IV. The main cha ac e is ics o OBELIX pixel senso
Technoloy Towe Jazz 0.18 µm CMOS
Chip size 32.2 mm×18.3 mm
Ac i e a ea 31.6 mm ×18.1 mm
Pixel size 33 µm×33 µm
2.3 Expec ed physics pe o mance
The physics pe o mance o Belle II a e he VTX ins alla ion is es ima ed by using he Mon e-
Ca lo simula ion. The effec o he inc eased beam backg ound o he nominal luminosi y is aken
in o accoun . Figs. 5 (a) and (b) shows he compa ison o he econs uc ion efficiency o so pions
(πs) om D∗meson decay. Thanks o he small ma e ial hickness and he high spa ial esolu ion, he
econs uc ion efficiency o he πswill imp o e by 50-80 %. The efficiency imp o emen will esul
in highe sensi i i y o he new physics phenomena.
3. SOI - Silicon on Insula o
The SOI is a s anda d echnology o p oducing high-pe o mance CMOS ci cui . The SOI wa e
consis s o he subs a e silicon and he silicon laye o he CMOS ci cui sepa a ed by a hin SiO2
laye (Bu ied oxide o BOX), Figu e 6. In he SOI senso , a senso g ade wa e is used. Wi h impu i y
injec ion, a complex senso s uc u e can be designed in he subs a e. The cha ge gene a ed by he
adia ion is p ocessed in he ci cui laye .
Fig. 6 shows he s uc u e o PDD (Pinned Deple ed Diode). The impu i y s uc u e is designed
so ha he cha ge ca ie induced by adia ion d i s o he collec o node smoo hly, he e o e, he
efficien and as cha ge collec ion is ealized. The BPW (Bu ied P-well) egion is se o a fixed
ol age, VBPW which p e en s he subs a e po en ial affec ing he ope a ion o he CMOS ci cui
abo e he BOX laye . Thanks o he small collec ion node, he senso capaci ance is as small as 3 F.
The DuTiP, Dual Time Pixel senso , concep is designed o he Belle II upg ade. using Lapis 0.2 µm
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(a) (b)
Fig. 5. Recons uc ion efficiency o so pions in (a) B→D∗µν,D∗→πsKπand (b) B→D∗µν,D∗→
πsKπππ Red poin s show he Belle II VXD and black poin s, he VTX de ec o concep . The econs uc ion
efficiency imp o es by 50-80 %. Lowe limi o πs econs uc ion is ex ended om 75 MeV/c o 50 MeV/c.
CMOS ci cui
p+
Gnd
p--
Cha ge
Co ec o
BNW
BPW
p+
BOX
Pa icle ack
n+
Cha ge ca ie
e- e- e- e- e-
Vbias
VBPW
n-ch p-ch
Fig. 6. A ypical SOI pixel senso wi h PDD (Pinned Deple ed Diode) subs a e s uc u e. The wa e is high-
esis i i y p− ype. The p- ype and n- ype impu i ies a e implan ed o o m he elec ic field as and efficien .
The CMOS ci cui is in eg a ed on he bu ied oxide (BOX) laye .
senso
ALPIDE pixel mask
seqence
delay coun e 2
delay coun e 1
Belle II global igge
hi memo y 1
hi memo y 2
Hi eadou bus
Fig. 7. The pixel ci cui o he DuTiP. The hi cha ge in he wa e is picked up by he senso node and
p ocessed by he ALPIDE amplifie . The delay coun e -1 and -2 a e used o delay he hi signal o he igge
decision ime o Belle II global igge . I he delayed hi signal coincides wi h he Belle II igge , he hi will
be ead ou h ough he hi - eadou bus and sen o he Belle II da a acquisi ion sys em.
SOI pixel senso echnology. The pixel ci cui is shown in Fig. 7 [12]. The ALPIDE- ype on end
[13] is adop ed o low powe consump ion. The hi signal is delayed wi h he delay coun e ( ime )
and he coincidence wi h he Belle II global igge is aken. The coincidence educes he backg ound
hi occupancy efficien ly. Two ime a e in eg a ed in each pixel o secu e hi s a i ing wi hin he
igge decision ime. The hi in o ma ion is sen fi s o he column FIFO and hen o he global FIFO
o he eadou . The igge ID is added o each hi inside he chip. Simula ion s udy shows he hi
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Table V. The specifica ions o he DuTiP pixel senso
Wa e High esis i i y
p- ype FZ silicon(6-8 kΩcm)
Bu ied oxide (BOX) 140 nm SiO2
Silicon 20 nm low esis i i y
Senso s uc u e Pinned Deple ed Diode
Chip size 17.2 mm ×29.6 mm
Pixel size 45 µm×45 µm
Ac i e a ea 14.4 mm ×28.8 mm
occupancy can be educed <0.1 % unde he 113 MHz/cm2backg ound hi condi ion. Efficiency da a
ans e is expec ed wi h he wo s age FIFO [12]. Two p o o ypes ha e been p oduced as shown in
Table VI. DuTiP1 (2021) was designed o s udy he DuTiP pixel ci cui , especially, he pe o mance
o he wo- ime concep . DuTiP2 (2022) is a ull size senso in he column di ec ion and in ended o
s udy he eadou sequence o he DuTiP. Bo h chips a e unde e alua ion.
Table VI. The specifica ions o he DuTiP pixel senso
DuTiP1 DuTiP2
Chip size 6 mm ×6 mm 6 mm ×18.4 mm
Pixel size 45 µm×45 µm 45 µm×45 µm
Pixel a ay 64 ×64 64 ×320
4. TFP - Thin Fine Pi ch double sided de ec o
The silicon s ip senso is a sui able o co e ing a la ge a ea in he ou e laye s. Double-sided
silicon s ip de ec o s (DSSDs) wi h a hickness o ≃300 µm we e used in ou e ou laye s o he
Belle II VXD (Table I). In he o wa d egion 17◦< θ < 45◦, he c ossing angle o he cha ge acks
o he senso laye s becomes la ge. The clus e shapes a e elonga ed and he posi ion esolu ion in
z apidly deg ades. The senso s in he o wa d egion a e he e o e slan ed (Fig. 1) o eco e he
posi ion esolu ion. The TFP ( hin fine-pi ch) DSSD g oup p oposed o eplace he he exis ing SVD
wi h new double-sided s ip senso s made om 150-µm hick silicon wa e [14]. To educe he hi
occupancy and o imp o e he spa ial esolu ion especially in z, he eadou pi ch is educed om 240
µm o 75 µm (z-measu emen ) and 75 µm o 50 µm ( −ϕ-measu emen ).
A dedica ed eadou ASIC, SNAP128A, has been p oduced wi h he Sil e a 180 nm CMOS ech-
nology [14]. SNAP128A was designed o be ope a ed in he expec ed high backg ound en i onmen
o he a ge luminosi y. The on end is a cha ge sensi i e amplifie wi h a shaping ime o 100 ns op-
imized o he 150-µm hick DSSD senso . The signal pola i y in e e is implemen ed o he p-side
and n-side eadou . A e he compa a o , he hi signal is delayed by a 2 kbi digi al pipeline. When a
igge is ecei ed, he da a one o mo e cells o he digi al pipeline a e ead ou . The hi in o ma ion
is sen o he LVDS d i e . FO he igge pu poses, he SNAP128A will p o ide a hi -OR signal o
he Belle II igge sys em. The TFP hi signal is use ul o gene a ing he as ack in o ma ion.
A p o o ype TFP senso wi h a size o 59 mm ×52.6 mm was ab ica ed by Mic on (UK). The
es esul will be epo ed in his p oceedings [14]. The TFP senso and he SNAP128A chip ha e
been i adia ed wi h an elec on beam o measu e he TID and NIEL adia ion ha dness. The analysis
is in p og ess.
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6120 um
5945 um
52.6 mm
59.0 mm
(A) (B)
Fig. 8. (A) A p o o ype TFP DSSD: The wa e hickness is 150 ￥um. S ip pi ch on p-side and n-side is
50-µm and 75-µm. (B) The SNAP128A chip on he es PCB.
The concep o he module s uc u e is shown in Fig. 9. An aluminum flex laye (Al 15 µm)
will be in oduced o he powe ails. Al hough each senso is ead ou by 14 SNAP128A chips, he
gene a ed hea can be emo ed by he wa e cooling a 5 °C, whe eas he coolan is ci cula ed in hin
s ainless s eel ubes.
(A) (B)
(A)
(B)
(C)
(H)
(G)
(F)
(E)
(D)
Fig. 9. The b eakdown o he TFP module s uc u e: (A) he s ainless cooling ube, (B) he mal conduc i e
film, (C) aluminum flex o he powe ing, (D) ASIC flex o signal ans e , (E) g aphi e hea sp eade , (F)
he mal insula o , (G) TFP DSSD senso , (H) Fanou o he bo om-side signal
5. Summa y
The upg ade ac i i y o he Belle II e ex de ec o (VXD) has been p esen ed. The p og ess o
DMAP, DuTiP and TFP is ema kable. Recen ly, a new discussion o eplacing se e al inne -wi e
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011013-8JPS Con . P oc. , 011013 (2024)42
P oceedingso  he31s In e na ionalWo kshoponVe exDe ec o s(VERTEX2022)
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