POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 19 |NUMBER: 3 |2021 |SEPTEMBER
High F equency Mul ipu pose SiC MOSFET D i e
Jan STROSSA , Vladisla DAMEC , Ma in SOBEK , Daniel KOURIL ,
Jakub BACA
Depa men o Elec onics, Facul y o Elec ical Enginee ing and Compu e Science,
VSB–Technical Uni e si y o Os a a, 17. lis opadu 2172/15, 708 00 Os a a, Czech Republic
[email p o ec ed], ladisla[email p o ec ed], ma in.sob[email p o ec ed], daniel.k[email p o ec ed], [email p o ec ed]
DOI: 10.15598/aeee. 19i3.4159
A icle his o y: Recei ed Ma 11, 2021; Re ised Ap 24, 2021; Accep ed May 12, 2021; Published Sep 30, 2021.
This is an open access a icle unde he BY-CC license.
Abs ac . This a icle desc ibes a new mul ipu pose
Silicone-Ca bide (SiC) Me al Oxide Semiconduc o
Field E ec T ansis o (MOSFET) d i e , which was
designed and manu ac u ed o a high equency ope -
a ing SiC ansis o as a semiconduc o swi ching de-
ice o powe con e e s. The design o he in oduced
d i e enables o adjus he ou pu ol age le els eas-
ily by choosing he in eg a ed linea ol age s abiliz-
e s wi h sui able ou pu pa ame e s used o P in ed
Ci cui Boa d (PCB) moun ing. The ol age insula-
ion o he p oposed d i e be ween he p ima y con-
ol side and he seconda y ou pu side is pe o med by
MGJ6D12H24MC muRa a Ps DC-DC con e e wi h
a decla ed d /d immuni y 80 kV/1000 ms a 1.6 kV
and by IX3180 IXYS High Speed ga e d i e op ocou-
ple s wi h a decla ed 10 kV/1000 ms minimum com-
mon mode ejec ion a 1.5 kV. The ol age insula ion
o hese coupling elemen s is accompanied by sa e y
gaps on he PCB. These insula ion ea u es enable
he p oposed d i e o wo k on high equencies as
a high-side ansis o o H-b idges as same as in o he
powe con e e opologies wi h a high equency and
high ol age s ess o he insula ion bo de . The p o-
posed d i e also p o ides he possibili y o ipping
he signal, when he sho ci cui o he con olled
powe ansis o occu s.
Keywo ds
D i e , high swi ching equency, MOSFET,
mul ipu pose d i e , o e shoo , SiC.
1. In oduc ion
Mode n Silicone-Ca bide (SiC) Me al Oxide Semicon-
duc o Field E ec T ansis o s (MOSFET) can be
used in powe con e e applica ions wo king wi h high
swi ching equencies in a ange om ens o kHz up
o MHz. High swi ching equency wi h a combina ion
o low ansis o swi ching cha ge b ings a possibili y
o as swi ching wi h low powe losses [1] and [2]. This
leads o low swi ching losses due o as ansis o open-
ing and closing and low consumed powe o con ol
he ansis o due o low ga e cha ge [3] and [4].
The equi emen s o a p ecise ga e-sou ce ol age
con ol a ise om accomplish he p ecise swi ching
s a ed abo e [5]. Fas ise and all imes o he ga e-
sou ce ol age a e necessa y o a as swi ching and
ela ed low swi ching loss achie emen [6]. The ela ed
as swi ching enables he con e e o wo k wi h high
con ol dynamics, which is o en equi ed wi hin con-
ol algo i hms [7]. The s eady le els o he ga e-sou ce
ol age, mainly he posi i e le el o he swi ched-on
s a e, a e demanded o be close o he maximum
a ing alues o he used powe ansis o o elimi-
na e he conduc ion and leakage losses [8]. These e-
qui emen s o igina e especially in a necessi y o p e-
cise une up he d i e ou pu esis ance in high ol -
age con e e applica ions. I is caused by he wa e
impedance o he cable line applied be ween he d i e
and con olled ansis o and he ansis o inpu ca-
paci y [9], [10], and [11]. This adjus men is usually
necessa y because o he ga e-sou ce ol age o e shoo
o igina ed a he end o he con ol signal ising edge
and he alling edge, espec i ely. Gene ally, i is de-
manded o de elop a mul ipu pose d i e adjus able
o he speci ic applica ion.
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The high ol age s ess o insula ion bo de be ween
he p ima y and seconda y pa s o he d i e is o ig-
ina ed in some applica ions. Tha can be seen espe-
cially in H-b idges whe e he powe ansis o is d ain
connec ed o he s eady poin o powe ol age wi h
e e ence o he con ol sys em g ound. This ol age
s ess is mo e s enuous wi h a as e swi ching and
highe swi ched ol age due o capaci y cu en low-
ing ia he insula ion bo de and s essing he isola ing
dielec ic.
In gene al, ela i ely high swi ching equencies and
ela ed as ise and all imes o swi ched semicon-
duc o s a e achie able wi h he mode n MOSFETs.
Howe e , i means p ecisely une up he d i e bu e
ou pu esis i i y acco ding o he ou pu cable in-
duc ance, he MOSFET inpu capaci y, and he e-
la ed ga e-sou ce ol age o e shoo . The o e shoo is
highe wi h a highe ising and alling ga e-sou ce ol -
age slopes. High swi ching equencies o he applica-
ions, whe e he ansis o sou ce e minal changes i s
elec ic po en ial wi h changing he swi ch s a e means
high insula ion bo de s ess. In gene al, many d i e s
a e comme cially a ailable, and many d i e designs
we e al eady published, see [12], [13], [14], [15], [16],
[17], [18], [19], and [20].
The goal o he pape is o p esen a mul ipu pose
d i e concep wi h a ew no el po en ials acco ding
o he ollowing speci ic applica ion equi emen s:
•easy se up o he s eady on and o s a e ou pu
ol age le els,
•easy se up o he ou pu esis ance o une i up
acco ding o he ou pu cable impedance,
•high d /d insula ion bo de immuni y up
o 1.7 kV·µs−1,
•signal ip ex ension,
•ex ension o ans e ing he in o ma ion abou
d ain-sou ce ol age p esence,
•possibili y o use he de ice no as a ansis o
d i e , bu as an insula ed ol age de ec o .
All he men ioned ea u es should be easible by
choosing he app op ia e PCB assembly. This makes
he d i e easy o elease o a speci ic applica ion.
Mo eo e , i ep esses he isk o mal unc ion o less
eliable pa s, such as po en iome e s. These pa s a e
no used in he p oposed concep .
2. P oposed D i e Concep
2.1. Gene al Desc ip ion
The p oposed d i e PCB con ains 3 po s a he p i-
ma y side and a g oup o 3 e minals a he sec-
onda y side, each one o one MOSFET pin, see Fig. 1.
The i s p ima y po J1 con ains he powe supply
e minals o 9.6–18 V DC wi h he nega i e pole con-
nec ed o he signal g ound. This po also con ains
an inpu signal o d i ing he con olled ansis o and
i is eady o ace he con olled ansis o sho ci -
cui de ec ion ip signal oo.
J1
DC
DC
In e nal insula ed
powe supply
Inpu
po
Seconda y side ol age
le els gene a o
2x 24 VDC
-15 V DC
-5 V DC
15 V DC
20 V DC
SOURCE
GATE
GATE
Resis o s
GATE Low-
side in eg a ed
d i e
IXDN609SI
MGJ6D12H24MC
Op o
-couple
IX3180
Compa a o . – posi i e
Compa a o . – nega i e
DRAIN
R-cascade
IX3180
IX3180
J4
J5
T ip o -s a e
sup esss
Insula ion gap
Fig. 1: P oposed d i e simpli ied block diag am.
The nex 2 p ima y po s con ain ou pu signals
o he seconda y d ain-sou ce ol age de ec ions, po
J4 eac s on posi i e ol age, po J5 on nega i e.
Each o hese po s has an independen powe supply
on he p ima y side, which is gal anically insula ed.
I can wo k wi h di e en ol age signal s a e le els
acco ding o he connec ed sys em, he ol age adjus -
men is possible wi hin he choice o PCB moun ing
combina ion.
I is also possible o nega e he ou pu signal
a he p ima y side o he posi i e d ain-sou ce ol -
age de ec ion, which can be bene icial mainly i his
signal is used as a ip unc ion. The posi i e d ain-
sou ce ol age de ec o ou pu can be aced in he po
J1 wi h a common signal g ound as same as in po
J4 wi h an independen g ound sys em. In gene al,
he posi i e d ain-sou ce ol age de ec ion can be used
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as a ip unc ion - in his case, he de ec o ou pu
is supp essed when he ou pu ansis o is in an o
s a e. This is pe o med o a oid he alse aul de-
ec ion caused by he p esence o de ec ed ol age on
he swi ched-o semiconduc o . I he supp ession is
no pe o med, he de ec o ou pu jus ollows he de-
ec ed ol age.
2.2. Seconda y Side Powe Supply
Sys em
The p oposed concep con ains a DC-DC
MGJ6D12H24MC muRa a Ps auxilia y sou ce
which p o ides he high du/d immuni y gal anic
insula ion o he powe supply sys em. The uni
o seconda y side powe supply s abiliza ion gene a es
4 ol age le els, which a e assumed o −15 V, −5V,
+15 V and +20 V, as de aul s.
The le els +/−15 V a e aced on o powe supplies
o as ope a ional ampli ie s, which a e used as com-
pa a o s wi hin he uni s o d ain-sou ce ol age de-
ec ions, i hese unc ions a e eleased. The seconda y
side o he d i ing signal op ocouple powe supply is
supplied asymme ically, +15 V/−5V, so he le el
+15 V is also used he e. The e is cu en ly no ex-
pec a ion o demand o change he +/−15 V alues,
bu i could be demanded, e.g. in he case o he used
ope a ional ampli ie s change. In his case, i can be
adjus ed by changing he ela ed e e ence esis o s se-
ies nea he linea ol age egula o s o by changing
hese egula o s, which a e used in he TO-252-3 and
SOT-89 package, espec i ely. I he d ain-sou ce ol -
age de ec ions a e no used, PCB moun ing he −15 V
egula o is no necessa y.
The de aul le els assumed as −5V, +20 V a e used
as ol ages, which a e swi ched a he ga e ou pu .
These should be se acco ding o he applied powe
ansis o on- and o -s a e nominal ol age le els and
he o e shoo o he ga e-sou ce ol age on he applied
ansis o a he end o he ansien swi ching p o-
cesses.
These ol age le els a e gene a ed by he linea ol -
age egula o s wi h no e e ence esis o s and wi h
he signal g ound connec ed di ec ly o he seconda y
g ound. This g ound is also connec ed o he ansis o
sou ce po en ial.
The ol age egula o s a e used in he TO-252 pack-
age and belong o he well-known LM78xx and LM79xx
se ies, espec i ely. I is necessa y o se hese ol age
le els by choosing he app op ia e ol age egula o s.
The nominal o and on-s a e powe MOSFET an-
sis o s ga e-sou ce ol ages a e usually asymme ical
wi h a lowe nega i e le el. Because o ha , he sec-
onda y g ound connec ed o he ou pu ansis o
sou ce is no connec ed o he middle o he DC-DC
insula ion auxilia y sou ce ou pu , e en hough hese
2×24 V DC ou pu s a e connec ed in se ies.
The seconda y side g ound is connec ed o he ou -
pu o ano he −5V DC linea ol age egula o , which
mo es he e e ence g ound om he middle o 2×24 V
abou 5V down. This ensu es ha he e a e a ailable
c. +29 V and −9V as he inpu s o he s eady s a e
ga e-sou ce ol age egula o s.
Seconda y side ol age le els
gene a o
D i ing sys em
Isola ion gap
T ipping sys em/posi i e
d ain-sou ce ol age
de ec ion sys em
Nega i e d ain-sou ce
ol age de ec ion sys em
D ain inpu
up o 1700 V,
R cascade
Fig. 2: P oposed d i e PCB design layou , Eagle expo , blue
colo - bo om ias, ed colo - op ias.
2.3. D i ing Sys em
The d i ing sys em con ains he cascaded op ocou-
ple IX3180, an in eg a ed low-side MOSFET d i e
IXDN609SI and esis i e bu e o pa allel package
1210 esis o s. Fas ec i ying bypass diode o coupling
he pa allel esis o s wi h o he esis o s o he nega-
i e ou pu ol age is also ins alled.
The men ioned elemen s also con ain an ou pu
o supp ess he ip ou pu o do no signalize he ail,
when he powe ansis o is in he o -s a e. I is no
necessa y o moun pa s o all he ou pu esis o s
PCB pads. Howe e , i is impo an o une he o al
alue acco ding o he applied MOSFET and he line
cable be ween he powe ansis o and he d i e ou -
pu [9]. I is also impo an o ind an op imal esis-
o s combina ion acco ding o he powe loss limi a ion
o hese elemen s.
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2.4. T ipping Sys em/D-S Vol age
De ec ion
The ipping sys em/posi i e D-S ol age de ec o is
based on he inpu R-cascade 10 ×1206 package. This
cascade couples he DRAIN inpu e minal, see Fig. 1,
wi h a pai o diodes in an i-se ies, which g ound
he R-cascade ia SOURCE e minal, see Fig. 1.
The an i-se ies diodes limi he ol age be ween
he ou pu o he R-cascade and he sys em g ound.
This ol age is aced o compa a o based on ope a-
ional ampli ie ADA4627. The compa ison e e ence
mus be se by he ela ed pai o esis o s. The p o-
posed PCB layou o he compa a o ou pu con ains
pads o placing he esis o and he capaci o o
he low pass il e ing a he compa a o ou pu .
The inpu R-cascade also o igina es he RC low pass
il e oge he wi h diodes PN-junc ions pa asi ic ca-
paci ies. Choice o an op imal combina ion o inpu
esis i i y and he g ounding diodes hen can be used
o il e ing he inpu signal.
The main ea u e o he p oposed posi i e D-S ol -
age de ec o sys em is he possibili y o uning up
he sensi i i y wi hin a ew le els. Fi s ly, he low pass
il e o igina ed by he inpu R-cascade and he ela ed
diodes can be used o supp ess he noise ecei ed by
he ope a ional ampli ie . Secondly, he low-pass il e ,
o igina ed by he RC elemen o R1and C1, can be
used o supp ess some as ansien peaks a he op-
e a ional ampli ie ou pu , see Fig. 3.
DRAIN
10x1206
SOURCE
– 15 V
+ 15 V
T ipping supp ess
Op ocouple
RREF1
RREF2
RH
DD1
DD2
RD1
RD2
RD10
R1
R2
C1
DT1
Fig. 3: T ipping sys em/posi i e D-S ol age de ec o sys em
simpli ied ci cui diag am.
Se ing up he e e ence esis o s RREF 1and RREF 2
a ec s he e e ence compa ison le el and he inpu
signal- o-noise a io oo.
3. P oposed D i e P o o ype
The d i e p o o ype was ealized o d i ing SiC
C2M0045170D MOSFET manu ac u ed by CREE, Inc.
The ou pu esis i i y was se o app oxima ely 3.33 Ω
o posi i e G-S ol age and 2.22 Ω o nega i e ol age,
using 9×20 Ω esis o s. The s eady posi i e ou pu
ol age was se o +20 V, he s eady nega i e ou pu
ol age was se o −5V.
Fig. 4: Moun ed p oposed d i e PCB.
4. Ob ained Resul s
The p oposed d i e was applied o es on o S ep-
down con e e based on he s a ed C2M0045170D
MOSFET using up o 1000 V swi ched ol age and
wi h he in e connec ion o he powe ansis o
o he p oposed d i e ia coaxial app oxima ely 20 cm
long cable.
Fig. 5: Tes ed d i e p o o ype applica ion.
In Fig. 7 and Fig. 8, he esponses ob ained
wi hin he i s d i e es a e p esen ed. The es
was pe o med wi hou ol age a he powe ci cui .
The swi ching equency up o 500 kHz was achie ed,
o dina y ol age scope p obes we e used.
The ob ained u n-on delay was app ox. 150 ns and
u n - o delay was app ox. 220 ns, see Fig. 8. The low
o e shoo s can be seen wi hin he eached ga e-sou ce
ol age cu e, see Fig. 7 and Fig. 8.
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CIN
UIN
DL
RL
LL
C2M0045170D
Fig. 6: Tes ing powe ci cui diag am.
Fig. 7: D i e p o o ype esponse, no ol age a he powe ci -
cui , inpu d i e signal ol age 1:1 (V) - iole cu e,
eached G-S ol age di ec ly on he powe ansis o 1:1
(V) - blue cu e.
Fig. 8: De ailed d i e p o o ype esponse, no ol age
a he powe ci cui , inpu d i e signal ol age 1:1
(V) - iole cu e, eached G-S ol age di ec ly on
he powe ansis o 1:1 (V) - blue cu e.
I is impo an no o exceed he swi ched MOS-
FET absolu e maximum a ing, which is passed, bu
he inal o e shoo s a e di e en because o he e e se
ans e capaci ance impac , see Fig. 12 and Fig. 13.
The esponses measu ed ia he p obes men ioned
in App. A and App. B a e shown in Fig. 9, Fig. 10,
Fig. 11, Fig. 12, and Fig. 13. The nominal ou pu
capaci ance o he used C2M0045170D MOSFET is
171 pF. The nominal ol age p obe inpu capaci y
is less han 5.5pF ( he d ain connec ed ol age p obe
inpu e minal is no connec ed o he loa ing ol age
po en ial, so he e is no inpu capaci y impac ). As can
be seen, he connec ed ol age p obe inpu capaci y
is much lowe han he MOSFET ou pu capaci y, so
he minimal impac on o he measu ed ansien s a e
can be supposed.
Fig. 9: Ob ained one-pulse swi ching p ocess a UIN = 1000 V,
d ain-sou ce ol age 1:100 (V) - blue cu e, d ain cu -
en 100 mV/A (V) - iole cu e.
Fig. 10: Ob ained swi ching-on p ocess de ail a UIN = 1000 V
- d ain-sou ce ol age 1:100 (V) - blue cu e, d ain
cu en 100 mV/A (V) - iole cu e.
The p oposed p o o ype was es ed ia one-pulse,
which occu ed o 25 µs. The swi ching pulse p ocess
can be seen in Fig. 9, whe e he d ain-sou ce ol age
alls down a he beginning o he swi ching-on p o-
cess, and he d ain cu en lowing h ough he RL
load begins exponen ially g owing up a he same ime.
This is in p og ess un il he beginning o he swi ching-
o p ocess, when he d ain cu en alls down o ze o
and he d ain-sou ce ol age g ows o UIN alue o e
he swi ching-o o e shoo .
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Fig. 11: Ob ained swi ching o p ocess de ail a UIN = 1000 V
- d ain-sou ce ol age 1:100 (V) - blue cu e, d ain
cu en 100 mV/A (V) - iole cu e.
Fig. 12: Ob ained swi ching on p ocess de ail a UIN = 1000 V
- ga e-sou ce ol age measu ed di ec ly on powe an-
sis o (V).
Fig. 13: Ob ained swi ching o p ocess de ail a UIN =
1000 V, ga e-sou ce ol age measu ed di ec ly on
powe ansis o (V).
The highly smoo hed quasi-pe iodic mul i-ha monics
d ain cu en oscilla ions can be obse ed wi hin
he scoped cu es, see Fig. 10 and Fig. 11, which ep-
esen he de ails o he swi ching-on and swi ching-o
p ocesses. These oscilla ions a e caused by a pa asi ic
LC ci cui gene a ed by he induc ance o he wi es
be ween he powe MOSFET sou ce and he load and
by he P-N junc ion capaci y o he load diode DL(see
Fig. 6).
Howe e , he d ain cu en oscilla es sho ly a e
he swi ching-on p ocess is o e , bu he powe an-
sis o pe ec ly swi ches-on wi h no oscilla ions wi hin
he swi ching p ocess. I can be seen in Fig. 10
om he cu e o he d ain-sou ce ol age, which oscil-
la es sligh ly nea he s eady s a e ol age d op alue.
The ob ained ise ime in Fig. 10 is app ox. 40 ns,
which is close o he nominal alue o 20 ns. The nomi-
nal u n-on delay is 65 ns. The used ol age p obe ise
ime is less han 14 ns, which demons a es he possi-
bili y o moni o ing his cu e co ec ly by he p obe.
The d ain cu en quasi-pe iodic oscilla ions can be
also obse ed a he swi ching o -p ocess, see Fig. 11,
bu he d ain-sou ce ol age cu e ises con inuously,
wi hin 20 ns, which is close o he nominal all ime
o 18 ns.
Figu e 12 and Fig. 13 show he ga e-sou ce ol age
measu ed wi hin he same swi ching-on and swi ching-
o p ocess, espec i ely, as i is e lec ed wi hin Fig. 10
and Fig. 11. Some ansposi ions o he d ain cu en
oscilla ions o he ga e-sou ce ol age, can be obse ed
he e, see Fig. 12 and Fig. 13.
Howe e , he o e shoo o he ising slope does no
exceed 25 V, which is he applied MOSFET absolu e
maximum a ing, see Fig. 12.
The alling slope wi hin he swi ching-o p ocess
does no exceed −10 V, which is he used MOSFET
absolu e maximum a ing, see Fig. 13.
5. Conclusion
A new SiC MOSFET d i e is p esen ed in he pape .
I was disco e ed ha he uned up ealized d i e p o-
o ype is able o ich he nominal alues o ise and all
imes o he assigned con olled powe ansis o , e en
hough he e was no e o o localize he d i e as close
as possible o he con olled ansis o . The app ox.
20 cm long coaxial cable was used in his case. Despi e
he ela ed wi e induc ance, he used MOSFET ga e-
sou ce ol age absolu e maximum a ings we e no ex-
ceeded. The s eady s a es ga e-sou ce ol ages we e
se o he ansis o ecommended alues.
The ob ained esul s a e e y bene icial
om he p ac ical poin o iew, because i is
no usually possible o loca e he d i e absolu ely
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nea he d i en powe ansis o acco ding o he con-
e e cons uc ion aspec s. The p oposed solu ion
enables o wo k nea he ansis o limi s and also wi h
he use o a cable be ween he d i e and he powe
ansis o .
The supp essed cu en oscilla ions can be obse ed
a he ends o he swi ching p ocesses. These a e
o igina ed by he esponse o he pa asi ic LC el-
emen o he es ing ci cui . Al hough hese os-
cilla ions a e ans e ed on o ga e-sou ce ol age,
he swi ching p ocesses a e con inuous, which can be
seen om he cu es o he d ain-sou ce ol age.
Acknowledgmen
This wo k was suppo ed by he S uden G an Com-
pe i ion o VSB–Technical Uni e si y o Os a a unde
p ojec SP2021/70 and by he Minis y o Educa ion,
You h and Spo s o he Czech Republic unde p ojec
LTE220001 - E-Town.
Au ho Con ibu ions
J.S. and V.D. c ea ed he concep ualiza ion and o -
mula ed he main ideas o he p oposed de ice includ-
ing he applica ion equi emen s leading o he main
goals. M.S. and D.K. p epa ed he p o o ype design
and wo ked coope a ing wi h V.D. wi hin he p o o-
ype building-up p ocess. J.B. and M.S. pe o med
es ing and inal unning up he p o o ype o ge he
p esen ed ob ained esul s. D.K. and J.B. pe o med
he s a e o he a in es iga ion and J.S. pe o med he
c i ical e i ica ion o he ob ained esul s and w o e
he pape d a iáncluding he o iginal d a p epa a-
ion, and edi ing.
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Abou Au ho s
Jan STROSSA was bo n in P ague, Czech Republic.
He ecei ed his M.Sc. deg ee in Applied Elec onics
om he VSB–Technical Uni e si y o Os a a in 2018.
He is cu en ly a Ph.D. s uden a he Depa men
o Elec onics, Facul y o Elec ical Enginee ing
and Compu e Science, VSB–Technical Uni e si y
o Os a a, and wo ks o Siemens Mobili y Aus ia,
GmbH, R&D a he same ime. His esea ch in e es s
include powe elec onics in he ield o so swi ching
mul ipo DC-DC con e e s.
Vladisla DAMEC was bo n in Ka ina, Czech
Republic. He ecei ed he M.Sc. and Ph.D. deg ees
in Elec onics and Elec ical machines, appa a us and
d i es om VSB–Technical Uni e si y o Os a a,
Czech Republic, in 2000 and 2003, espec i ely. He
wo ks cu en ly o Siemens Mobili y Aus ia, GmbH,
R&D and as an assis an p o esso a Depa men
o Elec onics by VSB–Technical Uni e si y o Os a a
a same ime. His esea ch in e es s include powe
elec onics in he ield o la ge elec ic d i es.
Ma in SOBEK was bo n in F ydek-Mis ek,
Czech Republic, in 1983. He ecei ed he M.Sc. and
Ph.D. deg ees in Elec onics and Elec ical machines,
appa a us and d i es om VSB–Technical Uni e si y
o Os a a, Czech Republic, in 2008 and 2012, espec-
i ely. He wo ks cu en ly as an assis an p o esso
210 ©2021 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING
POWER ENGINEERING AND ELECTRICAL ENGINEERING VOLUME: 19 |NUMBER: 3 |2021 |SEPTEMBER
a Depa men o Elec onics by VSB–Technical
Uni e si y o Os a a. His cu en esea ch in e es s
a e mic op ocesso con ol sys ems, digi al elec onics,
powe elec onics and elec ic d i es.
Daniel KOURIL was bo n in Os a a, Czech
Republic. He ecei ed his M.Sc. deg ee in Applied
Elec onics om he VSB–Technical Uni e si y o Os-
a a in 2017. His esea ch ocused on he Ha dwa e
de elopmen o a mode n p ocesso con ol sys ems
in he ield o elec ic con olled d i es o he use wi h
GA and ANN-based algo i hms.
Jakub BACA was bo n in F ydek-Mis ek, Czech
Republic. He ecei ed his M.Sc. in Applied Elec onics
om he VSB–Technical Uni e si y o Os a a in 2017.
He is cu en ly a Ph.D. s uden a he Depa men
o Elec onics, Facul y o Elec ical Enginee ing
and Compu e Science, VSB–Technical Uni e si y
o Os a a. His main esea ch in e es is cu en ly
ocused on a i icial neu al ne wo ks and hei use
in he ield o elec ic d i es, especially o senso less
con ol o induc ion machine d i es.
Appendix A Used D ain
Cu en P obe
LEM PR50
•Bandwid h BW = 50 MHz.
•Rise ime <7ns.
•Delay ime d<25 ns.
Appendix B Used D ain-Sou ce
Vol age P obe
Teledyne LeC oy AP031
•Bandwid h BW = 25 MHz.
•Rise ime <14 ns.
•Inpu capaci ance d<5.5pF each inpu e minal
o g ound.
©2021 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 211