CONTROL ENGINEERING VOLUME: 12 |NUMBER: 5 |2014 |DECEMBER
On Ladde Diag ams Compila ion and Syn hesis o
FPGA Implemen ed Recon igu able Logic
Con olle
Adam MILIK
Ins i u e o Elec onics, Silesian Uni e si y o Technology, Akademicka 16, 44 100 Gliwice, Poland
[email protected]
Abs ac . The pape p esen s syn hesis p ocess o a
ha dwa e implemen ed econ igu able logic con olle
om a ladde diag am acco ding o IEC61131-3 e-
qui emen s. I is ocused on he o iginally de eloped
a high-pe o mance LD p ocessing me hod. I is able o
p ocess a se o diag ams es ic ed o logic ope a ions
in a single clock cycle independen ly om he numbe
o p ocessed ungs. The pape conside s he compila-
ion o he ladde diag am in o an in e media e o m
sui able o logic syn hesis p ocess acco ding o de el-
oped p ocessing me hod. The enhanced da a low g aph
(EDFG) has been de eloped o he in e media e ep e-
sen a ion o an LD p og am. The o iginal cons uc ion
o he EDFG wi h a ibu ed edges has been desc ibed.
I allows o e icien ep esen a ion and p ocessing o
logic and a i hme ic o mulas. The se o compila ion
algo i hms ha allow o p ese e se ial analysis o de
and o ob ain massi ely pa allel p ocessing uni a e p e-
sen ed. The o e iew o a ha dwa e mapping concludes
he p esen ed conside a ions.
Keywo ds
DFG, FPGA, high-le el syn hesis, IEC61131-3,
LD, logic syn hesis, PLC, econ igu able ha d-
wa e.
1. In oduc ion
The P og ammable Logic Con olle s (PLC) ha e been
used since 1970s and i s hey we e applied o elay
con ol sys ems. Wi hin yea s o as de elopmen o
elec onic echnology, he equi emen s gi en o PLC
become highe all he ime (ope a ing speed, handling
o analog objec s, he inc easing eliabili y, e c.). To-
day, he a eas o PLC applica ions include small com-
plexi y p ocesses as well as la ge manu ac u ing lines.
The gene al concep o a PLC is based on he mic o-
p og ammable ci cui s. I consis s o wo insepa able
pa s ha a e a ha dwa e pla o m and so wa e. The
Ha dwa e pla o m is able o execu e gi en se o logic
and a i hme ic ins uc ions. A con ol algo i hm is c e-
a ed in he o m o ins uc ions sequence [1], [2], [8].
In con as o so wa e cen ic solu ions, ha dwa e
o e s in insic pa allel execu ion o he asks. I adi-
cally educes he esponse ime and o e s be e pe o -
mance han so wa e solu ions. The implemen a ion o
he con ol algo i hm wi h he use o ep og ammable
and econ igu able logic has been p oposed by di e -
en esea ch g oups [3], [4], [5], [9], [11], [13], [15], [16],
[19]. The e ha e been p oposed a cus om FPGA a chi-
ec u e o di ec mapping o he LD logic [17]. The
signi ican limi a ion in wide use o ep og ammable
digi al ci cui s is a high design complexi y o he imple-
men a ion p ocesses (in compa ison o he ins uc ion
based s anda d app oach).
A se o ools o c ea ing a econ igu able con olle
and i s di ec p og amming wi h well de ined and com-
monly used ladde diag am has been de eloped. P e-
sen ed wo k concen a es on ans o ming o con ol
algo i hm designed wi h he use o he ladde diag am
in o a o m sui able o he en i e p ocess o ha dwa e
implemen a ion inco po a ing: op imiza ion, schedul-
ing and ha dwa e mapping. The e has been consid-
e ed de ails o he LD p og am execu ion acco ding o
IEC61131-3 equi emen s.
An in e media e o m o he con ol p og am has
been de eloped acco ding o conside ed s anda d e-
qui emen s. Algo i hms, p esen ed in his pape , a e
a pa o he de eloped concep o econ igu able logic
con olle s amilies and oolse o hei p og amming
acco ding o he IEC61131-3 e e ence manual.
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2. The LD Execu ion Model
The LD ne wo k is widely used me hod o desc ibing
con ol algo i hms [1]. This me hod has been inhe i ed
om elay con ol sys ems. Con ac s and coils ep e-
sen logic dependencies be ween signals and unc ion
blocks. Acco ding o IEC61131-3 equi emen s a ne -
wo k is analyzed in a ow based ashion ha e alua es
powe low h ough componen s ung by ung. In con-
as o he elec ical schema ic diag am he powe low
is unidi ec ional. The powe is ansmi ed om he
le ail o he igh . The e a e implied limi a ions ha
p ohibi o e e se powe low in ladde schema ic [8].
Sequen ial analysis o schema ic p oduces an o de ed
sequence o ins uc ions o a PLC (Fig. 1). A swi ch
is ans o med in o a logic AND ope a ion. This ope -
a ion is pe o med be ween cu en esul coming om
he p edeceasing node and a signal ha con ols he
swi ch. A junc ion me ges powe low coming om
se e al ungs. In some cases, he e is a need o c ea -
ing a iables ha enables s o age o pa ial esul s o
nes ed ope a ions.
Fig. 1: The ladde diag am and i s equi alen ins uc ion se-
quence.
The LD ne wo k p ocessing speed can be inc eased
by pa allel execu ion o he logic ope a ion in p o-
g ammable ha dwa e. T ans o ming logic dependen-
cies in o combina o ial logic allows inc easing pe o -
mance se e al o de s o magni ude. I is equi ed o
de elop a uni e sal me hod sui able o ep esen ing
no only LD p og ams, bu o he p og amming me h-
ods speci ied by IEC61131. This me hod should be able
o syn hesize logic ope a ion, bu also o he ope a ions
pe o med by PLCs (e.g. ime s, coun e s, a i hme ic
ope a ions).
2.1. Exis ing Syn hesis Models o
LD
An LD diag am is desc ibed by wo se s o Boolean
a iables Iand Q. The se Iconsis s o a iables asso-
cia ed wi h inpu s while he se Qconsis s o a iables
associa ed wi h ou pu s and in e nal ma ke s. The
logic unc ions a e de ined by ungs and c ea e an o -
de ed sequence o Boolean exp essions:
qi= i(I, Q), i = 1... , (1)
whe e iis he ung index. Equa ion (1) de ines he
o de ed sequence o p ocessing acco ding o he index
i. This ea u e has been u ilized in implemen a ions
p oposed by [9], [10], [16].
An exempla y LD ne wo k and i s implemen a ion
ha e been p esen ed in he igu e (Fig. 2). In his
model each ung is p ocessed in indi idual cycle. The
con olle esponse ime is p opo ional o he num-
be o ungs in a p og am. In compa ison o he p o-
g amma ic app oach, his model educes a compu a-
ion ime o logic unc ions. I can be no iced ha
calcula ions o some a iables can be p ocessed in pa -
allel. Dis ibu ing calcula ion p ocess o each ung (q
a iable) in oduces edundan cycles. In conside ed
diag am (Fig. 2) a iables q1and q3do no depend on
o he q a iables. The q1 a iable and he q3can be
e alua ed in he i s cycle ( 1).
Fig. 2: The LD ne wo k (A) and i s equi alen (B).
In o de o educe he numbe o calcula ion cycles
dependencies be ween qi a iables ha e o be de e -
mined. In he pape [6] au ho s in oduced an idea o
using dependencies and simul anei ies g aphs o c ea -
ing a sequen ial unc ional cha (SFC) om gi en LD.
This idea has been employed in [3] o c ea ing op i-
mized ha dwa e desc ip ion. Simila idea has been em-
ployed in [15] o con ol algo i hm pa i ioning. Du -
ing he analysis o he LD, a dependencies g aph is
c ea ed. This is a di ec ed g aph ha consis s o nodes
ep esen ing all qi a iables. The node i( ep esen ing
a iable qi) is connec ed by di ec ed edge wi h node j
only i unc ion idepends on a iable qjand i>j:
( j, i)↔ i(qi)6=cons . (2)
The numbe o elemen a y cycles based on depen-
dencies analysis is equal o:
T=pmax + 1,(3)
whe e pmax is he longes pa h in he dependencies
g aph.
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2.2. The LD High-Pe o mance
Syn hesis Model
P esen ed dependency analysis o he ladde diag am
is di ec ly de i ed om sequen ial execu ion model.
The e a e conside ed ungs as independen uni s de-
li e ing a iables alue. The ea ly app oaches conside
each ung o be dependan o p edeceasing ungs. The
execu ion is pe o med in se ial ashion a ung by a
cycle. Applying ung dependencies analysis allows o
de e mine he calcula ion dependencies in he o m o
he g aph which is used o imp o ed ungs scheduling.
The LD can be conside ed as a sequence o ope a-
ions. Le assume ha a iables associa ed wi h inpu s
a e upda ed be o e he s a o he calcula ion p ocess
and emain cons an du ing i . Le in oduce he se
o a iables D ha a e assigned wi h a alue o p o-
cessed exp essions. Value o he a iable diis assigned
o a iable qia he end o calcula ion cycle (qi=di).
This app oach allows o dis inguish be ween wo alues
ha a e calcula ed in he p esen cycle (di) and in he
p e ious cycle (qi). Equa ion (1) o m h ung can be
ew i en in ollowing o m:
dm= m(I, d0, ..., dm−1, qm, ..., qn),(4)
qm=dm.(5)
Using p oposed subs i u ion o q a iables allows o
p opaga e calcula ion esul s h ough all unc ions by-
passing egis e s (Fig. 3). The cu en alue o con ol
p ocess is upda ed by single clock pulse a e calcu-
la ing all di alues. In p esen ed o m he calcula ion
p ocess is ully pa allel and comple es in a single cycle
ha ans e s alues om d o espec i e q a iables.
Fig. 3: The LD ne wo k (A) and i s ha dwa e equi alen ob-
ained wi h p oposed syn hesis me hod (B).
3. In e media e
Rep esen a ion wi h he
Use o Da a Flow G aphs
I is equi ed o de elop app op ia e ep esen a ion o
an in e media e o m o con ol algo i hm ha is sui -
able o high-le el syn hesis p ocess. The in e medi-
a e o m should be able o ep esen logic and a i h-
me ic ope a ions pe o med by PLCs main aining op-
e a ion sequence and e iling i s dependencies. Com-
monly used o m o in e media e ep esen a ions o
logic syn hesis and compile s a e da a low g aphs [7].
A node o he g aph ep esen s elemen a y ope a ion
while di ec ed edges indica e p ocessing low be ween
nodes.
3.1. The EDFG Concep
Fo he pu pose o eco ding PLC p og ams, he au-
ho has de eloped a o m o enhanced da a low g aph
(EDFG). This has been inspi ed by concep o a -
ibu ed edges used in BDD in oduced by Mina o [14].
In a simila way he EDFG handle una y ope a ions
like logic in e sion and a i hme ic complemen . The
o he implemen ed ex ension is a mul iple a gumen
node o commu a i e ope a ions. P esen ed modi ica-
ions allow o e icien c ea ing o da a low g aph and
educes algo i hmic complexi y.
The Ex ended Da a Flow G aph is gi en by G=
hV, Eiwhe e Vis a se o nodes ep esen ing elemen-
a y ope a ions and Eis a se o di ec ed edges wi h
a ibu es. The di ec ed edge e∈Eis desc ibed by
iple e=h S, D, aiwhe e Sis a p edeceasing node
and Dis a successo node o he di ec ed edge. The a
is an a ibu e o he selec ed om he se Ao allowed
a ibu es.
Fig. 4: Compa ison o he gene al DFG (1) wi h EDFG (2).
An equi alen DFG o he Boolean o mula y=
a·¯
b·c+d·¯eis p esen ed in he igu e (Fig. 4). The e
ha e been conside ed wo cases: a s anda d app oach
DFG (1) and wi h he use o he EDFG (2). The DFG
(1) implemen s logic in e sion by sepa a e NOT nodes.
In oducing a ibu ed edges wi h logic in e sion elim-
ina es a NOT node EDFG (2). The a ibu ed edge
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no only educes he numbe o nodes in he diag am,
bu also allow o simpli y logic ope a ion handling.
Figu e 5 shows he g aph ans o ma ions o logic
nodes. One o he common ope a ion a e compila ion
p ocess is ope a ion me ge. Using EDFG simpli ies he
algo i hms o node me ging. P edeceasing node can be
me ged i i is connec ed wi h simple edge and bo h
nodes implemen he same logic ope a ion. (shown in
Fig. 5.1.). The e e ence node is ma ked wi h g ay
colo . The ope a ion is pe o med by modi ying g aph
edges. The e is exchanged D ha equals 1 o 2. The
me ge ule can be ex ended wi h he use o de Mo -
gan’s laws. In he case (Fig. 5.2.) he p edeceasing
node is connec ed wi h in e ed edge and implemen s
opposi e logic unc ion (AND↔OR) o he e e ence
node. The ope a ion is pe o med by exchanging he
D ha equals 2 o 4and he edge a ibu e is in-
e ed. Finally, he 2node is emo ed The inal EDFG
is p esen ed in Fig. 5.3.
Fig. 5: Implemen a ion o node me ge (1) and de Mo gan’s laws
(2) in DFG wi h a ibu ed edges.
Thanks o a ibu ed edges simila lexibili y is
achie ed o a i hme ic ope a ions. In he domain o
a i hme ic ope a ions, he sub ac ion node is eplaced
by an edge wi h complemen alue a ibu e. I educes
he se o a i hme ic ope a ions o: addi ion, mul ipli-
ca ion and di ision. The igu e (Fig. 6) shows he im-
plemen a ion o he exp ession: y=a+b−c+d−eand
compa es he use o a ibu ed edges o a i hme ic op-
e a ions. Using a s anda d app oach wi h sepa a e ad-
di ion and sub ac ion nodes is shown in Fig. 6.A. Sim-
ila esul is achie ed using a ibu ed edges (Fig. 6.B).
The a ibu ed edges simpli y algo i hms o ope a ion
me ge and cons an p opaga ion as shown in Fig. 6.C.
Fig. 6: Compa ison o he gene al DFG (A) and he EDFG
(B, C).
4. Con e ing LD o EDFG
The compila ion p ocess deli e s basic i ems o a lan-
guage [18]. Subsequen algo i hms show sys ema ic
me hods o ansla ing hose i ems in o an EDFG sui -
able o ha dwa e mapping.
4.1. Va iables
The a iables a e decla ed a he beginning o a ne -
wo k acco ding o IEC61131-3 equi emen s. Fo he
pu pose o he syn hesis p ocess he a iables se is di-
ided in o h ee subse s. The a iable classi ica ion is
based on he signal associa ion o inpu , ou pu and in-
e nal ma ke a eas. The a iable educ ion p ocedu e
akes in o conside a ion a iables membe ship. Va i-
ables associa ed wi h inpu signals a e allowed o be
ead while alue assignmen is implied and made om
inpu signals. Va iables associa ed wi h ou pu s and
ma ke s a e allowed o ead and w i e access. The
a iables associa ed wi h ma ke s can be elimina ed
when only w i e access is de ec ed. The e a e wo
possible cases. The i s one when a a iable is used
as a empo a y s o age o dis ibu ing he alue and
he o he one when a a iable is unused. The unused
a iable is dis inguished as he only sink o he d i -
ing node. Va iables associa ed wi h ou pu signals and
ma ke s a e no allowed o be ead wi hou alue as-
signmen . The momen o assignmen is independen
o he ead access bu mus be comple ed a leas once
in en i e calcula ion cycle.
The a iable alue access implemen a ion assu es se-
quen ial a iable access acco ding o LD desc ip ion.
In o de o sa is y his equi emen , a a iable cu en
alue is accessed by ollowing algo i hm.
Algo i hm 1: Le he xis a a iable ha he alue
is going o be ead by node , xW R is an assignmen
node o he x a iable, xDRV is he node deli e ing
alue o he a iable x. The a iable x e e s o EDFG
nodes h ough he able poin ing ead and w i e nodes
(Fig. 7). The DRV (i exis s) is connec ed wi h a di-
ec ed edge wi h xW R. The xRD is a alue eading
node o he x a iable. Following wo cases a e pos-
sible depending on he alue assignmen sequence. I
he a iable x alue is no assigned han he xW R node
does no exis . The alue o he x a iable is ead by
c ea ing he xRD node ( his no i ies ha he alue is
coming om he p e ious cycle – e.g. o wa d coil e -
e ence). The xRD node becomes he a gumen o he
node (Fig. 7.1). I he a iable x is assigned he xW R
node exis s. The di ec ed edge connec s i wi h d i ing
node DRV . The DRV is used o d i ing he node
(Fig. 7.2). The a ibu e o he edge is inhe i ed. I
should be no iced ha his mechanism ollows ecen ly
assigned alue o he x a iable.
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Fig. 7: The a iable alue access algo i hm.
4.2. Nodes
The ladde diag am node me ges powe low coming
om mul iple sou ces. I should deli e a logic sum
o all connec ed signals. A gene al algo i hm ha ac-
cep s mul iple d i e s o a node is used. P ocess s a s
om he a iable decla a ion. The a iable name is in-
he i ed om ne wo k node name (au oma ically gene -
a ed). I is included in o a subse o in e nal signals.
Algo i hm 2: Le he xis a a iable associa ed wi h a
schema ic node (junc ion), xW R is he x a iable alue
assignmen node, Cis he g aph node ha is going
o d i e he x a iable, Pis he node ha cu en ly
d i es he x a iable. The e a e wo possible cases. I
he x a iable is no assigned han he xW R node does
no exis . The Cnode is connec ed wi h newly c e-
a ed xW R node (Fig. 8.1). I he x a iable is al eady
assigned hen he xW R node exis s. In his si ua ion,
he OR node is c ea ed. Nodes Pand Ca e con-
nec ed o OR node. The OR node becomes he only
d i e o xW R (Fig. 8.2). The desc ibed algo i hm can
be epea ed i e a i ely o nodes wi h mul iple d i ing
sou ces.
Fig. 8: The i e a i e con e sion o he LD node in o equi alen
EDFG.
4.3. Swi ches
A swi ch is a basic componen used o c ea ing he
logic AND ope a ion be ween d i ing and inpu sig-
nals. The swi ch is con e ed in o EDFG equi alen
ha has been shown in he Fig. 9. The EDFG p o-
cedu e u ilizes wo p e iously desc ibed algo i hms o
a iable access and node d i ing.
Algo i hm 3: Le he xis a a iable associa ed wi h
an inpu node, ais a a iable d i ing he swi ch and
yis a a iable associa ed wi h he ou pu node. The
AND node is c ea ed o conside ed swi ch. The alue
o he xand a a iables a e accessed wi h he use o he
algo i hm 1. The p ocedu e e u ns espec i e d i ing
nodes ha a e connec ed o he AND node. The a -
ibu e o he edge o a iable ais se o a logic in e -
sion o no mally closed swi ch (Fig. 9.2). The AND
node assigns alue o he y a iable. The assignmen
is pe o med acco ding o he algo i hm 2.
Fig. 9: The EDFG swi ch equi alen .
4.4. Coils
The coil assigns o eassigns alue o a pa icula a i-
able. Following algo i hm is used o ob aining EDFG
om a coil i em. This algo i hm is adop ed o coope -
a e wi h emaining compila ion algo i hms, especially
wi h a iable alue access.
Algo i hm 4: Le he ais a d i ing signal, yis he
a iable associa ed wi h a signal d i en by he coil.
The a iable alue is ead acco ding o he algo i hm 1
ha e u ns d i ing node aD. Re u ned aD node is
assigned o he a iable y. I a alue assignmen node
yW R does no exis i is c ea ed and linked wi h aD
(Fig. 10.1). I he a iable yis al eady assigned han
he di ec ed edge is econnec ed o he ecen d i ing
node (Fig. 10.2). The edge a ibu e is se acco ding
o he coil ype (e.g. in e ed coil - Fig. 10.3).
Fig. 10: The coil compila ion scheme.
4.5. Func ional Modules
The complex a i hme ic o mixed a i hme ic-logic
unc ionali y o he con olle is implemen ed wi h he
use o unc ional blocks. In he o m o blocks a e im-
plemen ed ime s, coun e s and a i hme ic unc ions
[1], [8]. Those blocks a e con olled by logic and a i h-
me ic signals. All logic signals a e connec ed in o lad-
de ne wo k while nume ic a iables a e e e enced by
iden i ie s (names).
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All hese blocks pe o m condi ional execu ion con-
olled by inpu logic signals. This implies he condi-
ional execu ion o a i hme ic ope a ions. The EDFG
equi es in oduc ion o he condi ional selec ion node
ha implemen selec ion and assu es pa allel ope a ion
execu ion). The condi ional selec ion node shown in
Fig. 11.1 e lec s he high-le el syn hesis concep based
on EDFG. I enables selec ion be ween a gumen s o
same da a ype and can be used o low con ol in
logic and a i hme ic pa hs. The op imiza ion p ocess
can be sepa a ely applied o he da a pa hs and con-
ol (selec ion inpu ) pa h. The addi ional op imiza-
ion ules a e de ined o selec ion nodes. This is im-
po an o op imiza ion pe o med in a i hme ic op-
e a ions pa hs. When conside ed o logic pa hs he
condi ional node is ans o med in o mul iplexe equa-
ion o med om logic nodes. This ope a ion c ea es
consis en logic EDFG ha u he can be op imized.
Fig. 11: The EDFG condi ional selec in node (1) and gene al
implemen a ion EDFGimplemen a ion o a i hme ic
blocks (2).
The exempla y gene al a i hme ic module is shown
in Fig. 11.2. This block pe o ms calcula ions condi-
ionally depending on he enable (en) signal. An a i h-
me ic block is combined in o EDFG be ween sou ce
and sink nodes. Condi ional execu ion o he block
o ces an au oma ic a iable implemen a ion. I is
achie ed by execu ing algo i hm 1 o he ou pu a i-
able be o e calling assignmen algo i hm 4 This a i-
able is esponsible o d i ing ou pu when block is
disabled (en = 0). The op imiza ion p ocedu es o se-
lec ion nodes allow o elimina ing co e ed by logic con-
di ion in e media e nodes. A he block le el he e a e
used wo di e en alue assignmen p ocedu es. Fo
logic a iables, he algo i hm 2 is used while o nu-
me ic a iables he algo i hm 4 desc ibed o coils is
used.
The igu e (Fig. 12) shows an EDFG implemen a ion
o TON ime . This block is deli e ed in he o m o
sub EDFG ha is inco po a ed in o inal EDFG du ing
he compila ion p ocess. The ime is a speci ic imple-
men a ion o a coun e . I decla es a hidden clocking
signal ha is igge ed wi h ime base pe iod. This
signal enables coun ing o he ime uni . I is d i en
om he con olle amewo k c ea ed du ing he im-
plemen a ion phase. Simila ly o he a i hme ic mod-
ules, he e a e decla ed in e nal a iables esponsible
o s o ing elapsed ime (e ) and ime ac i i y (q).
Fig. 12: The ime on equi alen sub EDFG.
5. The EDFG Ha dwa e
Mapping
A syn hesizable HDL model op imized o an FPGA
a ge is ob ained om desc ibed EDFG s uc u e.
The mapping p ocedu e o an EDFG s a s om he
op imiza ion p ocess. The EDFG allows o limi ed
op imiza ion o he logic ope a ions as p esen ed in
chap e 3. A e ini ial ope a ion me ge and logic ab-
so p ion, he Esp esso minimiza ion is used. This al-
lows o u he educ ion o he logic ope a ions and
op imiza ion o unused pa hs. In he domain o he
a i hme ic ope a ion, a cons an me ge and common
subexp ession ex ac ion a e pe o med. Finally, mul-
iple a gumen a i hme ic nodes a e expanded in o a
wo a gumen nodes ha can be di ec ly mapped in o
a i hme ic modules (adde s and mul iplie s). The ex-
pansion p ocess balances he p opaga ion delay o op-
e a ions in EDFG pa hs [12].
Fig. 13: The EDFG scheduling and mapping p ocess.
The op imized EDFG is a subjec o scheduling. I
can be di ec ly implemen ed wi h he use o g eedy
app oaches wi h ALAP o ASAP scheduling me hods
[7]. In con as o logic ope a ions, a i hme ic ope -
a ions esou ce equi emen s a e much highe . The
g eedy mapping app oach will lead o quick esou ces
un ou . To o e come his limi a ion, a scheduling
me hod based on lis app oach wi h o iginal ope a-
ion so ing is applied. The ope a ion schedule akes
in o conside a ion he ope a ion mobili y and local de-
pendencies. Scheduled nodes a e mapped in o a se
o a i hme ic esou ces. A e ope a ion schedule, he
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egis e alloca ion is made wi h he use o modi ied le
edge algo i hm. Schema ically EDFG ha dwa e map-
ping p ocess is shown in (Fig. 13). The e is shown a
schedule esul in he o m o an EDFG (Fig. 13.1). On
he g aph a e ma ked: ope a ion s a ime (c) ope -
a ion end ime ( 0) and las access ime o he esul
( 1). Ob ained mapping e lec s he ha dwa e s uc-
u e shown in Fig. 13.2.
The mapping p ocedu e op imizes he esou ce dis-
ibu ion by minimizing he cos o a gumen mul i-
plexing. S uc u e o he con olle and p inciples o
i s ope a ion a e shown schema ically in Fig. 14. The
speci ic EDFG depic s he alloca ed egis e s (small
ci cles) and ope a ions (la ge ci cles). The hick line
connec ing small ci cles deno es he a iable li e ime.
The e a e h ee compu a ion s ages. The calcula ion
p ocess s a s om image egis e s upda e and in e nal
a iables exchange. A e his ope a ion, a calcula ion
p ocess akes place. The cycle is ended wi h a esul
w i e back.
Fig. 14: The calcula ion cycle and i s EDFG ep esen a ion
wi h ma ked a iable li e ime.
The p oposed me hod o implemen a ion has been
compa ed wi h di ec EDFG mapping app oach. The
esul a e p esen ed in Tab. 1. The e has been selec ed
3 ep esen a i e FPGA amilies ha a e Spa an II,
Spa an 3 and Spa an 6. The Spa an II and he
Spa an 3 a e equipped wi h 4 inpu LUTs while he
Spa an 3 is addi ionally equipped wi h combina o ial
18x18 mul iplie s. The Spa an 6 amily is equipped
wi h 6 inpu LUTs and DSP48A1 uni s. Fo illus a -
ing implemen a ion, wo ep esen a i e p ojec s o au-
oma ic con ol ha e been chosen. The C2 p ojec im-
plemen s double PID con olle wi h low pass il e ing
and hys e esis igge . The T8 p ojec implemen s he
cascade o 8 ime s con olling ime dependan p ocess.
The op imiza ion p ocess can in luence he con olle
esponse ime by ex ending calcula ion ime due o e-
sou ce sha ing. In he case o he C2 p ojec he e was
used me hod o esou ce sha ing ha p ohibi s pe o -
mance loss. This app oach p esen s a non- edundan
g eedy assignmen accommoda ed o FPGA a chi ec-
u e sha ing. In gene al, he con olle a ea has been
educed be ween 50 % - 60 % o he ini ial a ea. The e
can be obse ed a s ong educ ion o mul iplie s usage
(50 %).
Tab. 1: The FPGA esou ce usage compa ison.
FPGA P oj. Di ec Op Gain
[LUT/MUL] [%]
Spa an II
(LUT4)
C2 1021/- 612/- 59.9 %
T8 341/- 93/- 27.2 %
Spa an 3
(LUT4 + MUL)
C2 1252/4 717/2 57.2 %
T8 341/- 93/- 27.2 %
Spa an 6
(LUT6 + DSP)
C2 1274/4 598/2 46.9 %
T8 205/- 95/- 46.3 %
The T8 p ojec s demons a e he idea o esou ce
sha ing wi h an accep able inc ease o esponse ime.
In he case o ime s, he la s uc u e esponse ime
is 2 cycles. Fo his s uc u e, he algo i hm akes
bene i s o m use o dis ibu ed RAMs ha allows o
educe esou ce equi emen s abou 3.67 imes on ex-
pense o esponse ime inc ease. This me hod is ap-
plicable when con olle pe o ms o he calcula ion o
pe o mance educ ion is accep able.
6. Conclusion
The pape p esen s en i e syn hesis p ocess o ha d-
wa e implemen ed econ igu able logic con olle om
a ladde diag am o ha dwa e mapping. The pape is
ocused on he compila ion o he ladde diag am in o
an in e media e o m sui able o logic syn hesis p o-
cess. As i was p esen ed, chosen in e media e o m
and me hods o c ea ing i has ex emely high impac
on he inal esul o he syn hesis. The au ho has de-
eloped a me hod o in e media e ep esen a ion based
on he enhanced da a low g aph ha u ilize a ibu ed
edges. I signi ican ly simpli ies he g aph cons uc-
ion and p ocessing. The in e media e o m is c ea ed
om he ladde diag am wi h he use o p esen ed al-
go i hms. Due o limi ed space only gene al o e iew
o he LD compila ion has been desc ibed. The e a e
also de eloped me hod o ep esen ing a i hme ic op-
e a ions and complex unc ional blocks like ime s and
coun e s.
The g aph ep esen a ion is well sui ed o u he
p ocessing o ien ed o FPGA implemen a ion. Finally,
a b ie o e iew o mapping and implemen a ion o
syn hesizable HDL desc ip ion was gi en. De eloped
op imiza ion me hods allow o educe con olle size
be ween 1.66 – 2.13 imes wi hou pe o mance loss.
Signi ican educ ion o he con olle size (abou 3.6
imes) is obse ed o implemen a ion whe e speci ic
ea u es o FPGAs a e used and li le pe o mance loss
is accep able.
P esen ed algo i hms belong o o iginally de eloped
a ha dwa e PLC syn hesis ool capable o syn hesiz-
ing cus om ha dwa e implemen a ion om LD, IL and
SFC [11], [12]. The compila ion and syn hesis ool is
subjec o ongoing esea ch and de elopmen . I is
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planned o ex end a i hme ic suppo o loa ing poin
numbe s and imp o ing scheduling and mapping p o-
cesses.
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Abou Au ho s
Adam MILIK ecei ed M.Sc. and Ph.D. deg ees
om Silesian Uni e si y o Technology o Gliwice
in 1997 and 2003 espec i ely. Since 2003 he is a
p o esso assis an a Silesian Uni e si y o Technology
o Gliwice. His main in e es s and esea ch a eas
a e: high-le el logic syn hesis and implemen a ion,
algo i hm implemen a ion, echnology mapping in
FPGA de ices, he ha dwa e high-le el modeling
sys ems based on HDLs and i s in eg a ion wi h o he
ools like MATLAB, Simulink o Sys emVue.
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