senso s
A icle
A Dynamic Th eshold Cancella ion Technique o a
High-Powe Con e sion E iciency CMOS Rec i ie
An ónio Godinho 1,†, Zhaochu Yang 1,†, Tao Dong 2,*, Luís Gonçal es 3, Paulo Mendes 3, Yumei Wen 4, Ping Li 4
and Zhuangde Jiang 1


Ci a ion: Godinho, A.; Yang, Z.;
Dong, T.; Gonçal es, L.; Mendes, P.;
Wen, Y.; Li, P.; Jiang, Z. A Dynamic
Th eshold Cancella ion Technique o
a High-Powe Con e sion E iciency
CMOS Rec i ie . Senso s 2021,21, 6883.
h ps://doi.o g/10.3390/s21206883
Academic Edi o s: Jong-Ryul Yang
and Seong-Tae Han
Recei ed: 24 Sep embe 2021
Accep ed: 13 Oc obe 2021
Published: 17 Oc obe 2021
Publishe ’s No e: MDPI s ays neu al
wi h ega d o ju isdic ional claims in
published maps and ins i u ional a il-
ia ions.
Copy igh : © 2021 by he au ho s.
Licensee MDPI, Basel, Swi ze land.
This a icle is an open access a icle
dis ibu ed unde he e ms and
condi ions o he C ea i e Commons
A ibu ion (CC BY) license (h ps://
c ea i ecommons.o g/licenses/by/
4.0/).
1
Chongqing Key Labo a o y o Mic o-Nano Sys ems and Sma T ansduc ion, Collabo a i e Inno a ion Cen e
on Mic o-Nano T ansduc ion and In elligen Eco-In e ne o Things, Chongqing Key Labo a o y o Colleges
and Uni e si ies on Mic o-Nano Sys ems Technology and Sma T ansducing, Na ional Resea ch Base o
In elligen Manu ac u ing Se ice, Chongqing Technology and Business Uni e si y,
Chongqing 400067, China; [email p o ec ed] (A.G.); [email p o ec ed] (Z.Y.);
[email p o ec ed] (Z.J.)
2Depa men o Mic osys ems (IMS), Facul y o Technology Na u al Sciences and Ma i ime Sciences,
Uni e si y o Sou h-Eas e n No way, 3616 Kongsbe g, No way
3Cen e o Mic oElec omechanical Sys ems (CMEMS-UMinho), Uni e si y o Minho, 4800-058 Guima ães,
Po ugal; [email p o ec ed] (L.G.); [email p o ec ed] (P.M.)
4School o Elec onic In o ma ion and Elec ical Enginee ing, Shanghai Jiao Tong Uni e si y,
Shanghai 200240, China; [email p o ec ed] (Y.W.); [email p o ec ed] (P.L.)
*Co espondence: [email p o ec ed]
† Au ho s whom i s au ho ship is sha ed by An ónio Godinho and Zhaochu Yang.
Abs ac :
Powe con e sion e iciency (PCE) has been one o he key conce ns o powe managemen
ci cui s (PMC) due o he low ou pu powe o he ib a ional ene gy ha es e s. This wo k epo s a
dynamic h eshold cancella ion echnique o a high-powe con e sion e iciency CMOS ec i ie . The
p oposed ec i ie consis s o wo s ages, one passi e s age wi h a nega i e ol age con e e , and
ano he s age wi h an ac i e diode con olled by a h eshold cancella ion ci cui . The o me s age
conduc s he signal ull-wa e ec i ica ion wi h a ol age d op o 1 mV, whe eas he la e educes he
e e se leakage cu en , consequen ly enhancing he ou pu powe deli e ed o he ohmic load. As
a esul , he ec i ie can achie e a ol age and powe con e sion e iciency o o e 99% and 90%,
espec i ely, o an inpu ol age o 0.45 V and o low ohmic loads. The p oposed ci cui is designed
in a s anda d 130 nm CMOS p ocess and wo ks o an ope a ing equency ange om 800 Hz o
51.2 kHz, which is p omising o p ac ical applica ions.
Keywo ds:
ib a ion ene gy ha es e ; powe managemen ci cui ; CMOS ec i ie ; dynamic h esh-
old cancella ion echnique; high powe con e sion e iciency
1. In oduc ion
P esen ly, ene gy ha es ing appea s as a p omising eliable echnology ha can
p olong he li e ime o ba e ies and powe wi eless senso ne wo ks (WSNs) o en i-
onmen al moni o ing [
1
]. Howe e , in hese WSN applica ions, ambien ib a ions a e
unp edic able, ime- a ying, and low ampli ude, which es ic s he a ailable powe o he
ene gy ha es ing sys em [
2
]. To o e come hese d awbacks, esea ch g oups ha e been
ocusing on using piezoelec ic ha es e s due o hei high powe densi y and capabili y o
in eg a e MEMS and CMOS echnology, making i possible o de elop all he sys ems (en-
e gy ha es e and elec onic sys em) in a single chip [
3
–
5
]. Thus, o maximize he amoun
o ene gy ans e ed unde di e en ambien condi ions, a powe managemen ci cui
(PMC) is c ucial in o de o ex ac , con e , s o e, egula e, and manage he sca enged
ene gy om he piezoelec ic de ice [6,7].
Because he ib a ional ene gy sou ces p oduce AC signals, sca enging such ene gy
equi es a ull-wa e ec i ie as a key ci cui inside he PMC, which allows he AC/DC
Senso s 2021,21, 6883. h ps://doi.o g/10.3390/s21206883 h ps://www.mdpi.com/jou nal/senso s
Senso s 2021,21, 6883 2 o 13
con e sion o p ope ly powe he WSNs. Howe e , because he ou pu powe o he
ib a ional ene gy ha es e is low [
4
], he high o wa d ol age equi ed by s anda d
ull-wa e diode b idges and Scho ky diode ec i ie s limi s hei use on hese low powe
es ic applica ions [
8
]. To su pass hese limi a ions, diode-connec ed MOS ansis o s
ha e been widely used because hey p esen simila I-V cha ac e is ics o he s anda d
diodes. Thus, designing he ec i ie in CMOS echnology is highly desi able o dec ease
he de ice’s o m ac o and easily in eg a e wi h he ene gy ha es e while explo ing new
dynamic echniques o educe he powe consump ion, achie e high PCE, and minimize
leakage cu en [9,10].
Recen wo k has been de eloping dynamic h eshold echniques o educe he h esh-
old ol age e ec [
11
]. Add essing hese echniques allows o he educ ion o o al ol age
d op and mi iga ion o he e e se leakage cu en in he ac i e s age. By a ending o
hese conce ns du ing he design o he ci cui , i is possible o minimize he ci cui ’s
o e all powe and leakage cu en consump ion. Thus, all hese condi ions we e ca e ully
conside ed du ing he design o he p oposed high-powe e iciency CMOS ec i ie o
a end o he demands o his applica ion.
In his wo k, a new CMOS ec i ie s uc u e o piezoelec ic ene gy ha es e s is
p esen ed. I combines a passi e s age nega i e ol age con e e (NVC) wi h an ac i e
diode con olled by a dynamic h eshold cancella ion ci cui o build a new a chi ec u e
ha can educe i s o al ol age d op. Wi h his con igu a ion, a ol age d op lowe han
2 mV can be achie ed in he second s age, which consequen ly enhances ea u es such as
VCE and PCE, as well as educes he e e se leakage cu en ha lows om he load.
2. CMOS Rec i ie s
2.1. Passi e Rec i ie s
The CMOS ga e c oss coupled can eplace he con en ional ull-wa e b idge ec i ie
o o e come he high o wa d ol age d op because i allows a minimum inpu ol age o
ope a e [
10
,
12
,
13
]. Howe e , his opology s ill lacks e iciency due o he h eshold ol age
(VTH) d op ac oss he diode connec ed in each conduc ion pa h [13].
The ully c oss-coupled ec i ie in ends o ul ill he gap o he p e ious con igu a ion
by elimina ing all
VTH
d ops, which educes he ol age d op ac oss his s age [
13
]. Conse-
quen ly, his opology imp o es bo h PCE and VCE o he ci cui [
13
]. Howe e , he e e se
leakage cu en appea s o be he main disad an age o using his single con igu a ion,
which a ec s he powe ans e ed om he ci cui o he load [
10
]. Thus, an ex a ci cui
mus be added o o e come his issue.
2.2. Ac i e Rec i ie s
To p e en he ci cui om e e se leakage cu en , he CMOS passi e ec i ie s
combined wi h an ac i e con igu a ion can mi iga e he e e se leakage cu en o enhance
he DC powe o he load [
14
–
19
]. In hese ac i e con igu a ions, compa a o s a e designed
o con ol he ga e ol age o he ac i e diode (o so-called he main ansis o ) depending
on i s inpu and ou pu ol age condi ions. In wo k done by Pe e s e al. [
15
], an ac i e
ec i ie wi h a bulk-inpu compa a o echnique is p oposed o ul a-low- ol age ene gy
ha es ing sys ems. Howe e , when he inpu ol age is highe han he ou pu ol age,
he PN junc ions be ween he bulk and sou ce e minal o he inpu ansis o will be
u ned on. Consequen ly, he e e se leakage cu en will low om he ca hode e minal
o he anode e minal h ough he body PN junc ions, which comp omises he e iciency
o he ci cui [
8
]. In addi ion, he p oposed ec i ie in [
19
] has a equency ange no
sui able o he applica ion o his esea ch wo k. In con as , in he ollowing esea ch
pape s [
8
,
9
,
20
,
21
], he equency bandwid h co esponds o he desi ed applica ion. The
au ho s use wo ac i e diodes o con ol he e e se cu en ha lows h ough he wo
NMOS in each inpu cycle, and wo PMOS in c oss-coupled o p o ide he conduc ion
pa h. Howe e , he dynamic ange does no mee he equi emen s o achie e a high PCE
o inpu ol ages lowe han 1 V, which is c i ical o ene gy ha es ing applica ions [
8
].
Senso s 2021,21, 6883 3 o 13
In [
20
], he au ho s designed a ully ac i e con igu a ion using PMOS and NMOS o ensu e
ha he e e se cu en h ough he PMOS inpu sou ce is ze o. The main disad an age
o his con igu a ion occu s when he wo NMOS de ices u n on simul aneously, which
leads o powe losses. Chang e al. [
21
] p oposed a ec i ie wi h a hi d compa a o o
elimina e he oscilla ions o NMOS, which a oids he wo ac i e diodes u ning on/o
simul aneously. Ne e heless, he PCE is only high o an inpu ol age a ound 4.88 V.
Howe e , he main limi a ions o hese con igu a ions a e ha hey canno con ol
he
VG
o he main ansis o o inc ease
VSG
du ing he conduc ion phase. Thus, i is no
possible o educe he in e nal esis ance o his ansis o , which limi s he ou pu powe
o he ec i ie . The e o e, an ex a ci cui is needed o educe he h eshold ol age e ec o
his ansis o o o e come hese d awbacks.
2.3. Th eshold Cancella ion Topologies
Se e al h eshold cancella ion opologies we e p oposed o enhance he ou pu s o ed
ol age by dynamically educing he h eshold ol age e ec o he main ansis o o he
ec i ie [
22
–
25
]. The h eshold ol age is a p ocess pa ame e dependen on he oxide
ype and hickness [
24
]. Low h eshold ol age MOSFETs p esen a high leakage cu en
caused by he low subs a e doping, which leads o an inc ease in powe consump ion
and eliabili y p oblems [
24
,
26
]. Thus, hese h eshold cancella ion echniques a e used o
a oid hose ypes o MOSFETs since i is only needed o educe he h eshold ol age e ec
when he main pass ansis o is ON. In [
25
], a low- ol age CMOS ec i ie is p oposed o
pe o m his echnique by using he boo s ap echnique, which has enhanced he ou pu
ol age s o ed in he load capaci o . Howe e , o he minimum ope a ing ol age o his
con igu a ion (0.8 V), he PCE o his ci cui is a ound 30%, which is no enough o he
equi emen s o his applica ion.
An ac i e boo s apping ec i ie is p esen ed in [
27
] o o e come he issues o he
p e ious wo k. This opology uses wo ac i e diodes o con ol he conduc ion pa h o
each inpu cycle and a boo s ap echnique o educe he h eshold ol age o bo h main
pass PMOS. Addi ionally, an adap i e ol age con e e is se in his wo k o adjus he
ga e ol age o he main pass PMOS, which educes he ol age d op by educing he
on- esis ance. Besides lowe ing he e e se leakage cu en , he PCE o his con igu a ion
can s ill be imp o ed o inpu ol ages smalle han 1 V. To o e come he low PCE alues
o a na ow inpu ol age ange, in [
28
], a dual swi ching echnique eplaced he wo
ac i e diodes. This app oach can main ain a cons an ga e bias on he wo main NMOS
ansis o s, a oid he e e se leakage cu en , educe he a ea on-chip, and enhance he
PCE o low ol age applica ions. Howe e , high alues o PCE can only be ob ained o
inpu equencies a ound 20 kHz, which makes he equency bandwid h na ow.
3. Design Implemen a ion
Rega ding he inhe en ou pu cha ac e is ics o he piezoelec ic ansduce , he
p oposed CMOS ec i ie was mainly designed o achie e a high PCE o wide low inpu
ol age and equency condi ions. The e o e, he ope a ional ol age anges om 0.4 V
o 1 V, and he wo king equency a ies om hund eds o Hz o a ew kHz. In addi ion,
he ou pu impedance o he ene gy ha es e is no conside ed in his design because
he ma ching impedance p ocess is pe o med be o e his ec i ica ion s age in he PMC.
Thus, he main goal o his wo k is o educe he ol age d op ac oss he s uc u e by
applying a h eshold cancella ion echnique ha will u he enhance he powe con e ed
o he ohmic load. These imp o emen s will o e come he d awbacks o p e ious wo k
by mi iga ing he e e se leakage cu en , and hus enhancing he PCE o a low inpu
ol age ange.
Figu e 1shows he simpli ied schema ic o he p oposed ac i e ec i ie . I consis s
o an NVC and an ac i e diode biased by a h eshold cancella ion ci cui . The i s s age
is se o pe o m he signal ull-wa e ec i ica ion. Howe e , because his passi e s age
canno con ol he e e se cu en om he load capaci o when he ou pu ol age is highe
Senso s 2021,21, 6883 4 o 13
han he inpu , a second s age ac i e diode (M5) is needed. This ac i e s age is composed
o a PMOS con olled by a h eshold cancella ion ci cui wi h a boo s apping capaci o
o educe he e ec i e h eshold o he ac i e diode, and an adap i e ol age con olle
(AVC) o adjus he ga e ol age o M5 by con olling he cha ging/discha ging cycle o
he boo s apping capaci o . To pe o m i , a wo-inpu common ga e compa a o and an
NMOS ansis o a e used. Besides hese s ages, a dynamic swi ching bulk (DSB) echnique
was used o con ol he bulk ol age o he ac i e diode PMOS.
Senso s 2021, 21, x FOR PEER REVIEW 4 o 14
Figu e 1 shows he simpli ied schema ic o he p oposed ac i e ec i ie . I consis s o
an NVC and an ac i e diode biased by a h eshold cancella ion ci cui . The i s s age is
se o pe o m he signal ull-wa e ec i ica ion. Howe e , because his passi e s age can-
no con ol he e e se cu en om he load capaci o when he ou pu ol age is highe
han he inpu , a second s age ac i e diode (M5) is needed. This ac i e s age is composed
o a PMOS con olled by a h eshold cancella ion ci cui wi h a boo s apping capaci o o
educe he e ec i e h eshold o he ac i e diode, and an adap i e ol age con olle
(AVC) o adjus he ga e ol age o M5 by con olling he cha ging/discha ging cycle o
he boo s apping capaci o . To pe o m i , a wo-inpu common ga e compa a o and an
NMOS ansis o a e used. Besides hese s ages, a dynamic swi ching bulk (DSB) ech-
nique was used o con ol he bulk ol age o he ac i e diode PMOS.
Figu e 1. Schema ic o he p oposed ac i e ec i ie composed by a NVC and an ac i e diode con olled by a h eshold
cancella ion ci cui .
3.1. Nega i e Vol age Con e e
The i s s age is ully passi e, and i is used o pe o m he signal ull-wa e ec i i-
ca ion by applying a ully-c oss coupled con igu a ion. Du ing he posi i e hal pe iod o
he inpu signal (𝑉 > 𝑉
), M1 and M3 will be conduc i e as soon as he inpu ol age
ge s la ge han 𝑉 and |𝑉|. In his cycle, node 1 is connec ed o 𝑉 and node 2 o
𝑉. Fo he nega i e pe iod o he sine wa e, M2 and M4 a e conduc ing while he p e-
ious wo ansis o s a e now u ned o (cu -o egion). The e o e, he highe ol age
po en ial is always a 𝑉
, whe eas he lowes po en ial is a 0 V. The ol age d op o he
NVC is gi en by 𝑉 + 𝑉
 in each conduc ion pa h, whe e 𝑉 and 𝑉 a e he ol -
age d op o NMOS ansis o s M2 o M3 and PMOS ansis o s M1 o M4, espec i ely.
To mee all he powe es ic ions ela ed o he piezoelec ic ene gy ha es ing sys-
ems, he ec i ie ci cui mus minimize he ol age d op ac oss he ec i ica ion p ocess.
As less ol age d op occu s, bo h he VCE and he PCE o he ci cui will be highe . Fo
his s age, NVC, he main equi emen is o dec ease he ol age d op associa ed wi h each
MOSFET by educing hei on- esis ance.
3.2. Ac i e Diode
One o he main challenges on he ec i ie ci cui is o a oid he e e se leakage cu -
en by con olling he ope a ion o ansis o M5. The e o e, an ac i e diode con olled
wi h a h eshold cancella ion ci cui can egula e he wo k beha io o his de ice
Figu e 1.
Schema ic o he p oposed ac i e ec i ie composed by a NVC and an ac i e diode con olled by a h eshold
cancella ion ci cui .
3.1. Nega i e Vol age Con e e
The i s s age is ully passi e, and i is used o pe o m he signal ull-wa e ec i ica-
ion by applying a ully-c oss coupled con igu a ion. Du ing he posi i e hal pe iod o he
inpu signal (
Vin+>Vin−
), M1 and M3 will be conduc i e as soon as he inpu ol age ge s
la ge han
VTHn
and

VTHp

. In his cycle, node 1 is connec ed o
Vin+
and node 2 o
Vin−
.
Fo he nega i e pe iod o he sine wa e, M2 and M4 a e conduc ing while he p e ious
wo ansis o s a e now u ned o (cu -o egion). The e o e, he highe ol age po en ial
is always a
Vn c
, whe eas he lowes po en ial is a 0 V. The ol age d op o he NVC is
gi en by
VDSn +VSDp
in each conduc ion pa h, whe e
VDSn
and
VSDp
a e he ol age d op
o NMOS ansis o s M2 o M3 and PMOS ansis o s M1 o M4, espec i ely.
To mee all he powe es ic ions ela ed o he piezoelec ic ene gy ha es ing sys-
ems, he ec i ie ci cui mus minimize he ol age d op ac oss he ec i ica ion p ocess.
As less ol age d op occu s, bo h he VCE and he PCE o he ci cui will be highe . Fo
his s age, NVC, he main equi emen is o dec ease he ol age d op associa ed wi h each
MOSFET by educing hei on- esis ance.
3.2. Ac i e Diode
One o he main challenges on he ec i ie ci cui is o a oid he e e se leakage cu en
by con olling he ope a ion o ansis o M5. The e o e, an ac i e diode con olled wi h a
h eshold cancella ion ci cui can egula e he wo k beha io o his de ice depending on
he ol age po en ial be ween he inpu and ou pu . The deployed h eshold cancella ion
ci cui con ols he ga e po en ial o he MOSFET M5 by compa ing he inpu /ou pu
ol age condi ions. Addi ionally, he wid h o M5 has a la ge in luence on he pe o mance
o his ec i ie because he ol age d op is mainly a ec ed by his pa ame e due o he
Senso s 2021,21, 6883 5 o 13
in e nal on- esis ance. Consequen ly, since he ga e capaci ance o M5 depends on he
wid h, he u n on/o ime o he ansis o will also be a ec ed by his pa ame e . In
addi ion, he DSB echnique, composed o M6 and M8, is deployed o educe he leakage
cu en h ough he bulk e minal o M5 by connec ing i o he highe po en ial (
Vn c
o
V ec
). Ano he ad an age o his echnique is elimina ing he body e ec o M5, which
educes he ec i ie ol age d op. Bo h M6 and M8 can be small in size since only a e y
low cu en lows h ough hem du ing he s a -up phase.
To assu e a sa e s a -up o M5, a bypass PMOS diode (M10) was connec ed in pa allel.
This ansis o makes he ac i e diode mo e obus by p e en ing i om leakage cu en in
he sub ac ion ha induces la ch-up. A e he s a -up phase, he bypass diode always
ope a es in he cu -o egion.
3.3. Th eshold Cancella ion Ci cui
In o de o educe he h eshold ol age e ec on M5, a boo s ap echnique is used
by a aching he capaci o
C1
o he ou pu e minal. When he
VNVC
is highe han he
ou pu ol age
V ec
, M5 is u ned ON, since
VSG5
is no longe lowe han
VTH5
, and hus
i can be de ined in (1). Ne e heless, because M5 is ope a ing in he deep- iode egion
due o
VSD5
2
·(VSG5−|VTH5|)
,
VSG5
can also be de ined acco ding o he on- esis ance
equa ion, see (2).
VSG5=VNVC −VCAP (1)
VSG5=1
µp·Cox·W5/L5·RSD5
+|VTH5|(2)
He e,
µp
is he ca ie mobili y,
Cox
is he oxide capaci ance,
W5/L5
is he aspec a io
o ansis o M5, and VTH5is i s espec i e h eshold ol age.
The boo s apping capaci o (
C1
) is cha ged up h ough an auxilia y diode-connec ed
PMOS ansis o M7, and i main ains a alue when he ec i ie is unde he s eady-s a e
egime. A his ime, because
C1
is discha ging,
VCAP
is one diode o wa d-bias ol age
(
VTH7
) bellow
V ec
due o M7 is being in he sa u a ion egion. Thus, he ol age held on
he boo s apping capaci o can be de ined as:
VCAP =V ec −|VTH7|(3)
VSG5
and
VCAP
om (2) and (3), espec i ely, can be eplaced in (1), which means ha
V ec can now be de ined acco ding o he ollowing equa ion:
V ec =VNVC −(|VTH5|−|VTH7|)−1
µp·Cox·W5/L5·RSD5
(4)
Acco ding o (4), he ec i ied signal is highly in luenced by he size o M5 and he
h eshold ol age o bo h M5 and M7, and hus i is i al o manage hese pa ame e s o
enhance he ou pu signal ol age. The implemen ed h eshold cancella ion ci cui educes
he ol age d op o he main pass ansis o M5 by lowe ing he h eshold ol age e ec .
Addi ionally, he size o he boo s ap capaci o is an impo an design conce n o he
implemen a ion o he p oposed ec i ie . In eg a ed capaci o s consume a la ge a ea on he
chip when s anda d CMOS p ocesses a e used [
24
]. The e o e,
C1
was se a 200 F no only
o educe he co esponden a ea on he die bu also o ha e a as e cha ging/discha ging
ime. Consequen ly, his low boo s ap capaci ance allows a lowe ga e ol age o M5 a he
ON s a e. Due o he educ ion o i s in e nal sou ce o d ain esis ance, he ol age d op is
dec eased. The e e se leakage cu en du ing he OFF s a e will be a oided because
VSG5
is educed. Mo eo e , i is necessa y o ha e an auxilia y ci cui o hold he
VCAP
node
when M5 is OFF, and o discha ge i a he opposi e s a e.
The boo s apping capaci o is used o educe he h eshold ol age e ec o M5.
Howe e , an inc ease in i s on- esis ance can be no iced due o he educ ion o
VSG5
. Thus,
a conduc ion pa h needs o be gene a ed o discha ge he ga e o M5 du ing he ON s a e,

Senso s 2021,21, 6883 6 o 13
which will lead o a u he inc ease o
VSG5
. The p oposed AVC is composed o NMOS M9
and a compa a o CMP ha d i es i s ga e. When
VNVC
is highe han he ou pu ol age
V ec
, he compa a o CMP should immedia ely u n on M9 o p o ide a discha ge pa h
o he
VCAP
node. Consequen ly, i will u n on he main pass ansis o M5 wi h a low
on- esis ance. Because he la ge size o M5 inc eases he ga e capaci ance, he AVC mus
ha e a as e bias signal con ol o swi ch he discha ge pa h o he ga e node (
VCAP
). Thus,
he compa a o mus be designed o a end o hese demands.
Figu e 2shows he p oposed wo-inpu common ga e compa a o . This compa a o
is composed o a cu en mi o s age o make he compa ison, plus an in e e block
o bias he ga e o M9. E en i he ansis o o he cu en mi o should be as small
as possible o educe he cu en consump ion o he compa a o , he size o M12 and
M15 mus be ca e ully chosen o manage he delay, and consequen ly, he e e se leakage
cu en in M5. These wo ansis o s canno ha e he same W/L a io as M11 and M14.
O he wise, his would gene a e a delay caused by he in e e ’s ga e capaci ance’s low
cha ging/discha ging ime. Addi ionally, hey canno be much la ge han he o he
ansis o s because o he educed ime ha M5 would be ON, which would lead o a
PCE educ ion. The e o e, M12 and M15 only need o be sligh ly highe o p o ide he
equi ed cha ging/discha ging ime o educe he delay o he o e all compa a o . Table 1
summa izes he dimension alues o he p oposed ec i ie ci cui .
Senso s 2021, 21, x FOR PEER REVIEW 6 o 14
a oided because 𝑉 is educed. Mo eo e , i is necessa y o ha e an auxilia y ci cui o
hold he 𝑉 node when M5 is OFF, and o discha ge i a he opposi e s a e.
The boo s apping capaci o is used o educe he h eshold ol age e ec o M5.
Howe e , an inc ease in i s on- esis ance can be no iced due o he educ ion o 𝑉. Thus,
a conduc ion pa h needs o be gene a ed o discha ge he ga e o M5 du ing he ON s a e,
which will lead o a u he inc ease o 𝑉. The p oposed AVC is composed o NMOS
M9 and a compa a o CMP ha d i es i s ga e. When 𝑉 is highe han he ou pu ol -
age 𝑉
, he compa a o CMP should immedia ely u n on M9 o p o ide a discha ge
pa h o he 𝑉 node. Consequen ly, i will u n on he main pass ansis o M5 wi h a
low on- esis ance. Because he la ge size o M5 inc eases he ga e capaci ance, he AVC
mus ha e a as e bias signal con ol o swi ch he discha ge pa h o he ga e node (𝑉).
Thus, he compa a o mus be designed o a end o hese demands.
Figu e 2 shows he p oposed wo-inpu common ga e compa a o . This compa a o
is composed o a cu en mi o s age o make he compa ison, plus an in e e block o
bias he ga e o M9. E en i he ansis o o he cu en mi o should be as small as pos-
sible o educe he cu en consump ion o he compa a o , he size o M12 and M15 mus
be ca e ully chosen o manage he delay, and consequen ly, he e e se leakage cu en in
M5. These wo ansis o s canno ha e he same W/L a io as M11 and M14. O he wise,
his would gene a e a delay caused by he in e e ’s ga e capaci ance’s low cha ging/dis-
cha ging ime. Addi ionally, hey canno be much la ge han he o he ansis o s because
o he educed ime ha M5 would be ON, which would lead o a PCE educ ion. The e-
o e, M12 and M15 only need o be sligh ly highe o p o ide he equi ed cha ging/dis-
cha ging ime o educe he delay o he o e all compa a o . Table 1 summa izes he di-
mension alues o he p oposed ec i ie ci cui .
Figu e 2. Schema ic o he wo-inpu common ga e compa a o CMP.
Table 1. Ci cui ansis o sizes.
Uni Size (µm/µm) Mul iply Fac o
M1/2/3/4 100/0.13 100
M5 100/0.13 50
M6/7/10/11/13/14/16 0.28/0.13 1
M7/9 20/0.13 1
M11/12 0.34/0.13 1
Figu e 2. Schema ic o he wo-inpu common ga e compa a o CMP.
Table 1. Ci cui ansis o sizes.
Uni Size (µm/µm) Mul iply Fac o
M1/2/3/4 100/0.13 100
M5 100/0.13 50
M6/7/10/11/13/14/16 0.28/0.13 1
M7/9 20/0.13 1
M11/12 0.34/0.13 1
4. Resul s and Discussion
The simula ion expe imen s we e ca ied ou using Cadence Vi uoso Analog Design
En i onmen wi h a 130 nm CMOS p ocess. The espec i e physical layou o he CMOS
ec i ie is p esen ed in Figu e 3. To eplica e he ou pu beha io o he ene gy ha es e ,
he de aul inpu sinusoidal ol age ampli ude and equency used in he simula ions
we e 600 mV and 3.2 kHz, espec i ely. Th oughou mos o he es s,
CLOAD
and
RLOAD
Senso s 2021,21, 6883 7 o 13
we e se a 2
µ
F and 5.5 k
Ω
o simula e he capaci ance o he s o ing capaci o and he
impedance o he elec onics o be powe ed, espec i ely.
Senso s 2021, 21, x FOR PEER REVIEW 7 o 14
4. Resul s and Discussion
The simula ion expe imen s we e ca ied ou using Cadence Vi uoso Analog Design
En i onmen wi h a 130 nm CMOS p ocess. The espec i e physical layou o he CMOS
ec i ie is p esen ed in Figu e 3. To eplica e he ou pu beha io o he ene gy ha es e ,
he de aul inpu sinusoidal ol age ampli ude and equency used in he simula ions
we e 600 mV and 3.2 kHz, espec i ely. Th oughou mos o he es s, 𝐶 and 𝑅
we e se a 2 µF and 5.5 kΩ o simula e he capaci ance o he s o ing capaci o and he
impedance o he elec onics o be powe ed, espec i ely.
Figu e 3. Physical layou o he p oposed CMOS ec i ie .
4.1. T ansien Beha io
The ansien pe o mance o he ou pu ol age, in bo h s ages, is displayed in Figu e
4. The i s s age pe o ms he ull-wa e ec i ica ion by con e ing he nega i e inpu
ol ages (𝑉) in o posi i e ones (𝑉). The ol age d op on his s age is a ound 1 mV,
whe eas he o al ol age d op on he ci cui is a ound 12 mV, which is possible due o
he educ ion o he in e nal esis ance o he main pass ansis o M5. The achie ed ol -
age d op is c ucial o enhance he ou pu ol age ac oss he load.
Figu e 4. Simula ed wa e o ms o he ec i ie o R =5.5 kΩ and C =2 µF.
Figu e 3. Physical layou o he p oposed CMOS ec i ie .
4.1. T ansien Beha io
The ansien pe o mance o he ou pu ol age, in bo h s ages, is displayed in
Figu e 4
. The i s s age pe o ms he ull-wa e ec i ica ion by con e ing he nega i e
inpu ol ages (
VIN
) in o posi i e ones (
VNVC
). The ol age d op on his s age is a ound
1 mV, whe eas he o al ol age d op on he ci cui is a ound 12 mV, which is possible due
o he educ ion o he in e nal esis ance o he main pass ansis o M5. The achie ed
ol age d op is c ucial o enhance he ou pu ol age ac oss he load.
Senso s 2021, 21, x FOR PEER REVIEW 7 o 14
4. Resul s and Discussion
The simula ion expe imen s we e ca ied ou using Cadence Vi uoso Analog Design
En i onmen wi h a 130 nm CMOS p ocess. The espec i e physical layou o he CMOS
ec i ie is p esen ed in Figu e 3. To eplica e he ou pu beha io o he ene gy ha es e ,
he de aul inpu sinusoidal ol age ampli ude and equency used in he simula ions
we e 600 mV and 3.2 kHz, espec i ely. Th oughou mos o he es s, 𝐶 and 𝑅
we e se a 2 µF and 5.5 kΩ o simula e he capaci ance o he s o ing capaci o and he
impedance o he elec onics o be powe ed, espec i ely.
Figu e 3. Physical layou o he p oposed CMOS ec i ie .
4.1. T ansien Beha io
The ansien pe o mance o he ou pu ol age, in bo h s ages, is displayed in Figu e
4. The i s s age pe o ms he ull-wa e ec i ica ion by con e ing he nega i e inpu
ol ages (𝑉) in o posi i e ones (𝑉). The ol age d op on his s age is a ound 1 mV,
whe eas he o al ol age d op on he ci cui is a ound 12 mV, which is possible due o
he educ ion o he in e nal esis ance o he main pass ansis o M5. The achie ed ol -
age d op is c ucial o enhance he ou pu ol age ac oss he load.
Figu e 4. Simula ed wa e o ms o he ec i ie o R =5.5 kΩ and C =2 µF.
Figu e 4. Simula ed wa e o ms o he ec i ie o RLOAD =5.5 kΩand CLOAD =2µF.
Figu e 5shows he VCE beha io e sus he inpu ol age ampli ude o di e en
RLOAD
alues. I is possible o obse e ha he p oposed ec i ie can wo k e icien ly o
an inpu ol age ange om 0.45 V o 1 V o di e en ohmic loads, wi h a VCE a ying
be ween 96% and 99%. Fo an inpu ol age lowe han 0.4 V, he VCE sha ply dec eases
because he NVC ansis o s will en e he sub h eshold egion o e en cu -o . Mo eo e , i
can be no iced ha he ec i ie VCE is highe o la ge load esis o s, as would be expec ed.
Senso s 2021,21, 6883 8 o 13
Senso s 2021, 21, x FOR PEER REVIEW 8 o 14
Figu e 5 shows he VCE beha io e sus he inpu ol age ampli ude o di e en
𝑅 alues. I is possible o obse e ha he p oposed ec i ie can wo k e icien ly o
an inpu ol age ange om 0.45 V o 1 V o di e en ohmic loads, wi h a VCE a ying
be ween 96% and 99%. Fo an inpu ol age lowe han 0.4 V, he VCE sha ply dec eases
because he NVC ansis o s will en e he sub h eshold egion o e en cu -o . Mo eo e ,
i can be no iced ha he ec i ie VCE is highe o la ge load esis o s, as would be ex-
pec ed.
Figu e 5. VCE e sus inpu ol age ampli ude simula ed o di e en ohmic loads.
4.2. Re e se Leakage Cu en Analysis
The e e se leakage cu en analysis is one o he mos impo an analyses o make
in CMOS ec i ie s because i a ec s he powe e iciency o he o e all sys em. This e-
e se leakage cu en is dependen on he delay o he compa a o and, consequen ly, o
he discha ging pa h o he ac i e diode p o ided by he AVC. The e o e, he analysis o
he ansien pe o mance o he compa a o is shown in Figu e 6. I p esen s he ou pu
ol age o he compa a o (𝑉), he inpu and ou pu ol age o he ac i e diode used o
pe o m he compa ison, he ga e ol age o M5 (𝑉), and he cu en ha lows h ough
he ac i e diode (𝐼). As can be obse ed, he compa a o immedia ely u ns on he ga e
o he AVC ansis o o c ea e he discha ge pa h when 𝑉 exceeds 𝑉
. A his s age,
he cu en is lowing h ough M5, and 𝑉 is low, which leads o a low ol age d op
because 𝑉 is high. When 𝑉 d ops below 𝑉
, he compa a o hen quickly u ns o
he AVC, and consequen ly he ac i e diode. Thus, he p oposed s uc u e does no exhibi
e e se leakage cu en ha would deg ade he PCE o he p oposed ec i ie .
Figu e 5. VCE e sus inpu ol age ampli ude simula ed o di e en ohmic loads.
4.2. Re e se Leakage Cu en Analysis
The e e se leakage cu en analysis is one o he mos impo an analyses o make in
CMOS ec i ie s because i a ec s he powe e iciency o he o e all sys em. This e e se
leakage cu en is dependen on he delay o he compa a o and, consequen ly, o he
discha ging pa h o he ac i e diode p o ided by he AVC. The e o e, he analysis o he
ansien pe o mance o he compa a o is shown in Figu e 6. I p esen s he ou pu
ol age o he compa a o (
VCMP
), he inpu and ou pu ol age o he ac i e diode used o
pe o m he compa ison, he ga e ol age o M5 (
VCAP
), and he cu en ha lows h ough
he ac i e diode (
IM5
). As can be obse ed, he compa a o immedia ely u ns on he ga e
o he AVC ansis o o c ea e he discha ge pa h when
VNVC
exceeds
V ec
. A his s age,
he cu en is lowing h ough M5, and
VCAP
is low, which leads o a low ol age d op
because
VSG
is high. When
VNVC
d ops below
V ec
, he compa a o hen quickly u ns o
he AVC, and consequen ly he ac i e diode. Thus, he p oposed s uc u e does no exhibi
e e se leakage cu en ha would deg ade he PCE o he p oposed ec i ie .
Senso s 2021, 21, x FOR PEER REVIEW 9 o 14
Figu e 6. Simula ed compa a o beha io in s eady s a e o R = 500 Ω and C =2 µF.
4.3. Powe E iciency
The simula ed powe e iciency e sus inpu ol age ampli ude o di e en load e-
sis o s is p esen ed in Figu e 7. The de ini ion o PCE is shown in (5):
𝑃𝐶𝐸 = 𝑉(𝑡)∙𝐼
(𝑡)𝑑𝑡
  

𝑉(𝑡)∙𝐼
(𝑡)𝑑𝑡
  

∙ 100% (5)
Figu e 7. PCE e sus inpu ol age ampli ude simula ed o di e en alues o R.
The maximum PCE alue o 94% can be ound a 0.6 V o a R o 500 Ω. When
𝑉 is lowe han his ange, he PCE sha ply dec eases due o he low ol age e iciency,
as no ed in Sec ion 4.1. Thus, he e iciency o he ec i ie is poo in he ul a-low ol age
ange. Addi ionally, he PCE ends o dec ease o highe inpu ol ages because he
powe losses a e mainly concen a ed in he compa a o . Howe e , his case is no signi -
ican o ohmic loads lowe han 15.5 kΩ. Mo eo e , o highe load esis o s, he PCE
ends o dec ease due o he educ ion o he ou pu cu en , whe eas he bias cu en ha
comes om he ol age sou ce keeps almos cons an . Rega dless, om 0.45 V o 1 V, he
Figu e 6. Simula ed compa a o beha io in s eady s a e o RLOAD =500 Ωand CLOAD =2µF.
Senso s 2021,21, 6883 9 o 13
4.3. Powe E iciency
The simula ed powe e iciency e sus inpu ol age ampli ude o di e en load
esis o s is p esen ed in Figu e 7. The de ini ion o PCE is shown in (5):
PCE =R +T
VOUT( )·IOUT( )d
R +T
VIN( )·IIN( )d ·100%. (5)
Senso s 2021, 21, x FOR PEER REVIEW 9 o 14
Figu e 6. Simula ed compa a o beha io in s eady s a e o R = 500 Ω and C =2 µF.
4.3. Powe E iciency
The simula ed powe e iciency e sus inpu ol age ampli ude o di e en load e-
sis o s is p esen ed in Figu e 7. The de ini ion o PCE is shown in (5):
𝑃𝐶𝐸 = 𝑉(𝑡)∙𝐼
(𝑡)𝑑𝑡
  

𝑉(𝑡)∙𝐼
(𝑡)𝑑𝑡
  

∙ 100% (5)
Figu e 7. PCE e sus inpu ol age ampli ude simula ed o di e en alues o R.
The maximum PCE alue o 94% can be ound a 0.6 V o a R o 500 Ω. When
𝑉 is lowe han his ange, he PCE sha ply dec eases due o he low ol age e iciency,
as no ed in Sec ion 4.1. Thus, he e iciency o he ec i ie is poo in he ul a-low ol age
ange. Addi ionally, he PCE ends o dec ease o highe inpu ol ages because he
powe losses a e mainly concen a ed in he compa a o . Howe e , his case is no signi -
ican o ohmic loads lowe han 15.5 kΩ. Mo eo e , o highe load esis o s, he PCE
ends o dec ease due o he educ ion o he ou pu cu en , whe eas he bias cu en ha
comes om he ol age sou ce keeps almos cons an . Rega dless, om 0.45 V o 1 V, he
Figu e 7. PCE e sus inpu ol age ampli ude simula ed o di e en alues o RLOAD
The maximum PCE alue o 94% can be ound a 0.6 V o a
RLOAD
o 500
Ω
. When
Vin
is lowe han his ange, he PCE sha ply dec eases due o he low ol age e iciency,
as no ed in Sec ion 4.1. Thus, he e iciency o he ec i ie is poo in he ul a-low ol age
ange. Addi ionally, he PCE ends o dec ease o highe inpu ol ages because he powe
losses a e mainly concen a ed in he compa a o . Howe e , his case is no signi ican
o ohmic loads lowe han 15.5 k
Ω
. Mo eo e , o highe load esis o s, he PCE ends o
dec ease due o he educ ion o he ou pu cu en , whe eas he bias cu en ha comes
om he ol age sou ce keeps almos cons an . Rega dless, om 0.45 V o 1 V, he powe
e iciency o low ohmic loads is conside ed as being good o his applica ion. Addi ionally,
he in luence o he wid h o he NVC s age (M1–M4) and o M5 in bo h PCE and VCE can
be obse ed in Figu e 8. Fo his simula ion es , he wid h o each s age was indi idually
a ied while he o he was kep cons an . This igu e shows ha he VCE and PCE ea u es
o bo h s ages a e a hei maximum poin o a wid h o 100
µ
m because he on- esis ance
o his ansis o is di ec ly in luenced by he
W/L
a io o he MOSFET. E en i he ga e
capaci ance o M5 inc eases wi h he size, Figu e 6shows ha he h eshold cancella ion
ci cui can d i e his la ge ansis o .
Figu e 9shows he powe e iciency e sus inpu ol age ampli ude o di e en
inpu equencies. The load capaci o alue was adap ed o keep he ou pu ipple ol age
small depending on he inpu equency. I is possible o obse e ha he p oposed
ec i ie can achie e a high-powe e iciency o low inpu equencies in he ope a ing
ol age ange. Howe e , when he inpu ol age and equency a e high, he powe
e iciency ends o sligh ly dec ease due o he powe losses in he NVC and in he ac i e
diode, which in his case i is caused by he ou pu signal o he compa a o being oo
as . Consequen ly, he wo king ime o ansis o M5 will be oo sho , which educes
he amoun o powe con e ed o he load. None heless, a ypical ene gy ha es ing
equencies, he pe o mance o he CMOS ec i ie o he p esen ed equency ange is
sui able o his applica ion.