Digital Space Vector Approach to Eliminate Overcharging of DC-link Capacitor in Asymmetrical VSI Fed Open End Winding Induction Motor Drive

REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER Research Article Digital Space Vector Approach to Eliminate Overcharging of DC-link Capacitor in Asymmetrical VSI Fed Open End Winding Induction Motor Drive M. Harshavardhan REDDY1, K. Sri GOWRI1, G. KISHOR1,∗, T. Bramhananda REDDY 1 1EEE Department, G.Pulla Reddy Engineering College (Autonomous), Kurnool [email protected],gowriv[email protected],[email protected],[email protected] ∗Corresponding author: G. KISHOR; [email protected] DOI: 10.15598/aeee.v22i3.5259 Article history: Received Jun 02, 2023; Revised Mar 19, 2024; Accepted Jul 01, 2024; Published Sep 30, 2024. This is an open access article under the BY-CC license. Abstract. Dual inverter topology with asymmetrical input voltage (2:1) is the simple and most economical solution to fabricate four-level output voltage. Due to the lack of switching status selections, the asymmetric configuration of the dual inverter suffers from overload of the DC link capacitor. The present work compares few exiting decoupled and coupled PWM techniques with implementation using multilevel carrier comparison approach and digital space vector approach. It is proved that proposed coupled PWM with the digital space vector approach provide easy path for switching state selection to eliminate the problem “overcharging of DC link capacitor”. The other decoupled PWM techniques may eliminate the problem, but generate poor quality of output voltage. In addition, the proposed digital space vector approach provides freedom in the choice of different voltage vectors to achieve good output voltage quality. Keywords Carrier comparison approach,Coupled PWM, Decopuled PWM, Digital space vector apparoach. 1. Introduction Medium to high power drives are employed with VSI fed induction motors. PWM techniques are used for voltage and output frequency monitoring [1–3]. The current trend is to use multilevel inverters (MLI) in the blank space of conventional two-level VSI [4–7] to improve the quality of output potential and reduced common mode voltage (CMV). But the conventional topologies of multi-level inverters suffer from major disadvantages such as the problems of balancing capacitors [5] and high power capacitors are necessary to support the charge current. Among the various configurations of multi-level inverters for induction motor drives, open-winding induction motor drives powered by two inverters are increasing in importance [6]. Established along the provision of input DC voltage dual inverter fed open end winding IM drives are classified as symmetrical (1:1 voltage ratio) [7] and asymmetrical (2:1 voltage ratio) dual inverter configurations [8, 9]. Based on the switching scheme used in PWM techniques [10], the asymmetric configuration of the dual inverter (4 levels) generates a higher number of voltage levels relative to the symmetrical configuration of the dual inverter (3 levels). Equally the same circuit configuration is capable of generating higher number of levels, in this article focus is applied to asymmetrical dual inverter configuration. From the survey it is observed that PWM techniques can be carried out based on carrier compari- ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 202 REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER son approach and digital space vector approach [1–3]. In a carrier comparison approach, modulation signals are compared with high-frequency carrier signals for generating control signals. These two-level modulating signals can be generated based on space vector approach [2] and scalar approach [1, 3]. In the digital space vector approach, the instantaneous reference voltage space vector is synthesised by voltage vectors in an average direction by satisfying the volt-sec equilibrium condition. For two-level inverter both these PWM approaches give identical results [2] and many authors, co-related carrier comparison and digital space vector approaches. In carrier comparison approach for a multilevel inverter (N level inverter), modulating signals are compared to N-1 level shifting carrier signals [11]. In digital space vector approach for multilevel inverters, the actual reference vector shifts to nearest sub hexagon center and nearest voltage vectors are used to synthesize the new reference voltage vector by satisfying the volt second balance condition [11–13]. Two two-level inverters are arranged to form the multilevel inverter configuration (Dual inverter configuration). Hence, based on controlling of two-level inverters, control techniques are classified as coupled PWM techniques [14–16] and decoupled PWM techniques [17]. These PWM techniques may also be carried out using either a carrier comparison approach or a digital spatial vector approach. Based on the analysis of the literature [14–17], decoupled PWM techniques generate poor output voltage quality for asymmetric drives of open-end induction motors powered by dual inverters. On the other hand, coupled PWM techniques generate good output voltage quality, but have the DC-link capacitor overload issue [14, 15]. Overcharging of DC-link capacitor is treated as the grievous problem in the asymmetrical dual inverter fed open end winding induction motor drive because this contributes to limited range of functioning and hence limited speed control. In order to overcome the DC link capacitor overload problem, various circuit configurations [22] and different decoupled PWM techniques [23, 25–27] were discussed in the literature. All these methods lead to decrease the quality of output voltage and also require modified circuit configurations which may increase the cost and complexity of operation. In [24,27], a discontinuous PWM technique (implemented in accordance with the carrier comparison approach) was proposed to eliminate over-charging of the DC link capacitor. The downside of this approach is that the required switching states are not selectable. Hence scope of the PWM technique is limited to extend. As the existing PWM methods [17–29] are implemented using carrier comparison approach (using the concept of switching times), freedom in selecting appropriate voltage vectors in four level space vector plane is not possible. Therefore, in this article, a multilevel digital space vector approach is presented for the asymmetrical double inverter open-winding induction motor drive. A new method of implementation and analysis of multilevel digital space vector based coupled PWM techniques were presented. With inherent simplicity in implementation this digital space vector PWM technique can be extended to N-level inverter. Moreover the digital space vector approach is compared to other space vector based carrier comparison approaches. The proposed digital space vector approach offers the freedom to choose different switching states to eliminate the overcharging of the DC link capacitor with good output voltage quality. 2. Asymmetrical dual inverter fed open end winding induction motor drive The configuration of the dual inverters with asymmetrical input voltage connected to open winding induction motor is illustrated in Fig. 1. A Vdc effective input DC voltage is split in the ratio of 2:1 as 2Vdc/3 to inverter-I and Vdc/3 to inverter-II. When the switch is ON, it is represented with switching state 1 and similarly when the switch is OFF it is represented by Switching state 0. When top switches in inverter-I are turned ON (Switching state 1), inverter-I will generate a pole voltage of 2Vdc/3. When top switches in inverter-I are turned OFF (Switching state 0), inverterI will generate a pole voltage of 0. Similarly When top switches in inverter-II are turned ON (Switching state 1), inverter-II will generate a pole voltage of Vdc/3 else 0. Table1 shows the voltage of each inverter pole and the calculated effective voltage of the dual inverter with asymmetric configuration. Based on the effective pole voltage shown in Table 1, the voltage has four levels (-Vdc/3, 0, Vdc/3 and 2Vdc/3). As a result, the asymmetric configuration of the dual inverters is referred to as the four-level inverter configuration. 3. PWM Techniques for asymmetrical dual inverter The asymmetrical dual inverter fed open end winding induction motor drive is equipped with 2 two-level inverters as shown in Fig. 1. PWM techniques can be applied either by treating the two inverters as one unit or by treating the two inverters as a separate unit. On the basis of this PWM, the dual inverter-powered openwinding induction motor drive techniques are split into ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 203 REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER Fig. 1: Drive configuration of the asymmetrical dual inverter with open end winding induction motor. Tab. 1: Calculation of Phase A Efficient Pole Voltage in dual inverter with Asymmetrical Configuration. SwitchInverter SwitchInverter EffecSwitching -I ing -II tive ing state of Pole state of Pole pole state of S11 in Voltage S12 in Voltage Voltage 4-Level Inverter Inverter SV -I -II plane 0 0 1 Vdc/3 -Vdc/3 0 0 0 0 0 0 1 1 2Vdc/3 1 Vdc/3 Vdc/3 2 1 2Vdc/3 0 0 2Vdc/3 3 two categories as coupled and decoupled PWM techniques. 3.1. Decoupled PWM technique With a decoupled PWM technique each inverter is treated as a separate unit and command reference signals are independently generated for each two-level inverter by using two-level space vector concept [6] or carrier comparison approach. The space vector plane of teo-level inverter with switching state for inverter-I and inverter-II are shown in Fig. 2(a) and Fig. 2(b). Mathematical formulation of resulting space vector from individual two-level inverters with decoupled space vector PWM is given by (1). Both the methods generate the same pulse pattern. The implementation of the decoupled PWM technique using space vector based Fig. 2: Space vector plane of (a) Inverter-I (b) inverter-II Fig. 3: Space vector plane of a four-level inverter imaginary switching times is disused in [17–19]. Vref1∠α1=Va+Vbej2π/3+Vcej4π/3, Vref2∠α2=Va′+Vb′ej2π/3+Vc′ej4π/3, Vref ∠α=Vref1∠α1−Vref2∠α2.(1) where Vi=Vmcos(ωt −2(r−1)π/3),i=a, b, c, and r= 1,2,3,Vi′=Vmcos(ωt −2(r−1)π/3−π). Fig. 4: Realization of carrier comparison approach for control signal generation. To get maximum output voltage the reference signals or modulating signals for inverter-I (Va,Vb,Vc) and inverter-II (Va′,Vb′,Vc′) are considered with a phase shift of 1800 as in (1). In the equivalent space vector approach inverter-I will operate in the first sector and inverter-II will operate in fourth sector. The switching sequence for each inverter in various sectors is given in Table 2 [17]. ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 204 REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER Tab. 2: Switching sequence of 2-level space vector plane Sector Switching states 1 8127-7218 2 8327-7238 3 8347-7438 4 8547-7458 5 8567-7658 6 8167-7618 3.2. Coupled PWM technique In the coupled PWM technique, the two inverters are treated as one unit (from which the configuration becomes a multilevel inverter configuration). The command, control signals are generated utilizing a tiered digital space vector PWM approach or a tiered carrier comparison approach. The mathematical expression for four-level space vector of asymmetrical dual inverter is given by (2). The four-level space vector plane with switching states is given in Fig. 3. The correlation between switching states of four-level space vector plane with switching states of inverter-I and inverter-II is given in Table 1. The process of selection of switching sates is elaborately discussed in section 4. . Vref ∠α= (Va−Va′)+(Vb−Vb′)ej2π/3+ (Vc−Vc′)ej4π/3 Vref ∠α=S11 2Vdc 3−S21Vdc 3 +S132Vdc 3−S23Vdc 3ej2π/3 +S152Vdc 3−S25Vdc 3ej4π/3.(2) In the four-level space vector plance it is observed that, there is only one switching state for the voltage vectors in the outer most peripheries. For the remaining voltage vectors which are in the innermost periphery there are more than one switching states. The selection among multiple switching states for a single voltage vector yields different PWM techniques. With the selection of few switching states space vector and carrier comparison approaches may or may not give identical pulse pattern. To obtain equivalent pulse pattern in carrier comparison approach has to be realized with many complex calculations and iterations. Moreover, with the change in modulation index these calculations and iterations changes. Hence, much freedom in selecting optimal switching state with generalized and easier implementation approach is only possible with the multilevel digital space vector approach. This method can be easily extended to any N-level inverter configurations. The realization of multilevel carrier comparison approach is shown in Fig. 4. Where a two-level basic modulating signal is compared to (three) level shifting carrier signals. The switching logic for generating the control signals is indicated in Table 3 [20]. Tab. 3: Generation of switching logic Condition Switch Status Vr∗> Vt1,Vr∗> Vt2S11: OFF, S14: ON, and Vr∗> Vt3S21:ON, S24:OFF Vr∗> Vt1,Vr∗> Vt2S11: OFF, S14: ON, and Vr∗< Vt3S21:OFF, S24:ON Vr∗> Vt1,Vr∗< Vt2S11: ON, S14: OFF, and Vr∗< Vt3S21:ON, S24:OFF Vr∗< Vt1,Vr∗< Vt2S11: ON, S14: OFF, and Vr∗< Vt3S21:OFF, S24:ON 4. Implementation of coupled PWM techniques using digital space vector approach In this approach the control signals to both the inverters are synthesized treating asymmetrical dual inverters as a single unit. Once the switching states shown in Fig. 3 are synthesized, they are bifurcated using a simple logic given in Table 1. Four-level space plane consists of 64 switching states, each corresponding to different voltage vectors. The space plane may be divided into three regions based on the modulation index. Modulation index (Mi) for an N-level inverter is defined through (3). Where Vdcis the normalized DClink voltage of a four level inverter. The normalized Mi,Min becomes same as the magnitude of the reference vector, when normalized to 2 3Vdc.Vref takes a maximum value of 2 3Vdc cos 30o. The reference vector is assumed to be in the linear modulation range if Min lies in the range of 0 to 2.598. This modulation range, R is further divided into three regions, if 0< M ⩽0.866, R takes a value 2, if 0.866 < M ⩽1.732, R takes a value 3 and if 1.732 < M ⩽2.598, R takes a value 4. The value of R indirectly specifies the inverter level to synthesize reference voltage. For R=2 the switching states generating two-level output voltage pulse pattern is obtained. Similarly for R=3 and R=4, three-level and four-level pulse pattern is obtained. Mi=Vref 2 3Vdc .(n−1),(3a) Min =Vref .(n−1).(3b) In any digital space vector approach selection of switching states is achieved by spotting out the triangle in which the tip of Vref lies is to be identified. To constitute the Vref any of the switching states can be selected. But to reduce the ripple nearest switching states should be selected for synthesizing the reference ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 205 REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER vector. By clear examination at Fig. 3 it can be observed that the four-level space plane consists of 19 sub hexagons with six triangles per sub hexagon. One such sub hexagon with blue color boundary is indicated in Fig. 3. To find the triangle in which tip of reference vector lies, it is very much essential to identify the sub hexagon in which Vref resides. For easy understanding the reference vector is assumed to be situated in sub hexagon with V8as centre making an angle αwith reference d-axis. The procedure and formulae involved to synthesize Vref at a given switching instant is explained in the following steps. Step 1: using the polar from of reference vector |Vref |∠α, sector number and modulation range are identified using (4), (5). S= 1 + fixα π/3,(4) R= 1 + floor|Vref | 0.866 .(5) Tab. 4: Lookup table of input voltage vectors for generation of NSS Sector no. Input Vectors (IV1, IV2) 1IV1= (100), IV2= (110) 2IV1= (110), IV2= (010) 3IV1= (010), IV2= (011) 4IV1= (011), IV2= (001) 5IV1= (001), IV2= (101) 6IV1= (101), IV2= (100) Tab. 5: Selection of Switching States with Conventional 0127 Sequence in S1 Zero Active sates Zero Range NSS Triangle sates sates (R) (T) State State State State ’0’ ’1’ ’2’ ’7’ 1V01 222 322 332 333 1 100 200 210 211 2V12 100 110 210 211 6 110 210 211 221 V21 110 210 220 221 1 200 300 310 311 V72 200 210 310 311 6 210 310 311 321 3V81 210 310 320 321 2 210 220 320 321 V96 220 320 321 331 1 220 320 330 331 To identify the sub hexagon in which the reference vector resides at a given switching instant the possible centre vector states around which a sub hexagon exists is to be identified. For instance if R= 3,V7,V8, and V9are such possibilities. During transit of reference vector along different sectors these voltage vectors are necessary. These are fed in the form of look-up table given in Table 4. Step 2: The lookup table to identify the input vectors IV1and IV2is given in Table 3. From Table 3, identify the input vectors at a given switching instant. Step 3: Given sector number and input vectors IV1 and IV2, a matrix, [SS]Rx3containing the probable nearest switching states are synthesized using the following set of equations, given in (6). X= (R−1) ∗IV1 R p=1SSp=X−(p−1) ∗∆.(6) where ∆=(IV1∼IV2) Step 4: Distance matrix, dRx1with distance from each switching state to the reference vector state as elements is synthesized using (7). R p=1dp=|Vref −SSp|.(7) Step 5: Identify the nearest switching state (NSS) which is at a minimum distance from the reference vector. This becomes the centre of the sub hexagon in which the tip of reference vector is lying at a given instant. Step 6: The reference vector is shifted to the sub hexagon with NSS as centre, the d-q axis components of shifted reference vector are obtained using (8). V′ ref,d =Vref,d −NSSd, V′ ref,q =Vref,q −NSSq.(8) Here V′ ref,d,Vref,d,NSSdand V′ ref,q,Vref,q,NSSqare the d-q axes components of shifted reference vector, original reference vector and NSS respectively. Now the shifted reference vector is given by (9). V′ ref =V′ ref,d +jV ′ ref,q (9) Step 7: From the d-q axis components the triangle T in which the shifted reference vector is lying at a given instant is found using (α′) α′= tan−1V′ ref,q V′ ref,d , T= 1 + fixα′ π/3.(10) Step 8: Knowing the sub hexagon and triangle in which the tip of the shifted reference vector lies, the corresponding nearest switching states to synthesize the reference vector are drawn from the look-up table given in Table 5. Step 9: Once the switching states to be executed are identified, the reference vector V′ ref is to be synthesized using the switching states by satisfying the volt-sec balance condition similar to the two-level space vector PWM. The switching states are to be alienated as active switching states and zero switching sates. Based on position of reference vector in different regions (R1 ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 206 REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER Fig. 5: Zoomed potion of four-level space vector plane in sector S1. to R3) active vectors and zero vectors are interchangeably used. For simplicity the active sates and zero states in sector S1 shown in Fig. 5 are tabulated in Table 4. As all the sectors (S1-S6) are symmetrical, remaining states can be further tabulated. Step 10: Knowing the magnitude, position and nearest switching states of the |V′ ref |∠α′, the active state and zero state switching times for executing a given sequence is calculated in an average sense. The resulting active vector times and zero vector times are given 11. Here Ta,Tband Tzare the active state vector and zero state vector dwell times in a given triangle. Ta=|V′ ref | ∗ Ts∗sin(pi/3−α′) sin(π/3) ,(11a) Tb=|V′ ref | ∗ Ts∗sin(α′) sin(π/3),(11b) Tz=Ts−Ta−Tb,(11c) T7= 0.5Tz, T70 = 0.5Tz.(11d) Step 11: Now the basic PWM technique can be implemented by selecting the switching sates in one switching cycle as in the first column of Table 5. Here in a given switching cycle first zero state is selected flowed by two active states and zero state. As the zero sates are sleeted at the starting and ending of the switching cycle, the zero state time is divide into two equal half’s as in 11(d). For this type of switching state in a switching cycle the PWM technique is named as sequence 0127. Furthermore the approach can be extended to other PWM sequences like bus-clamping (012, 721) involving only one zero state, double-switching bus-clamping sequences involving one zero state and division of either of the active states (0121or 1012, 7212 or 2721). For Fig. 6: Equivalent OEWIM drive circuit powered by dual inverter when both inverters are switched with the same impulse model. Tab. 6: Selection of Switching States with Conventional 0127 Sequence in S1 NSS R T Sequence 0127 012 7212 1 100-200100-200110-210V1210-110 210 200-210 2 110-110110-110200-2102 210-200 210 110-210 6 110-210110-210221-211V2211-221 211 210-211 1 110-210110-210221-220220-221 220 210-220 simplicity the execution of different sequences with reference vector centering at NSS as V1,V2and transiting through different triangles in range 2 is depicted in Table 6. For simplicity the conventional 0127 sequence is considered in this paper. A similar approach can be extended to any PWM sequence with a constraint that it has to maintain volt-second balance in every switching cycle. 5. Analysis of overcharging with different PWM techniques The asymmetrical configuration of the dual inverter suffers from a major limitation i.e. overcharging of DC link capacitor [20]. This occurs when switching of two inverters happens with same switching states. The equivalent circuit so formed during this switching cycle is shown in Fig. 6. In [20] overcharging of DC link capacitors during various switching cycles is addressed for pulse generation through the traditional carrier comparison approach. In the switching duration where both inverters are conducting the two DC link capacitors C1and C2come in parallel with respect to ab and a’b’ respectively. This causes the C2 to overcharge at a voltage greater than Vdc/3 up to 2Vdc/3. This in turn interrupts the maintenance of DC link voltages in the ratio of 2:1. Since the pulse ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 207 REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER pattern adapted for the asymmetrical topology is different with the symmetrical topology [20], in this mode of operation it behaves as if asymmetrical pulse pattern is applied to symmetrical topology. The RMS output voltage becomes zero with this operation. To mitigate this problem some redundant switching states are to be eliminated. From Table 1 and Fig. 3 it is observed that switching states 211, 221, 121, 122, 112 and 212 will generate same pulse pattern to both the inverters. When these switching states are applied the equivalent circuit will be similar to Fig. 6 with sequential change in phase windings connected to C1and C2. From Fig. 3 it is observed that these switching states are positioned at the six corners of a center most hexagon. With the elimination of these switching states overcharging can be eliminated. 5.1. Digital coupled space vector PWM In the proposed digital approach, as discussed in Section 4. , the realization of inverter output is decided by the magnitude and position of the reference input (Vr). The nearest switching states are selected to reduce the output ripple. When the reference voltage lies in regions R1 and R2 the over-charging, switching states may become the closest states. As a result, C2 gets overcharged. When the reference vector lies in region R3 over-charging switching states will not be the nearest switching states. Consequently, overcharging of the C2 is not observed in R3 In Fig. 3 it is observed that there are three redundant states available at the vertices of the inner most hexagon that can synthesize same output voltage. Among the available three redundant states one state is selected based on the criteria "single switch transition at a time". The resulting switching states in sector S1 after satisfying the conditions is given in Table 5. It is observed that over-charging switching state is selected from three switching states. To eliminate those overcharging switching states in the proposed multilevel digital space vector approach “one switch transition at a time” conditions is not considered. The switching states used for 0127 sequence after eliminating overcharging switching states are given in Table 7. The replaced switching states are highlighted bold (red in color) in Table 7. As the over-charging switching states are eliminated from the total possible switching states, DC-link capacity is maintained as 2:1. The only disadvantage with the elimination of over-charging switching states is that switching losses may slightly increase as the criteria "one switch transition at a time" is not satisfied. Tab. 7: Selection of Switching States with Conventional 0127 Sequence in S1 for the Elimination of Over-Charging Zero Active sates Zero Range NSS Triangle sates sates (R) (T) State State State State ’0’ ’1’ ’2’ ’7’ 1V01 222 322 332 333 1 100 200 210 322 2V12 100 110 210 322 6 110 210 322 322 V21 110 210 220 322 1 200 300 310 311 V72 200 210 310 311 6 210 310 311 321 3V81 210 310 320 321 2 210 220 320 321 V96 220 320 321 331 1 220 320 330 331 Fig. 7: Prototype model of dual inverter fed open end winding induction motor drive 5.2. Digital decoupled space vector PWM As disused in section 3. a phase difference of 1800 is considered among the input voltage vector of the first inverter (Vref1) and second inverter (Vref2). If the phase shift is ignored both the inverters will operate with same switching states. (i.e reference vector lies in sector 1 then the switching states would be (8127) for inverter-I and (8’ 1’ 2’ 7’) for inverter-II). When both inverters are operated by same switching states equivalent circuit similar to that of the circuit shown in Fig. 6 will be formed. Hence over-charging of DClink capacitor is observed with 00 phase shift among the reference voltage vectors. Among different phase shifts, a phase shift of 1800 is considered to get maximum output voltage. With the phase shift of 1800 the switching states would be (8127) for inverter-I and (8’ 4’ 5’ 7’) would be for inverterII. With such a switching combination overcharging is eliminated, but the switching states may generate high magnitude of voltage steps [17–19]. This may lead to poor quality of output voltage and high total harmonic distortion. Hence digital decoupled PWM with phase shift of 1800 will eliminate overcharging of capacitors, but results output voltage with high harmonic content when compared to digital coupled space vector PWM. ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 208 REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER 5.3. Two-level modulating signal based carrier comparison approach With two-level modulating signal based carrier comparison approach the selection of all of all possible switching states is not possible. With the realization of control signals using the modulating signal shown in Fig. 4 possibility of charging of capacitors beyond their capacity may takes place [20]. This can be addressed with discontinuous modulating signal based PWM techniques and is considered in the literature [20]. The disadvantage of this approach is required switching states cannot be selected. Hence scope of the PWM technique is limited to extend. 6. Results and Discussion The hypothetical analysis of various PWM techniques fed to the proposed induction motor drive with open end terminals by two inverters feeding the drive is carried in MATLAB. The algebraic expression of phase voltages expressed in terms of pole voltages are shown in (12). The zero sequence voltage for the said drive using (12) is formulated in (13). The phase voltages and zero sequence voltage for different switching states in sector S1 is given in Table 8. Similarly, it can be calculated for remaining switching states using (12) and (13). Vaa′=2 3Vaoa′o′−1 3Vbob′o′−1 3Vcoc′o′, Vbb′=2 3Vbob′o′−1 3Vaoa′o′−1 3Vcoc′o′,, Vcc′=2 3Vcoc′o′−1 3Vbob′o′−1 3Vaoa′o′.(12) VZSV =VZSV 1−VZSV 2, VOO′=Vao −Va′o′+Vbo −Vb′o′+Vco −Vc′o′ 3, =Vaoa′o′+Vbob′o′+Vcoc′o′ 3.(13) To validate the hypothetical analysis a prototype model of the drive is developed. The built in prototype model is shown in Fig. 7. In the prototype mode DC-link inverters of 9.2 kVA are connected to 415V, 50Hz and 10A rated drive. The DC link converter uses a SKYPER 32R driver IC to provide a dead time of 4.3µsec. This dead time had kept constant for all present PWM techniques. The PWM signals for DClink dual inverters are synthesized using control board, dSPACE 1104. The switching frequency of the pulse signals is fixed at 1 kHz. A DC voltage of 510V is shared among the inverters in 2:1 ratio of to both the inverters. To capture the results a voltage regulator Tab. 8: Calculation of Phase A Efficient Pole Voltage in dual inverter with Asymmetrical Configuration. SwitchEffecZero SwitchEffecZero ing tive sequence ing tive sequence states phase voltage states phase voltage voltage voltage 000 0 -Vdc/3 200 4Vdc/9 -Vdc/9 111 0 0 311 4Vdc/9 2Vdc/9 222 0 Vdc/3 321 3Vdc/9 3Vdc/9 333 0 2Vdc/3 210 3Vdc/9 0 100 2Vdc/9 -2Vdc/9 331 Vdc/9 4Vdc/9 211 2Vdc/9 Vdc/9 220 Vdc/9 Vdc/9 322 2Vdc/9 4Vdc/9 300 6Vdc/9 0 332 Vdc/9 5Vdc/9 310 5Vdc/9 Vdc/9 221 Vdc/9 2Vdc/9 320 4Vdc/9 2Vdc/9 110 Vdc/9 -Vdc/9 330 Vdc/9 3Vdc/9 (a) (b) (c) Fig. 8: DC-link capacitor voltages of inverter-I and Inverter-II with different PWM techniques (a) Digital Decoupled space vector PWM (M=0.52) (b) Two-level modulating signal based carrier comparison approach (M=0.52) (c) Digital coupled space vector PWM (at M=0.67, M=1.56, M=2.49). LV20-P (500 V to 3.3 V) and current sensor (50A to 3.3 V with one turn) LA-55P are used. The DC-link voltages of two inverters with various PWM techniques are shown in Fig. 8 at varied modulation values. The captured results from 1 MHz Tetronix DSO are made available in Fig. 8 and are compatible with the simulation study and the concept discussed in section 5. . The DC-link voltages of two inverters with various PWM techniques are shown in Fig. 8 at varied modulation values. The captured results from 1 MHz Tetronix DSO are made available in Fig. 8 and are compatible with the simulation study and the concept discussed in section 5. With decoupled and coupled space vector PWM techniques the overcharging of two capacitors C1 and C2 is controlled in the entire modulation range. To validate the test results the capacitor voltage levels ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 209 REDDY, M. H. et al. VOLUME: 22 |NUMBER: 3 |2024 |SEPTEMBER (a) (b) (c) (d) Fig. 9: Pulse pattern for inverter-I and inverter-I with different PWM techniques (a) Digital decoupled space vector based PWM technique at M=0.83 (b) Digital coupled space vector based PWM technique at M=2.49 (c) Digital coupled space vector based PWM technique at M=1.56 (d) Digital coupled space vector based PWM technique at M=0.67. are shown in Fig. 8(a) and Fig. 8(c) and are maintained at 2:1 ratio. There is a substantial amount of improvement when compared with two-level modulating signal based carrier comparison approach. This is because in that method only for a limited modulation range, greater than 0.9 the overcharging of capacitors is avoided. But for the remaining range it is seen prominently [20]. Fig. 8(b) depicts that the DC link voltage of C2 has overcharged to the voltage equal to that of C1 resulting in violating the principle asymmetrical dual inverter operation of maintaining 2:1 ratio. The experimental results of pulse pattern to inverters, various voltages and currents of the drive fed with two inverters integrated with digital space vector based PWM technique at different modulation index are shown in Fig. 9 and Fig. 10. From the pulse pattern of digital decoupled space vector PWM shown in Fig. 9(a), it is concluded that both inverters are continuously switched at all the modulation indices. Because of this continuous switching pattern the six corner voltage vectors of outer most hexagon (V19, V25...) and center most voltage vectors (V0) will be selected or used to constitute effective voltage of dual inverter. Because of the selection of non nearest voltage vector of three-level space vector plane these are a high error voltage between instantaneous applied voltage vector and reference voltage vector. Hence the high magnitude of voltage levels will be created in the voltage plots. With digital decoupled space vector PWM the effective phase voltage plot shown in Fig. 10(a),(i) is having a voltage step of magnitudes 6Vdc/9, 4Vdc/9, 2Vdc/9 and Vdc/9 at all the modulation indices. The obtained voltage levels or steps in the effective phase voltage plot are same as the theoretical calculations given in Table 8. From the pulse pattern of digital coupled space vector PWM shown in Fig. 9 (9(b), 9(c), 9(d)), it is observed that both inverters are not continuously switched. Moreover, it is also observed from the analysis that all the possible nearest voltage vectors are used to constitute effective voltage of dual inverter. Hence the magnitude of the error voltage vector is less and this lead to low magnitude of voltage step. With digital coupled space vector PWM is shown in Fig. 10(b), (i) effective phase voltage is having a voltage step with magnitudes 2Vdc/9 and Vdc/9 at all the modulation indices. Hence, with both the digital PWM techniques numbers of voltage levels or steps are same, but the magnitudes of voltage steps are different. With a high magnitude of voltage steps 5Vdc/9, 4Vdc/9 total harmonic distortion (THD) is high with digital decoupled space vector PWM when compared to digital coupled space vector PWM. The same can be observed from THD plots shown in Fig. 10. From, Fig. 10 (10(c), 10(d)) it is observed that with the change in modulation indices magnitude of voltage step remains same but number of voltage steps are changing with coupled space vector PWM. But with decoupled space vector PWM magnitude of voltage step and number of voltage levels remains same only change will be there in the pulse width [17–19].With digital coupled space vector PWM technique as the modulation index increases voltage THD decreases as observed in Fig. 10(iii) (10(b), 10(c), 10(d)). As voltage harmonics are decreasing current harmonics will also decrease, hence the THD plot shown in Fig. 10(iv) (10(b), 10(c), 10(d)) decreases with increase in modulation index. The calculated zero sequence voltage (ZSV) level for different switching states are given in Table 8. In the proposed digital decoupled PWM technique to eliminate overcharging effect, switching states (211, 221, 121, 122, 112 and 212) are replaced by (322, 332,...). Because of this the magnitude of ZSV is increased from Vdc/9 to 4Vdc/9 or 2Vdc/9 to 5Vdc/9. Hence an increase in magnitude of 3Vdc/9 is observed, which may lead to increased stress on isolation transformer. The plots of zero sequence voltage with digital coupled space vector PWM shown in Fig. 10(ii) (10(b), 10(c), 10(d)) at various modulation indices. From the theoretical analysis and experimental results it is observed that in the region R2 the ZSV is high. This is because of non selection of overcharging voltage vectors. The plots of ZSV with digital decoupled space vector PWM is shown in Fig. 10(a)(ii). Because of selection of corner most voltage vectors of the outer most hexagon, the ZSV is having a voltage step of 0, Vdc/9, 2Vdc/9 and 3Vdc/9 constituting a peak to peak magnitude of Vdc/3 over the entire modulation range. ©2024 ADVANCES IN ELECTRICAL AND ELECTRONIC ENGINEERING 210