Design and control of novel grid tied multilevel filter-less inverter using current based sliding mode control

Received 6 October 2022, accepted 25 October 2022, date of publication 31 October 2022, date of current version 8 November 2022. Digital Object Identifier 10.1109/ACCESS.2022.3218338 Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter Using Current Based Sliding Mode Control MUHAMMAD OSAMA SAAD 1, ABASIN ULASYAR 1, WALEED ALI 1, HARIS SHEH ZAD 2, NASIM ULLAH 3, (Member, IEEE), VOJTECH BLAZEK 4, LUKAS PROKOP 4, AND STANISLAV MISAK 4 1Department of Electrical Power Engineering, USPCAS-E, National University of Sciences and Technology (NUST), Islamabad 44000, Pakistan 2Department of Mechanical and Manufacturing Engineering, Pak–Austria Fachhochschule: Institute of Applied Sciences and Technology, Haripur 22620, Pakistan 3Department of Electrical Engineering, College of Engineering, Taif University, Taif 11099, Saudi Arabia 4ENET Centre, VSB—Technical University of Ostrava, 708 00 Ostrava, Czech Republic Corresponding author: Abasin Ulasyar ([email protected]) This work was supported in part by the Doctoral Grant Competition VSB—Technical University of Ostrava, under Grant CZ.02.2.69/0.0/0.0/19_073/0016945; in part by the Operational Programme Research, Development and Education, under Project DGS/TEAM/2020-015; in part by the Partial Discharge Detection in Insulation Systems, National Centre for Energy, under Project TN01000007; and in part by Taif University Researchers Supporting Project, Taif University, Taif, Saudi Arabia, under Grant TURSP-2020/144. ABSTRACT The role of control techniques is increasing due to the high penetration of renewable energy sources at grid level. The importance of inverters also rises as it balances the supply between the renewable source and grid power system. The issues related to penetration of renewable energy like power quality maintenance, protection against the detection of islanding and maintaining the integrity of grid; control techniques play a vital role to solve these problems. This paper proposed an internal control technique known as current based sliding mode control (SMC) for a filter less multilevel inverter (MLI). The aim of proposed research work is to achieve 27 level output voltage by using an inverter, which approaches sinusoidal wave without using any filters. To control the output of MLI, a current based SMC is implemented in order to achieve the robustness, a good dynamic response, a smaller number of voltage ripples and a smaller current THD. Moreover, a comparative analysis of SMC is done with the conventional PI controller. The response of the controller has been investigated for different cases e.g., introducing sag, swell, faults and harmonics in grid level has been implemented on MATLAB/Simulink. To validate the results of SMC for MLI, an experimental setupwas also established which consists of National Instruments (NI) based hardware in loop (HIL) system and dSPACE 1202. The HIL system results show consistency with simulation results. INDEX TERMS Filter less, hardware in loop (HIL), multilevel inverter (MLI), sliding mode control (SMC), total harmonic distortion (THD). I. INTRODUCTION DC to AC power converters are used for integration of renewable energy resources. Traditional two-level inverters have certain drawbacks like high switching losses, high voltage stress, low power quality and high electromagnetic interference, etc. [1], [2]. On other hand, MLIs have better The associate editor coordinating the review of this manuscript and approving it for publication was Zhilei Yao . performance comparatively, and are considered more significant in high voltage and power conversion applications. Despite of its advantages, the main challenges in the design of MLI were complexity, increase in number of switches, and more than one DC sources [3]. In literature, various topologies of MLI were proposed considering different issues. Most of the topologies were derived from three basic topologies i.e. Diode clamped MLI (DCMLI), Flying capacitor MLI (FCMLI) and cascaded H VOLUME 10, 2022 This work is licensed under a Creative Commons Attribution 4.0 License. For more information, see https://creativecommons.org/licenses/by/4.0/ 115555 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter Bridge MLI (CHBMLI) [4]. Out of these basic topologies, CHBMLI is considered as most simple and advanced, while FCMLI and DCMLI topologies have issues regarding capacitor voltage balance when output levels are increased [5]. Based on the value of DC sources, the CHBMLI is classified into two topologies i.e., symmetrical with same value of each DC source and asymmetrical with different DC magnitudes. Kumar et al. [6] discussed hybrid topologies to reduce the number of input DC sources by combining floating capacitors with H bridge, which required a complex modulation scheme to balance capacitor voltage. Chattopadhyay and Chakraborty [7] proposed the level doubling network used with DC sources in the ratio of 1:7 to increase the output levels with a complex capacitor charging technique. Krishnachaitanya and Chitra [8] designed 15-level asymmetric MLI topology using nine switches and three DC sources but the voltage stress on the switches was high. So, it is inferred that the inverter topology with comparatively low voltage on high frequency switches has efficient performance. The switching losses of inverter were reduced by operating high voltage switches with low frequency as compared to low voltage switches [9]. Ziaeinejad and Mehrizi-Sani [10] proposed CHBMLI based on trinary sequence (1:3:9) DC sources were presented which operated at low frequency [11] and had higher level output with a smaller number of switches. In a trinary inverter for nine level output, the conducting switches per level were four as compared to five active switches in other asymmetric topologies [12]. Therefore, CHBMLI have gained considerable attention due to its modular design, simple control, reliability and there are no capacitor imbalance problems. Further trinary asymmetric CHB generates high quality voltage with minimum harmonics. Also, it requires least number of switches and DC sources [13], [14], [15]. Moreover, the complex mathematical process was previously required for finding switching angles for trinary CHB inverter [16]. Vargas et al. [17] introduced a sinusoidal pulse width modulation (SPWM) technique developed for 9 level trinary inverter by applying logical operations on carrier waves. Among different techniques of SPWM, carrier distribution or level shifting offered a superior output voltage with less THD and it is compatible with CHB topology. According to IEEE 1545 standards [18], total harmonic distortion (THD) should be less than 5% at the point of common coupling (PCC). Inverters are interfaced with the grid using filters made up of passive components like capacitors and inductors for THD reduction. Addition of filter results into increment in cost, weight, and power loss of the inverter. Park et al. [19] proposed higher order filter with reduced filter size. However, the higher order filter produces extra resonant peaks which requires a proper damping scheme [20], [21]. THD and filter size can be reduced by increasing the switching frequency but it is inefficient due to rise in switching losses. The wide band gap (WBG) technology-based switches have the ability to operate at much higher frequencies with minimum switching losses. Rockhill et al. [22] proposed that WBG Silicon Carbide (SiC) based inverter could operate at 50 kHz switching frequency in comparison to 16 kHz Silicon (Si) based converter,which reduced the filter size. However, the SiC based inverter is costly and only suitable for high power applications [23]. Therefore, in order to address all these limitations, systems without filters are being proposed. Inverters are mostly integratedwithfeedbackcontrol to stabilize system in accordance with the set parameters. The feedback control uses the difference of actual and the reference value to verify that the reference value is being followed by the system. In literature, many control techniques were used with inverters considering different objectives. Shi et al. [24] proposed feedforward control strategy was implemented with traditional PI control for half bridge three phase inverter, however it required high settling time and high overshoot which adversely affect the performance. In order to obtain low THD, the model predictive control (MPC) was implemented for LC filter based three phase inverter which requires load information and complex calculation for accurate performance [25]. Mohamed et al. [26] discussed a comparison between hysteresis control and space vector PWM (SVPWM) current control was made for grid-connected inverter. The system parameters did not affect the performance of the hysteresis controller and its implementation was also simple. However, variable switching frequency and high ripple current were the shortcomings in this type of controller. Various other controllers have also been used with three phase grid tied inverters such as partial feedback linearization control, H-infinity control and deadbeat control etc, as elaborated by Jena et al. [27]. Yang et al. [28] proposed a novel SMC design for PV based grid-tie inverters, which offered compensation in the fluctuations and external disturbances as well as had an improved error tracking ability. Further, this controller had a relatively easier implementation as compared to other non-linear controllers. Ozdemir et al. [29] proposed a super twisting algorithm of SMC for three-phase grid-tied threelevel neutral point clamped inverters. This controller had less THD and also operated at deteriorated/imbalanced voltages and offered considerable suppression in chattering along with efficient tracking performance. Sebaaly et al. [30] implemented the current based SMC on 3L-NPC. It was observed that there is low THD with respect to grid. Furthermore, in case of DC link voltages, SMC delivered a better response at high switching frequency. Sebaaly et al. [31] proposed space vector modulation-based SMC which was implemented on the 3L-NPC. The SMC controlled the amplitude and phase of the current signal with reduced harmonics. Due to the aforementioned characteristics and nonlinear properties of SMC, the SMC can be utilized for voltage and current regulation. The SMC demonstrated robustness against disturbances in the system and offered quick-dynamic response [32]. The conventional PI controller has many applications but it has some limitations e.g., it has high starting overshoot. It is very sensitive to controller gains and also, its response is very slow towards the external disturbances [33]. On the other hand, SMC shows very quick response towards external disturbances. SMC is very useful for higher order systems 115556 VOLUME 10, 2022 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter FIGURE 1. Circuit configuration of grid connected 27 level CHBMLI. because it replaces the original system with new one with lower order. Moreover, SMC produce the desirable and smooth output power because it is designed by using direct power control. Also, it helps to remove inaccuracy. Due to these features of SMC, it is preferable to implement it on Inverter to control its output Current [34], [35]. The main contributions of this article are as follows: •Trinary based cascaded H-bridge MLI is proposed for filter-less grid tied operations. Logic sum based PWM Technique is designed for Trinary based MLI to achieve 27 level output voltage. •SMC controller was designed for the trinary based CHBMLI, a mathematical model of SMC was derived and simulated for the system, which was not found in literature. Beside this, the SMC is compared with PI controller to demonstrate its effectiveness. •To further validate the simulation results, the topology of CHBMLI in HIL based OPAL RT system and the SMC was tested for CHBMLI by using dSPACE 1202 MicroLabBox. The rest of the study is discussed Section wise. The Mathematical model of CHBMLI topology is discussed in Section 2. The Section 3 focused on the modulation scheme and conduction states of CHBMLI. The discussion on derivation of equations for SMC and their feasibility is mentioned in Section 4. Section 5 explains the simulation results and hardware implementation of HIL system. The conclusion is given in Section 6. II. MATHEMATICAL MODEL OF CHBMLI Figure 1 shows the detailed structure of the proposed three phase grid tied inverter. The trinary asymmetric cascaded H-bridge MLI topology can generate 27 levels. Each bridge is connected with deparated DC source. The line connecting the inverter with the grid has resistance R and some Inductance L. The system equation can be written as:   i0 a i0 b i0 c  =A  ia ib ic  +B  ua ub uc  +C  vag vbg vcg  (1) where A=       −R L0 0 0−R L0 0 0 −R L       ,B=       1 L0 0 01 L0 0 0 1 L       , C= −B The dq model and their equations can be obtained by applying transformation from stationary (abc) to rotatory (dq) frame of reference using the following transfer matrix: T=r2 3   cosθcos(θ−2π 3cos(θ+2π 3 sinθsin(θ−2π 3sin(θ+2π 3   (2) After applying Park’s transformation, the system’s equation in matrix form can be written as: i0 d i0 q=Xid iq+YUd Uq+ZVgd Vgq(3) where X=   −R Lw −w−R L   ,Y=  1 L0 01 L  ,Z= −Y VOLUME 10, 2022 115557 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter FIGURE 2. Trinary cascaded H-bridge topology. In Eq (1), uabc shows the inverter output voltage, vgrid,abc shows the grid voltages and Ris the resistance and Lis the inductance through which inverter is connected to the grid. A. CHB TOPOLOGY Figure 2 displays the CHB topology for single phase. The asymmetric configuration possesses DC sources with different magnitudes. This topology utilizes a smaller number of components with ability to produce higher number of the voltage levels. The trinary sequence uses three DC sources in the ratio 1:3:9. The DC voltages are set in accordance with desired output voltage levels. For example, Vdc1=1Vdc, Vdc2=3Vdc and Vdc3=9Vdc. The specific voltage levels e.g., ±Vdc,±2Vdc,±3Vdc and ±4Vdc etc, can be achieved by selecting DC sources along with appropriate switching sequence. The output voltage levels can be increased by addition of DC voltage sources along with the switches. For achieving 27 levels, 12 switches and 3 voltage DC sources are used. For n DC sources, the output voltage level is given by Eq (4) VoltageLevels =3n(4) where nshows the number of DC sources. The sequence of DC source across each cell of inverter is indicated by Eq (5). Vdck =3k−1Vdc (5) where k=1,2,3. . . , Lwhich represents the sequence of DC source across the bridge and Vdc is the DC voltage across CHBMLI topology. The formula to achieve maximum magnitude of output voltage levels is represented by Eq (6). Vo=(3n−1)Vdc/2 (6) III. MODULATION SCHEME In this research, a multi carrier phase disposition (PD) technique was used in which all the carrier waves are in phase. FIGURE 3. Scheme for multi carrier phase disposition to achieve 27 levels. To achieve the required PWM signals for switches, a low frequency sinusoidal reference signal was compared with triangular carrier signals having high switching frequency as revealed in Figure 3. Since for N level MLI, N-1 carrier waves are required to generate PWM waves. To achieve 27 levels, 26 carrier signals are compared with reference signal to produce 26 command signals. In single phase, there are 12 switches. Therefore, some digital logic-based operations are required to convert the 26 command signals into the 12 driving gate signals for the single-phase inverter design. It will guarantee a voltage output signal with 27 levels. The remaining two phases will be switched using a similar method, making a total of 36 switches in a three-phase system [17]. The Eq (7-18) indicates the gate signals for switches in which C1,C2,C3,...,C26 are the command signals. S11 =C1⊗C7⊗C4⊗C3⊗C6⊗C10 ⊗C16 ⊗C13 ⊗C12 ⊗C15 ⊗C19 ⊗C25 ⊗C22 ⊗C21 ⊗C24 ⊗C9⊗C18 (7) S12 =C2⊗C8⊗C5⊗C3⊗C6⊗C11 ⊗C17 ⊗C14 ⊗C12 ⊗C15 ⊗C20 ⊗C26 ⊗C23 ⊗C21 ⊗C24 ⊗C9⊗C18 (8) S13 = ∼ S11 (9) S14 = ∼ S12 (10) S21 =C3⊗C21 ⊗C9⊗C12 ⊗C18 (11) S22 =C6⊗C24 ⊗C15 ⊗C9⊗C18 (12) S23 = ∼ S21 (13) S24 = ∼ S22 (14) S31 =C9(15) S32 =C18 (16) S33 = ∼ S31 (17) S34 = ∼ S32 (18) In Eq (7-18), it can be seen that XOR operation is applied on 26 command signals. In Upper bridge with low DC source, the switches have more command signals as compared to switches in other bridges with higher DC sources. These specific command signals decide the state of specific switch with goal to achieve 27 level output signals. 115558 VOLUME 10, 2022 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter FIGURE 4. Conduction path followed by switching signals (a) output voltage levels =13 (b) output voltage levels = −13 (c) output voltage levels = +1 (d) output voltage levels = −1 (e) output voltage levels =0. TABLE 1. Conduction states of MLI. Table 1 shows the conduction states for the MLI. H1, H2and H3shows the H-bridges across which DC sources are connected. The states of these H-bridges decide the levels of output voltage waveform. Only two switches of each bridge are shown in table, rest of the switches states are complementary e.g., S13 and S14 are complementary to S11 and S12. To attain 27 levels, 12 switches were used. It means 212 =4096 combinations can be made in which 64 conduction states are possible for this CHBMLI topology. Rest of 4032 combinations will cause either short circuit or open circuit and no output levels can be produced. Figure4showsthe conduction paths for +13,−13,+1,−1 and 0V. The rest of conduction paths can be drawn in similar way. The highlighted path with arrow shows the direction of current flow through the load. The positive flow of current through load shows positive voltage level and the reverse flow of current through load shows negative voltage level IV. SLIDING MODE CONTROL Sliding mode Control causes the system’s state trajectories to move in the direction of a sliding surface. In the direction of the equilibrium point, the states start to slide once they reach the sliding surface. The sliding surface must be selected in accordance with the system. Then a control law is constructed that compels states to move in the direction of the sliding surface. In this research, a SMC is designed to track output current of the inverter. The derivative current i0 d,i0 qcan be written as: i0 d=1 L[Ud−Vgd −Rid+ωLiq] (19) i0 q=1 L[Uq−Vgq −Riq−ωLid] (20) VOLUME 10, 2022 115559 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter FIGURE 5. Control schematic diagram. In dq frame of reference, two sliding surfaces are required. Sdrepresents the sliding surface in d-axis, which controls the direct current and Sqis the sliding surface in q-axis, which controls the current in the q-axis. Similarly, i(d,ref )and i(q,ref ) are the reference currents in d and q-axis. The sliding surface is indicated by Eq (21). S=λe(21) where λis the sliding coefficient and e is the error, which is the difference between reference current and actual current. Sd=λ(id−id,ref ) (22) Sq=λ(iq−iq,ref ) (23) The control law should satisfy the condition where S0 dand S0 q should be equal to zero. S0 d=λi0 d=0 (24) S0 q=λi0 q=0 (25) By putting values of Eq (19,20) in Eq (24,25), S0 dand S0 q becomes S0 d=λ L[Ud−Vgd −Rid+ωLiq] (26) S0 q=λ L[Uq−Vgq −Riq−ωLid] (27) The stability and reachability criteria can be achieved by following conditions: SdS0 d<0 (28) SqS0 q<0 (29) It can be written in term of function as SdS0 d=Sd(−KdSd−Mdsgn(Sd)) <0 (30) SqS0 q=Sq(−KqSq−Mqsgn(Sq)) <0 (31) −KS −Msgn(S) is the reaching law equation proposed by Sreekumar and Jiji [33]. This law presume that operations will occur in three modes i.e., reaching, sliding and steady state mode, beginning at any moment within a finite period of time. To reduce chattering effect, K should be greater than M. Furthermore, Md,Mq,Kdand Kqare the control variables and the following conditions can be applied on these variables to prove stability and reachability criteria. −Kdq|Sdq| − Mdq <0 (32) Kdq|Sdq| + Mdq <0 (33) Md>0,Mq>0,Kd>0,Kq>0 The selection of the values for control parameters is one of the important tasks because higher values cause the chattering problem as well as it reduces the dynamic response. On the other hand, smaller values cause the problems related to the convergence of the controller. So, tradeoff between the values has to be made By rearranging Eq (26,27), the equations for control law will be derived as: Ud=L λ×(−KdSd−Mdsgn(Sd)) +Vgd +Rid−ωLiq (34) Uq=L λ×(−KqSq−Mqsgn(Sq)) +Vgq +Riq+ωLid (35) Udrepresents the control law for d-axis and Uqrepresents the control law for q-axis as shown in Figure 5. V. RESULTS AND DISCUSSION The output of each individual H-bridge is shown in Figure 6. The Bridge 1 has lower voltage of 23 V and high switching rate. The bridge 2 has higher DC voltage of 69 V and comparatively low switching rate. Finally, the bridge 3 has higher 115560 VOLUME 10, 2022 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter FIGURE 6. Output of each individual bridge. FIGURE 7. 27 level inverter output waveform. DC voltage of 207 V and lowest switching rate among all the bridges. At higher voltages, higher switching rate causes more losses. So, in this topology the switching rate of higher voltage bridge is low and vice versa. There is tradeoff between switching rate and voltage of the bridge. This is the advantage of this topology and also the digital logic design (DLD) logics plays a vital role in order to reduce the number of switching gate signal as well as the losses of overall the inverter topology. Figure 7 shows the output voltage of trinary inverter for phase A, which is the summation of three individual H-bridges. It can be seen that total output levels are 27 and output voltage is 300 V which is the sum of individual DC voltages. In order to check the performance of proposed SMC, the comparisonwasmadebetweenconventionalPI controller and SMC.The PI controller was designed in Matlab/Simulink and it is used to control the output current of CHB MLI. The transfer function of the grid connected system was derived based on the values of the line resistance and line inductance as shown in Eq (36). By using this transfer function, the tuning of PI controller was done in Matlab/Simulink. In our research work, the value of Kpand Kiare 0.208 and 104.28 respectively. H(s)=1 0.0012s+0.2(36) TABLE 2. System parameters. FIGURE 8. Output current under NGO (a) dq Current for PI controller (b) dq current for SMC. Table 2 represents the design variables for PI controller and SMC. Simulation results are based on it. For SMC, it was observed that steady state error and chattering effect decreases for large values of Kdand Kq. The percentage overshoot is small for large values of λ. On the other hand, large value of Mdand Mqgives small percentage overshoot but high-rise time. So, trade-off has to be made between different control design parameters to achieve best results. The controller results were obtained for different operating conditions by using the design control parameters as shown in Table 2. Different operating conditions include normal grid operations (NGO) in which grid voltage contains no harmonics. Also, step response is added for variations in currents under NGO. At abnormal grid operations (AGO), 5% of 3rd,5th and 7th order harmonics are injected at grid voltage. Further, 20 % of sag and swell are also introduce at grid level in order to investigate the behavior of controllers. Figure 8 shows inverter current response under NGO. Figure 8(a) shows the dq current for PI and 8(b) shows the response of current for SMC controller. By analyzing the VOLUME 10, 2022 115561 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter FIGURE 9. Variation in output reference current under NGO (a) dq current for PI controller (b) dq current for SMC. FIGURE 10. Output current under AGO (a) dq current for PI controller (b) dq current for SMC. simulation results for PI under NGO, the rise time and percentage overshoot for current Idare observed to be 12.02ms and 13.06% respectively, whereas the fall time and percentage undershoot for current Iqis 2.72ms and 75.45%. The settling time of 60ms has been recorded. For SMC controller, It is observed that the rise time and percentage overshoot for current Idis 1.16ms and 3.62% whereas the fall time and FIGURE 11. Output current under sag condition (a) dq current for PI controller (b) dq current for SMC. FIGURE 12. Output current under swell condition (a) dq current for PI controller (b) dq current for SMC. percentage undershoot for current Iqis 0.3ms and 24.37% respectively. The settling time of 5ms has been recorded. Figure 9 shows the result for variation in output currents at NGO condition. The variation in reference current is made by applying step input at 0.15s. It can be observed in figure 9(a) that the rise and fall time of the Idand Iqis 12.1ms and 2.75ms. An overshoot of 13.06% and undershoot of 74% is 115562 VOLUME 10, 2022 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter FIGURE 13. THD of inverter current using SMC under NGO. FIGURE 14. THD of inverter current using SMC Under AGO. FIGURE 15. THD of inverter current using PI controller under NGO. FIGURE 16. THD of inverter current using PI controller under AGO. observed for Idand Iqfor PI controller. Figure 9(b) shows the current response for SMC controller where rise and fall time of current Idand Iqis 1.15ms and 0.3ms.An overshoot of 3.6% and undershoot of 24.4% is observed. Figure 10 shows the results for output currents at AGO condition. Figure 10(a) indicates the effect of current FIGURE 17. Grid voltages under AGO. FIGURE 18. Grid voltages during sag. FIGURE 19. Grid voltages during swell. during PI controller and 10(b) indicates the output current for SMC controller. For PI controller, It is observed that the rise time and percentage overshoot for current Idis 11.89ms and 14.36% whereas the fall time and percentage undershoot for current Iqis 1.14ms and 24.74% respectively. The settling time of 19.154ms has been recorded. For SMC, the rise time and percentage overshoot for current Idis 1.126ms and 1.91% whereas the fall time and percentage undershoot for current Iqis 0.290ms and 40.14% respectively. Figure 11 shows the results for sag condition at grid level. Figure 11(a) indicates the effects on output current during sag for PI controller. Figure 11(b) shows the effects during SMC controller. It is observed that the rise time and fall time of the currents Idand Iqis 11.66ms and 1.99ms under PI controller. An overshoot of 13.11% and undershoot of 134.79% is observed for Idand Iq. On the other hand, for SMC controller the rise and fall time of the Idand Iqis 1.044ms and 0.56ms. An overshoot of 0.115% and undershoot of 45.84% is observed for Idand Iq. The transients can be observed at the time when sag is introduced at grid for PI controller. But VOLUME 10, 2022 115563 M. O. Saad et al.: Design and Control of Novel Grid Tied Multilevel Filter-Less Inverter WALEED ALI received the bachelor’s degree in electrical engineering from Air University, Islamabad, Pakistan, with a focus on power engineering, the M.S. degree in electrical engineering from the National University of Sciences and Technology (NUST), Islamabad. His research interests include the Internet of Things (IoT), inverters, machine learning in power systems, and smart grid. HARIS SHEH ZAD was born in Pakistan. He received the B.S. degree in electrical engineering from the University of Engineering and Technology, Peshawar, Pakistan, in 2009, the M.S. degree in electrical engineering from the University of Engineering and Technology, Taxila, Pakistan, in 2012, with a focus on control, and the Ph.D. degree in electrical and electronics engineering from Koç University, Istanbul, Turkey, in August 2017, with a focus on control systems and automation. From 2009 to 2013, he served as a Lecturer with Riphah International University, Islamabad, Pakistan. From 2013 to 2017, he worked as a Research Assistant with the Manufacturing and Automation Research Center (MARC), Koç University. From 2017 to 2021, he worked as an Assistant Professor with the Electrical Engineering Department, Riphah International University. He is currently an Assistant Professor with the Department of Mechanical and Manufacturing Engineering, Pak–Austria Fachhochschule: Institute of Applied Sciences and Technology, Haripur, Pakistan. His research interests include electric vehicles, converters, inverters, permanent magnet motors, magnetic bearings, bearing less motors, third generation left ventricular assist devices, magnetic circuit design, analysis of systems using numerical methods, finite element analysis methods, mathematical modeling, and control of linear and non-linear systems. NASIM ULLAH (Member, IEEE) received the Ph.D. degree in mechatronic engineering from Beihang University, Beijing, China, in 2013. From September 2006 to 2010, he was a Senior Design Engineer with IICS, Pakistan. He is currently working as an Associate Professor of electrical engineering with Taif University, Saudi Arabia. His research interests include renewable energy, flight control systems, integer and fractional order modeling of dynamic systems, integer/fractional order adaptive robust control methods, fuzzy/NN, hydraulic and electrical servos, and epidemic and vaccination control strategies. VOJTECH BLAZEK was born in the Czech Republic, in 1991. He received the Ing. degree from the Department of Electrical Engineering, VŠB—Technical University of Ostrava, in 2016. He is currently an Internal Doctoral Student and a Junior Researcher with the Research Centre ENET–Energy Units for Utilization of Non-Traditional Energy Sources, VŠB— Technical University of Ostrava. His current research interest includes developing modern and green technologies in off-grid systems with vehicle to home technologies. LUKAS PROKOP graduated the Ing. degree majoring in electrical power engineering from FEEC Brno. He was an Associate Professor at FEI TU Ostrava. He is currently engaged in renewable energy sources, modern technologies, and methods in electrical power engineering and electrical measurements. He is a research team member of Czech and international research projects. He serves as the Deputy Head for the ENET Research Centre. STANISLAV MISAK was born in Czech Republic, in 1978. He received the Ing. and Ph.D. degrees from the Department of Electrical Engineering, VŠB—Technical University of Ostrava, in 2003 and 2007, respectively. He is currently a Professor at the VŠB—Technical University of Ostrava and the CEO of the Research Centre ENET and Centre for Energy and Environmental Technologies. He holds a patent for a fault detector for medium voltage power lines. His current research interests include the implementation of smart grid technologies using prediction models and bio-inspired methods. 115570 VOLUME 10, 2022